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Microcontroller Systems

Engineering Science

2nd year A2 Lectures

Prof David Murray

[email protected]/∼dwm/Courses/2CO

Michaelmas 2014


Introduction


Introduction

The development of the the digital computer must rank as one of thetwo engineering achievements that have had the most profoundimpact on the progress of the 20th century.

Open up the box on any computer, and one is likely to be impressedbut also daunted by the sheer complexity — even of what one cansee.

You’re looking at the cumulative wizardry of, say, 106 to 107

engineer-years of development.

* Not surprising if you personally could not reproduce it tomorrow.


IntroductionBut computers are so commonplace in office and domestic settingsthat when asked

“how does a computer work?”

you — even as engineers — probably start thinking along the “IT”lines of the sketch

That is — what peripheral plugs into what socket, etc.

Dull, dull, dull


Much more interesting and relevant is ...

How do computers function in an engineered system?

Short answer is that they provide

on the input sidea means of high-bandwidth data acquisition from sensors⇒A2 Signal Conditioning Lectures

internallya flexible firmware tool for real-time data analysis⇒these lectures

on the output sidea means to control a plant⇒A2 Control Lectures


Changing nature ...The ability to sense, compute, and actuate in real time allows youliterally to change nature.

Control engineers work to turn naughty transfer functionsintowell-behaved, predictable, stable, engineered on

Badly behaved

Engineered transfer function

Well behaved

Plant’sTransfer Function

Transfer FunctionPlant’s

Controller

Sensing


Changing nature ...Simple compensators can use analogue, but more sophistication,flexibility, etc created using a digital compensator.

Engineered transfer function

Well behaved

Computer Controlled



Controller

Computer

DAC

then

ZOH

S&H+ADC

S&H+ADC

Sensing

Sensing

That is, a computer surroundedon the input side by a Sample-and-Hold and an ADCon the output side by a DAC and Zero-order-Hold


Computers as part of the engineered machinePlanes, trains and automobiles, for sure ...

... but also Civil engineering – Taipei 101 – huge, scary, but simple

M1 M2

K1

c1

Controller

Fluid

Servo Valve

Sensors


Microcontroller systems

These four lectures are NOT about control, but will introduce you tohow a simple computer does its job in hardware.

Our focus is on simple computers which, though general purpose, areprogrammed to perform a particular set of tasks.

Such microcontrollers are oftenbundled together with input/outputdevices and memory into a singlemulti-pin package, costing £1-5.

They get embedded in a huge va-riety of machinery ranging in com-plexity from central heating boilersto nuclear power stations, etc


Microcontrollers

Some bad news — “simple” in this area is all relative. Excludingmemory, 8-bit microcontroller contains ∼ 0.1× 106 transistorsSounds substantial, until you compare with your desktop ...

Clock Processor Year Millions of ProcessSpeed transistors nm0.03 80486 1989 1 10000.07 Pentium 1993 3 8000.2 Pentium II 1997 8 5000.5 Pentium III 1999 10 2502.2 Pentium IV 2000 40 1803.0 CoreDuo 2006 290 653.6 Core i7 2008 780 453.8 Core i7 2011 2270 32? Itanium 2012 3100 32? Xeon Phi 2012 5000 22? Xbox One 2013 5000 28> 3.6 Sparc M7 2014 10000 20GPU Nvidia NV3 1997 4 350GPU Nvidia GK110 2012 7080 28


Microcontrollers

Yes, but even 105 transistors sounds daunting!!

The good news is ...Strip away the froth, and the principles turn out to bestraightforward, and applicable to all scales.

Even more good news ...the P2 course has provided everything you need to start.


Reading

There is no one book that sits comfortably alongside this (very) shortcourse, but I have found several helpful for different parts.

Hill & Peterson “Digital Logic and Microprocessors” Wiley –revision of basic logic components and for RTL.

Clements “Principles of Computer Architecture” OUP. Very clearon components of the CPU.


Course WWW Pages

Pdf copies ofthe notes (including colour and larger print versions)copies of these lecture slidesthe tutorial sheets, plus any corrections and updateshints, FAQs etc,

will be accessible from

www.robots.ox.ac.uk/∼dwm/Courses/2CO

(Only the notes and the tute sheets get put on weblearn.)

If you get really really stuck, email me.If the answer is a useful one, it will get put into the FAQs


Lecture Content

1 From Sequential Logic to a simple Central Processing Unit

2 Registers and Register Transfers in the CPU: how to fetch andexecute instructions

3 The Control Unit, the ALU, and Memory. Memory addressing.

4 I/0, Interfacing and Applications


Lecture 1

From Sequential Logic to a simple CPU

What is a computation?Finite state machinesSeparating control from dataRegister Transfer LanguageData, Control and the Central Processing Unit


What is a computation?


What is a computation?Before getting embroiled in the detail of hardware and so on, it isworth asking

what is meant by a computation?

A computation is the evaluation of some output O from some input I,where these are collections of symbols of some sort.

You can think of the computation as a digital transfer function f

O = f (I)

... one which can be broken down into elemental steps fi

O1 = f1(I) O2 = f2(O1) . . . O = fn(On−1) .

In a binary computer the symbols are likely to be 0’s and 1’s.


What is a computation?Now, you could imagine building different hardware for each fiseparately...

if

Input Output

Transferfunctionselector

f

Input Output

... but the idea of a general purpose computer is to reconfigure thesame piece of hardware to perform different tasks. That piece ofhardware is the central processing unit

Thoughts ...We need a second input to select the transfer function.We also need memory units, so that the Output can be storedbefore changing the transfer function and passing it through theInput again.This is nothing other than a finite state machine.


You knew that already!The P2 Digital Logic course pre-sented a diagram describing howa sequential finite state machinecould be built using combinationallogic and flip-flops.

The flip-flops provided a delay sothat the clock pulse would movethe system on to the next state.

Delay/storage

flip−flops

Logic

Combinational

Inputs Outputs

The lectures ended with the following:

The concept of finite state machines is as the heart of the theory of thecomputer ...

... If we introduce a branching capability which allows the sequence of statesto change according to an input condition ...

we have most elements required for understanding how a computer works ...


Finite State Machines


Branching using discrete combinational logic

Here is a simple example of introducing branching ...

♣ Problem: Using D-type flip-flops, design a modulo-4 counter thatcounts upwards (0,1,2,3,0,...) if input x = 0 but downwards if x = 1.A flag Z output should be set if the count output is zero.

A Solution: We can represent the state diagram as

A/0 B/1 C/2 D/3

x=0

x=1 x=1 x=1

x=1

x=0 x=0x=0

Four states are labelled with name/output; transitions with the input.

Derive the output bits from Q0 and Q1 of two D-types.


/ctdWrite down the D-type’s truth and transition tables, then determinethe values of D1,0 required to generate the sequences of Q1,0 ...

TruthDt Qt+1

0 01 1

TransitionQt → Qt+1 Dt

0 → 0 01 → 0 00 → 1 11 → 1 1

⇒

For x = 0Q1 Q0 D1 D0

0 0 0 10 1 1 01 0 1 11 1 0 0

&

For x = 1Q1 Q0 D1 D0

0 0 1 11 1 1 01 0 0 10 1 0 0

Now build the Karnaugh maps (remembering Gray code!)

For D1:

Q1Q0 → 00 01 11 10x ↓

0 0 1 0 11 1 0 1 0

For D0:

Q1Q0 → 00 01 11 10x ↓

0 1 0 0 11 1 0 0 1

whence

D1 = x .(Q0.Q1 + Q0.Q1) + x .(Q0.Q1 + Q0.Q1) D0 = Q0 Z = Q1.Q0


Using a ROM to create the combinational logic

You also saw in P2 that a quite easy method of building part of thecombinational logic was to use a PROM instead of discrete logicgates.

One part of the contents at a particular address tells youwhat to do now

The other part of the contents tells you the address ofwhere to go next

“Next” means after the next clock pulse.


Using a ROM to create the combinational logicSame problem as before ... but solved using a PROM

To allow branching we introduce alternative “where next” addresses,and x chooses one of them.

ROM

1010

1010

1001

0011

0101

1000

0110

01 0

123

ContentsWhere next? What now?

if x=0 if x=1

Address

AddressLines

0

1

2 2

Pair of D−type latcheswith same CLKMultiplexer

2

CLK

x }

0

1

CountOutput

Z flagOutput

A

A


The Moore fsm modelThe example just seen was typical of a Moore finite state machine.In this

The outputs at a particular time depend only on the current state.The inputs affect which state is reached after the next clockpulse, but don’t affect the current output.The current output is defined by the current state.

A/O

B/O

C/O

1

2

Input=I

Input=I1

2

3

Moore Model

PROM

Inputs

Outputs

Logic

Combi−national

Delayflip−flops

Logic

Combi−national

(The notes contrast this Moore model with a Mealy model. Mealyuses less hardware, but is harder to understand!)


Algorithmic State Machine Charts

The graphical state diagram of the sort give for the Moore model isone method of translating the written description of an fsm into aformal description.

A more descriptive method is the Algorithmic State Machine (ASM)chart — like process flow diagrams used in software design.


Algorithmic State Machine Charts

There are three symbols in ASM diagrams:

1. State definition rectangles: One per state. It gives the name ofthe state, the flip-flop values that define the state, and a list of outputs.

2. Decision diamonds: Any number of these for each state. Eachsenses an input condition or flag derived from an external sensor orother device, and takes a binary decision.

3. Conditional output curvy boxes: These occur at the exit lines ofdecision diamonds, and describe outputs that become true only whena condition is satisfied.

NB these outputs cannot “change” the outputs given in the state box. If you need to do that, you

need an extra state.


ASM Example (see Hill and Peterson for more)♣When washing finishes, the door remains locked until timer T1 counts up toa minute. If the door is not open by the user, the washing machine beepsloudly for 1 minute, and then beeps softly for 4 minutes. Opening the doorputs the machine in a reset state.

Justfinished

T1finished?

Reallyfinished!

Dooropened?

BeepLoud=1

BeepSoft=1

T1finished?

T5finished?

N Y

N

N

Y

Y

N

Y

DoorLock=1 DoorLock=0

To Reset State


Separating Data from Control



There seems an obvious difficulty in both graphical methods ...

... each and every state is represented.

Bad news ... n flip-flops can represent up to 2n states!

While this number is manageable for a few flip-flops, the methodbecomes unworkable for a machine with several tens of flip-flops,let alone several 109.

Better news ... The vast majority of flip-flops will merely bestoring data ...

... upon which the machine operates in the same way,irrespective of what the data is exactly.



Hence, in a sequential machine, it makes sense to split

the data section fromthe operational controlsection.

SignalsControl

FlagsData

Data In DataOut

ControlsExternal

Data Section

Control Section

At times, the control section will need to know something about thedata — eg, to take a different action if a datum is zero rather thanpositive.

So there will be two way communication between the control and datasections ...

but usually only flags about the data need sending.



Now we could now describe the control section using, say, ASMcharts ...

... but it is more convenient to use a description that has the syntax todeal with the data section at the same time.

We’ll adopt a “blackboard” hardware description language whichseparates data from control — a Register Transfer Language.

Commercial examples of such languages are VHDL(Very-High-Speed-Integrated-Circuit Hardware DescriptionLanguage), and Verilog.


Register Transfer Language


Preamble #1: What’s a Register?

D−type flip flop

4−bit register

Q[0]QD

CLK

CLK

D[1]

D[2]

D[3]

D[0]

Q[1]

Q[2]

Q[3]

An n-bit storage register is a parallel grouping of n 1-bit D-typeflip-flops which have coupled clocks, and transfer input to output on areceipt of a clock pulse

Qt+1 ← Dt

In this example, transfer occurs on a falling edge, indicated by thecircle placed in front of the clock input.


Preamble #2: What’s a Register Transfer?

D−type flip flop 1−bit transfer

Transfer from 4−bit register A to B

A[0]

A[1]

A[2]

A[3] B[3]

B[2]

B[1]

B[0]Q QRT

D

CLK CLK

CLK

A B

The transfer of data between two storage registers is the principalactivity that occurs in the data section of most sequential machines.

In the 1-bit example, clocking register R causes transfer R ← T .

In the 4-bit example B ← A means that B[i]← A[i] for i = 0,1,2,3.

The receiving register is clockedNOT the transmitting register.


Preamble #3: making pathways between registersOften two different registers A and B need to transfer to the sameregister C, although at different times.

We must NOT stuff both into the input of C(i) C will not know which to choose and (ii) connecting the outputof two registers with different output values (ie 0 and 1) may frythe output stage of one or both!!

Use either a multiplexer or tri-state buffers.

Both allow us to perform C ← A when s = 0 and C ← B when s = 1.

4

4

4

CLK

Multiplexer

s

M0

M1

Select

}

0/1

B

A

C4

4

4

CLK

Tristate buffers (4 in parallel)

Bus

A

B

C

sSelect


What’s RTL? An example ... Step 1

MODULE: DATAMOVERMEMORY: A[2]; B[2]; C[2]; SINPUTS: X [2].OUTPUTS: Z [2]; P.

1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)

ENDSEQUENCEControlReset(1); P = S.END

The first block defines the datasection.

A,B,C are two bit registers, but Sis single bit.

X is a two bit input wire and Z , Pare two, one bit output wires.



MODULE: DATAMOVERMEMORY: A[2]; B[2]; C[2];SINPUTS: X [2].OUTPUTS: Z [2]; P.

1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)


The numbered lines define the con-trol section. They are executed atsuccessive clock pulses (unless thereis branching).

On line 1: input X is transferred to A,so we need to clock register A.

On line 2: inverse of A is transferred toregister C, and S is set to A[0],

Lines 3 and 4: More register transfers.∨ is a logical OR.

On line 5: Output Z is conected to Cthroughout line 5. The goto arrow →sets the next line as 1.



MODULE: DATAMOVERMEMORY: A[2]; B[2]; C[2];SINPUTS: X [2].OUTPUTS: Z [2]; P.

1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)


At the end:

ControlReset(1) indicates that a resetpulse should set the control section toline 1.

P = S indicates that an output wire Pis permanently soldered to the outputof register S.


Control section: generating Level and Pulses

1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)

Typically, the activity on each step of thecontrol section requires

a level to select a pathway betweenregisters, anda pulse to fire register transfers.

These are Control Step Level and Pulse signals —- CSL1, CSP1,CSL2, CSP2 ... CSL5, CSP5

We need to build a state machine in hardware to deliver these signals.

Any method of building a sequential fsm can be used — eg a PROMsequencer — but here we will use a slightly wasteful but very intuitivemethod called one-hot.


Control section: generating Level and Pulses

1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)

The number of states equals the numberof steps — 5 in this case.

Now study the flow from one line to an-other. It is uninterrupted from line 1 to 5,where there is an unconditional goto indi-cated by→(1).

S R R R R

CSP1 CSP2 CSP3 CSP4 CSP5CSL2 CSL3 CSL4 CSL5CSL1

ControlReset

CLK

QD

1QD

2QD

3QD

4QD

5


Why is this one-hot?The one flip-flop corresponding to the active line of RTL has output 1(hence hot) — the remainder have output 0.

On a falling clock edge the output 1 is transferred to D-type 2, then 3,etc

Notice how the→(1) is achieved by looping the output of D-type 5into the input of D-type 1.

R R R R

CSP1 CSP2 CSP3 CSP4 CSP5CSL2 CSL3 CSL4 CSL5

S

CSL1

ControlReset

CLK

D

1Q

2QD

3QD

4QD

5Q D





R R R R

CSP1 CSP2 CSP3 CSP4 CSP5CSL3 CSL4 CSL5

S

CSL1 CSL2

ControlReset

CLK

D

1D

2Q

3QD

4QD

5Q Q D





R R R R


S

CSL1 CSL3

ControlReset

CLK

D

1QD

2D

3Q

4QD

5Q Q D





R R R R


S

CSL1 CSL4

ControlReset

CLK

D

1QD

2QD

3D

4Q

5Q Q D





R R R R


S

CSL1

ControlReset

CLK

D

1QD

2QD

3QD

4D

5Q Q





R R R R


S

CSL1

ControlReset

CLK

D

1Q

2QD

3QD

4QD

5Q D


Timing details

in data section

in data section

in control sectiontriggers D−typeFalling edge

combinational logicLevel to set up

trigger register transferFalling edge to

CSLn

CSPn = CLK .AND. CSLn

CLK

CSLn+1

CSPn+1


Data section: (Lines 1)In the Data Section ...Basic hardware is defined by the top + bottom block of the modulePathways are implicitly defined by the control steps.

Line 1* inputs X connected to input of register A* clock by CSP1.

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

X[0]

X[1]

CSP1

Z[0]

P

Z[1]

A S

B

CD Q

D Q

MODULE: DATAMOVERMEMORY: A[2]; B[2]; C[2];SINPUTS: X [2].OUTPUTS: Z [2]; P.1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)ENDSEQUENCEControlReset(1); P = S.END


Data section: (Lines 2 and 3)Line 2* Inverted outputs of A connected to C.* Output A[0] connected to input of S.* CSP2 to the CK input of C and S.

Line 3*

A

B

S

C

X[0]

X[1]

CSP1 CSP3 CSP2

D Q

Q

Q

D Q

D Q

QD

D Q

D

D

Q

Q

P

Z[0]

Z[1]



Data section: (Line 4): modifications needed nowLine 4:* C must be clocked on line 4 and line 2⇒C’s clock input is CSP2∨CPS4.

* On line 2, input to C is A but on line 4 input to C is A ∨ B.⇒insert AND gates, ANDing with CSL2 and CSL4 respectively, andthen OR the inputs into C.

A

B

S

C

Q

Q

D Q

D Q

X[0]

X[1]

CSP1 CSP3 CSL4 CSP4 CSP2

CSL2

D Q

CK

D

D

Q

Q

P

Z[0]

Z[1]

D

D Q

Q



Data section: (Line 5)

5 Z = C; S←0;→(1)

A

B

S

C

Q

Q

D Q

D Q

X[0]

X[1]


CSL2

D Q

CK

D

D

Q

Q

P

Z[0]

Z[1]

D

D Q

Q



5 Z = C; S←0;→(1)

A

B

S

C

Q

Q

D Q

D Q

X[0]

X[1]


CSL2

D Q

CK

D

D

Q

Q

P

Z[0]

Z[1]

D

D Q

Q

CSL5



5 Z = C; S←0;→(1)

CSP5

A

B

S

C

Q

Q

D Q

D Q

X[0]

X[1]

CSP1 CSP3 CSL4 CSP4

CSL2

D Q

CK

D

D

Q

Q

P

Z[0]

Z[1]

D

D Q

Q

CSL5CSP2


Conditional gotos in RTL

We’ve seen the unconditional goto

→(S1)

In our RTL, a conditional goto is written as follows:

→(L1, ...,Ln)/(S1, ...,Sn)

This evaluates logical expressions L1, L2, ... in turn. The very firstfound to be true causes a jump to the corresponding control step S.


Using conditionals with data flags to control flow

At step 4, if A[1] is 1 control passes to 5, if A[1] is 0, it goes to step 6.MODULE: DATAMOVERMEMORY: A[2]; B[2]; C[2]; SINPUTS: X [2].OUTPUTS: Z [2]; P.1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B;→(A[1],A[1])/(5,6)5 Z = C; S←1;→(1)6 Z = C; S←0;→(1)ENDSEQUENCEControlReset(1); P = S.END

MODULE: OLD-DATAMOVERMEMORY: A[2]; B[2]; C[2]; SINPUTS: X [2].OUTPUTS: Z [2]; P.1 A←X2 C←A; S←A[0]3 B←C4 C←A∨B5 Z = C; S←0;→(1)



Implementation of the new control section

The revised controller must have 6 flip-flops, and a connection fromA[1] into the control unit is needed. A[1] provides the selection signalin a multiplexer.

CSP6CSL6S

CSL1 CSL2 CSL3 CSL4CSP1 CSP2 CSP3 CSP4

CSL5CSP5

R

R R R R

CLK

ControlReset

D1

Q

QD6

A[1]

QD2

QD3

QD4

D5

Q

NB: OR gate handles the multiple ways of arriving back at Line 1.



CSP6CSL6S


CSL5CSP5

R

R R R R

CLK

ControlReset

D1

Q

QD6

QD2

QD3

QD4 5

QD

A[1]



CSP6CSL6S

CSL1 CSL2 CSL3 CSL4CSP1 CSP2 CSP3 CSP4 CSP5

R

R R R R

CLK

ControlReset

CSL5

D1

Q

QD6

A[1]

QD2

QD3

QD4

D5

Q



CSP6CSL6S


CSL5CSP5

R

R R R R

CLK

ControlReset

D1

QD6

A[1]

Q2

QD3

QD4

D5

QDQ



CSP6CSL6S


CSL5CSP5

R

R R R R

CLK

ControlReset

D1

Q

Q6

QD2

QD3

D4 5

Q

A[1]

D

D

Q



S


CSL5CSP5

R

R R R R

CLK

ControlReset

CSP6CSL6

1Q

D6

A[1]

QD2

QD3

QD4

D5

QD

Q



CSP6CSL6S


CSL5CSP5

R

R R R R

CLK

ControlReset

D1

QD6

A[1]

Q2

QD3

QD4

D5

QDQ


Timing

1 A←X2 C←A; S←A[0]etc

Do check theexample of thevariation over time ofthe various registeroutputs for particular(but arbitrary) inputsX ... ... useful forone of the tute sheetexamples if nothingelse.

1 2 3 4 6 1 2 3 4 5HOT

X0

X1

CLK

A0

A1

C0

C1

B0

B1

S

Z0

Z1


Two notesCombinational and sequential “black boxes”

“Black boxes” with names can be used in data section. ReadH&P Sections 10.7.The assumption is that these are defined elsewhere in your codeor elsewhere in a library of hardware

Step numbering when developingWithout “goto”, control passes from line S to line S + 1 on a clocktick, so all the steps 1,2,3...Smax should be present.While developing ideas, let’s allow gaps in the numbering, so thecontrol passes to the next highest number.

Eg, if there is no line 4, line 3 would pass to line 5.1 A←X2 C←A; S←A[0]3 B←C5 →(1)

Once complete, it is trivial to clean up.


Data, Control, and the CPU


So far ...

We’ve seen that separating data from control helps clarify andsimplify the design of sequential circuits.

We’ve also just seen how a single bit of data (A[1]) from the datasection can alter the flow in the control section ... ... effectivelychanging what the module does.

Now we want to extend that idea to the central processing unit(CPU) of a simple computer.

+ We’ll develop a von Neumann architecture,— data section is connected via a bus to a single mainmemory

+ But µcontrollers mostly adopt a Harvard architecture— two memories, one for the program, the other for the data.


Data, Control, and the CPUCentral Processing Unit

Plain DataProgram DataSignals

ControlFlagsData

Controls

Data In/Out

Control Section

Data Section

Main Memory

External

Data is read from the memory into the CPU via a bus.The CPUs’ data section contains registers and interconnectingpathways, and an Arithmetic Logic Unit.The result of a computation may be stored temporarily on CPUregisters or written back to Main Memory.The CPU’s control section is an fsm — we’ll use a one hotsequencer — which sends CSL’s and CSP’s to the data sectionto set pathways and to fire register transfers.


Data, Control, and the CPUCentral Processing Unit

Plain DataProgram DataSignals

ControlFlagsData

Controls

Data In/Out

Control Section

Data Section

Main Memory

External

As well as holding regular (grey) data, the Memory holds a set of(red) instructions that together form the program to execute.The control section (CU) performs register transfers to fetch aninstruction from memory. The CU turns the instruction into thesequence of CSLs and CSPs needed to execute the instruction.Once the execution of one instruction is finished, the nextinstruction is fetched, and so on.

microcontroller systems engineering science 2nd year a2 ...dwm/courses/2co_2014/2co-l1.pdf ·...

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