micro lec note1

MicroprocessorsSpring 2005

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-1

Books The Z80 Microprocessor , Hardware , Software

Author: Burry B. Brey Translator: Hossein Nia Publisher: Astane Ghodse Razavi(Beh Nashr

programming & interfacing


Microprocessors 1-2

Books Microcompiuter and Microprocessor : the 8080

, 8085 , Z-80 Programming , interfacing and trubleshooting

Publisher: Nass Pub.Date: 1381 Edition Turn: 3 ISBN: 964-6264-43-4-3 Pages: 719 Author: John E . UffenbeckTranslator: Mahmmod Dayani


Microprocessors 1-3

Books The 80x86 IBM PC and compatible computers (Design and interfacing of the

IBM PC PS and compatible)

Publisher: Baghani Pub.Date: 1379 Edition Turn: 2 ISBN: 964-91532-3-3 Pages: 760 Author: Mohammad Ali . Mazidi Janice Gillispie . MazidiTranslator: Dr. Sepidnamhsabaghianb @ kashanu.ac.ir Microprocessors 1-4

Books Microcontroller 8051 Publisher: Baghani Pub.Date: 1380 ISBN: 964-7343-00-0 Pages: 380 Author: Mohammad ali Mazidi Jonis Glispi MazidiTranslator: Dr. Sepidnam


Microprocessors 1-5

Books The 8051 Microcontroller Publisher: Baghani Pub.Date: 1380 Publishing Turn: 5 Edition Turn: 3 ISBN: 964-91532-2-5 Pages: 383 Author: Iscott Makenzi Translator: Rezaei Nia ,Darbandi Azarhsabaghianb @ kashanu.ac.ir Microprocessors 1-6

IntruductionMicroprocessor (uP)(MPU)A uP is a CPU on a single chip. Components of CPU ALU, instruction decoder, registers, bus control circuit, etc. small computer uP + peripheral I/O + memory specifically for data acquisition and control applications u-Computer on a single chip of siliconMicroprocessors 1-7

Micro-computer (u-Computer)

Microcontroller (uC)


uP vs. uC A uP only is a single-chip CPU bus is available RAM capacity, num of port is seletable RAM is larger than ROM (usually)

A uC

contains a CPU and RAM,ROM ,Prepherals, I/O port in a single IC internal hardware is fixed Communicate by port ROM is larger than RAM (usually) Small power consumption Single chip, small board Implementation is easy Low cost


Microprocessors 1-8

uP vs. uC cont.ApplicationsuCs are suitable to control of I/O devices in designs requiring a minimum component uPs are suitable to processing information in computer systems.


Microprocessors 1-9

uP vs. uC cont. uC is easy to use and design. Only single chip can be a complete system interfacing to other devices, for example, motors, displays, sensors, and communicate with PC.

In contrast, similar system that builds from uP would require a lot of additional units, such as RAM, UART, I/O , TIMER and etc.


Microprocessors 1-10

uC is a Reusable Hardware Logic circuit provides limited function for one single design. In order to change circuits functionality, we need to redesign the circuits. uC can reprogram and change functionality of every port, input to output or digital to analog on the fly.



uCs Many uCs are existing right now. 8051, 68HC11, MSP430, ARM series, and etc.

We may widely divide it with how it is designed RISC/CISC architecture.

What is the main difference between RISC/CISC? Does it make any difference to our application?



The Microprocessor (MPU) The uP is the brain of the microcomputer Is a single chip which is capable of processing data controlling all of the components which make up the microcomputer system

P used to sequence executions of instructions that is in memory uP Fetch , Decode , and Execute the instruction The internal architecture of the microprocessor is complex.



The Microprocessor (MPU) microprocessor (MPU) typically contains Registers: Temporary storage locations for programinstruction or data. The Arithmetic Logic unit (ALU): This part of the MPU

performs both arithmetic and logical operations Timing and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence



Microcomputers All Microcomputers consist of (at least) : 1. Microprocessor Unit (MPU) 2. Program Memory (ROM) 3. Data Memory (RAM) 4. Input / Output ports 5. Bus System (and Software)

MPU is the brain of microcomputer



Microcomputers



The Input/Output (I/O) System I/O is the link between the MPU and the outside world. An input port is a circuit through which an external device can send signals (data?) to the MPU. An output port is a circuit that allows the MPU to send signals (data?) to external devices. I/O ports connect both digital and analogue devices by DAC and ADChsabaghianb @ kashanu.ac.ir Microprocessors 1-17

Bus A Bus is a common communications pathway used to carry information between the various elements of a computer system The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another The individual subsystems of the digital computer are connected through an interconnecting BUS system.



BusThere are three main bus groups ADDRESS BUS DATA BUS CONTROL BUS



Data Bus The Data Bus carries the data which is transferred throughout the system. ( bi-directional) Examples of data transfers Program instructions being read from memory into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory

These are called read and write operations



Address Bus An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer The Address Bus is used to transmit the address of the location to the memory or the I/O port. The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.



Control Bus The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components.

Control signals are unidirectional, and are mainly outputs from the MPU. Example Control signals RD: read signal asserted to read data into MPU WR: write signal asserted to write data from MPUhsabaghianb @ kashanu.ac.ir Microprocessors 1-22

Main memory The duties of the memory are : To store programs To provide data to the MPU on request To accept result from the MPU for storage ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data valuesMicroprocessors 1-23

Main memory Types


Read-Only MemoryuP can read instructions from ROM quickly Cannot write new data to the ROM ROM remembers the data, even after power cycled Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )



Available ROMs Masked ROM or just ROM PROM or programmable ROM(once only) EPROM (erasable via ultraviolet light) Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading) EEPROM (electrically erasable read-only memory, also known as EEROMboth reading and writing are very slow but can program millions of timesuseless for storing a program but good for say configuration information.hsabaghianb @ kashanu.ac.ir Microprocessors 1-25

ROMm+1 bit Address

A0 A1 A2 Am

D0 D1 D2

Capacity :

2

m 1

2m1 (n 1)ROM PROM EEPROM

n+1 bit Data

Dn

OE : Output EnableCE (CS )

connect to RD of uP : Chip Enable to Address decoder

CE

OE



Timing Diagram for a Typical ROMA0-Am

D0-Dn

CE

OEOE falls to data valid Addr valid to data valid



27XX EPROMU3 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19U1 8 7 6 5 4 3 2 1 23 22 19 20 18 21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE CE VPP O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

U2 8 7 6 5 4 3 2 1 23 22 19 21 20 18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 OE/VPP CE O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

16 kbit 2 kbyte

2716

273232 kbit 4 kbyte

2764

64 kbit 8 kbyte

PGM and VPP are used to programminghsabaghianb @ kashanu.ac.ir Microprocessors 1-28

27XXX EPROMU7

U4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 OE PGM CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 22 20 1

U5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 1910 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 22 20 28

U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE/VPP CE VCC O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE PGM CE VPP

D0 D1 D2 D3 D4 D5 D6 D7

13 14 15 17 18 19 20 21

27128

27256

128 kbit 16 kbytehsabaghianb @ kashanu.ac.ir

256 kbit 32 kbyte

27512

512 kbit 64 kbyte

1024 kbit 128 kbyteMicroprocessors 1-29

27010

28XX E2PROM12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE WE CE VCC D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21

8 7 6 5 4 3 2 1 23 22 19 20 21 18 24

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE WE CE VCC

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

9 10 11 13 14 15 16 17

10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 28

A0 I/O0 A1 I/O1 A2 I/O2 A3 I/O3 A4 I/O4 A5 I/O5 A6 I/O6 A7 I/O7 A8 A9 RDY /BUSY A10 A11 A12 OE WE CE VCC

11 12 13 15 16 17 18 19 1

10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 22 27 20 28

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

11 12 13 15 16 17 18 19

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 24 31 22 32

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

13 14 15 17 18 19 20 21

281616 kbit 2 kbyte

64 kbit 8 kbyte

2864

28256256 kbit 32 kbyte

28010

28040

1026 kbit 128 kbyte

4096 kbit 512 kbyte



RAM (Random Access Memory)The uP can read the data from RAM quickly, The uP can write new data quickly to RAM RAM forgets its data if power is turned off Two type of is available :Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.



RAM(Static)A0 A1m+1 bit Address

D0 D1 D2

A2 Am

Capacity :

2

m 1

2m1 (n 1)RAM

n+1 bit Data

Dn

RD : Read signal connect to MemRD of uPWR : Write signal connect to MemWR of uP CS : Chip Select to Address decoderhsabaghianb @ kashanu.ac.ir

Data bus is Bidirectional

CS

WR

RD


Session 2Microprocessors History Data width 8086 vs 8088 8086 pin description Z80 Pin description



Microprocessors Microprocessors come in all kinds of varieties from the very simple to the very complex Depend on data bus and register and ALU width uP could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit We will discuss two sample of it Z80 as an 8-bit uP and 8086/88 as an 16-bit uP

All uPs have the address bus the data bus RD, WR, CLK , RST, INT, . . .



HistoryCompany 4 bit 4004 4040 8 bit 8008 8080 8085 Z80 6800 6802 6809 16 bit 8088/6 80186 80286 Z8000 Z8001 Z8002 68006 68008 68010 68020 68030 68040Microprocessors 1-35

32 bit 80386 80486

64 bit 80860 pentium

intel

zilog

Motorola


Internal and External BusInternal bus is a pathway for data transfer between registers and ALU in the uPs External bus is available externally to connect to RAM, ROM and I/O Int. and Ext. Bus width may be different For exampleIn 8088 Int. Bus is 16-bit , Ext. bus is 8-bit In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit



8086 vs 8088Only external bus of 8088 is 8_bitU? 33 22 19 21 18 MN READY CLK RESET INTR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 DEN DT/R M/IO HLDA HOLD NMI TEST 8086MIN RD WR ALE INTA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 39 38 37 36 35 34 26 27 28 32 29 25 24 30 31 17 23 HLDA HOLD NMI TEST 8088MIN 33 22 19 21 18 U? MN READY CLK RESET INTR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 A16/S3 A17/S4 A18/S5 A19/S6 SSO DEN DT/R IO/M RD WR ALE INTA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 39 38 37 36 35 34 26 27 28 32 29 25 24

8_bit Data Bus 20_bit Address

16_bit Data Bus 20_bit Address

30 31 17 23

8086

8088Microprocessors 1-37


8086 Pin Assignment



8086 Pin DescriptionVcc (pin 40) : PowerGnd (pin 1 and 20) : Ground AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX (input) : Indicates Operating mode READY (input , Active High) : take uP to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately terminate its present activity. TEST (input , Active Low) : Connect this to HIGH HOLD (input , Active High) : Connect this to LOW HLDA (output , Active High) : Hold Ack INTR (input , Active High) : Interrupt request INTA (output , Active Low) : Interrupt Acknowledge NMI (input , Active High) : Non-maskable interrupt



8086 Pin DescriptionDEN (output) : Data Enable. It is LOW when processor wants to receive data or processor is giving out data (to74245) DT/R (output) : Data Transmit/Receive. When High, data from uP to memory When Low, data is from memory to uP (to74245 dir) IO/M (output) : If High uP access I/O Device.

If Low uP access memory

RD (output) : When Low, uP is performing a read operation WR (output) : When Low, uP is performing a write operation ALE (output) : Address Latch Enable , Active High Provided by uP to latch address When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines



Z80 CPU Pin AssignmentM1 27 19 20 21 22 28 18 24 16 17 26 25 23 14 15 12 8 7 9 10 13 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5

System Control Lines

MREQ IORQ RD WR RFSH HALT WAIT -

Z - 80 CPU

CPU Control Lines

INT NMI RESET -

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7

Address Bus

Bus Control Lines

BUSRQ BUSAK + 5V GND

Data Bus

6 11 29



Z80 Pin DescriptionA15-A0 :Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus.

D7-D0 :

Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts.

RD:

Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O

WR:

Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.hsabaghianb @ kashanu.ac.ir Microprocessors 1-42

Z80 Pin DescriptionMREQ IORQMemory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1

M1

Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle

RFSH

Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAMhsabaghianb @ kashanu.ac.ir Microprocessors 1-43

Z80 Pin DescriptionINT Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. Checked at the end of the current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable Interrupt (Input, negative edge-triggered). Higher priority than INT. Recognized at the end of the current Instruction Independent of the status of IFF Forces the CPU to restart at location 0066H.



Z80 Pin DescriptionBUSREQ Bus Request (input, active Low). higher priority than NMI recognized at the end of the current machine cycle. forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp. BUSACK Bus Acknowledge (output, active,Low) indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high-impedance states.hsabaghianb @ kashanu.ac.ir Microprocessors 1-45

Z80 Pin DescriptionRESET Reset (input, active Low). RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive state. must be active for a minimum of three full clock cycles before the reset operation is complete.hsabaghianb @ kashanu.ac.ir Microprocessors 1-46

Z80 CPU8INTERNAL DATA BUS (8 BIT)

B U F F E R F F'

DATA BUS

MUXINSTRUCTION REGISTER

MUX A TMP A'

I

R

W'

Z'

W

Z

B' D' H'

C' E' L' IX IY SP

B D H

C E L

ACT

DECODER

CONTROLLER SEQUENCER

ALU

PC k k 16INTERNAL ADDRESS BUS (16 BIT)

CONTROL SECTION

B U F F E R

ADDRESS BUS

13INTERNAL CONTROL BUS

B U F F E R

CONTROL BUS



Z80 Programming Model



Register SetA : Accumulator Register F : Flag register Two sets of six general-purpose registersD E H L)

may be used individually as 8-bit A F B C D E H L (A F B C

The Alternative registers (A F B C D E H L) not visible to the programmer but can access via:

or in pairs as 16-bit registers AF BC DE HL (AF BC DE HL)

EXX (BC)(BC') , (DE)(DE') , (HL)(HL') EX AF, AF (AF)(AF') what is this instruction useful for?Microprocessors 1-49


Register Set(cont) 4 16-bit registers hold memory address (pointers) index registers (IX) and (IY) are 16-bit memory pointers 16 bit stack pointer (SP) Program counter (PC)

Program counter (PC) PC points to the next opcode to be fetched from ROM when the P places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location

Special purpose registers I : Interrupt vector register. R : memory Refresh registerhsabaghianb @ kashanu.ac.ir Microprocessors 1-50

Flag Register7 6 5 4 3 2 1 0

S Z X H XS Z H P V N C

P V

N C

Sign Flag (1:negativ)* Zero Flag (1:Zero) Half Carry Flag (1: Carry from Bit 3 to Bit 4)** Parity Flag (1: Even) Overflow Flag (1:Overflow)* Operation Flag (1:previous Operation wassubtraction)** Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand)

*: 2-complement number representation **: used in DAA-operation for BCD-arithmetichsabaghianb @ kashanu.ac.ir Microprocessors 1-51

DAA - Decimal Adjust AccumulatorAdjusts the content of the Accumulator A for BCD addition and subtraction operations such as ADD, ADC, SUB, SBC, and NEG according to the table:before DAA Op N 0 0 0 0 0 0 0 0 0 1 1 1 1 C 0 0 0 0 0 0 1 1 1 0 0 1 1 Bits 4-7 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F after DAA A=A+.. 00 06 06 60 66 66 60 66 66 00 FA A0 9A C 0 0 0 1 1 1 1 1 1 0 0 1 1Microprocessors 1-52

ADD ADC

SUB SBC NEG


Instruction cycles, machine cycles and T-statesInstruction cycle is the time taken to complete the execution of an instruction Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency)f= 4MHZ T-state=0.25 uS



Basic CPU Timing Example



Opcode Fetch Bus Timings (M1 Cycle)



The R register Is increased at every first machine cycle (M1). Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same Bit 7 can be changed using the LD R,A instruction. LD A,R and LD R,A access the R register after it is increased R is often used in programs for a random value, which is good but of course not truly random. the block instructions decrease the PC with two, so the instructions are re-executed.hsabaghianb @ kashanu.ac.ir Microprocessors 1-56

Memory read/write cycle



Adding One Wait State to an M1 Cycle



Adding One Wait State to Any Memory Cycle



IO read/write cycle

During I/O operations a single wait state is automatically insertedhsabaghianb @ kashanu.ac.ir Microprocessors 1-60

Bus Request/Acknowledge Cycle



Interrupt Request/Acknowledge Cycle

Two wait states are automatically added to this cyclehsabaghianb @ kashanu.ac.ir Microprocessors 1-62

Non-Maskable Interrupt Request Operation



M1 Refresh CycleTakes 4T to 6Ts Z80 includes built in circuitry for refreshing DRAM This simplifies the external interfacing hardware DRAM consists of MOS transistors, which store Information as capacitive charges; each cell needs to be periodically refreshed During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refreshhsabaghianb @ kashanu.ac.ir Microprocessors 1-64

Wait Signalthe Z80 samples the wait signal during T2 if low then Z80 adds wait states to extend the machine cycle used to interface memories with slow response time Slow memory is low cost



InterruptsThere are two types of interrupts: non mask-able (NMI)Could not be masked Jump to 0066H of memory

mask-able(INT)Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2hsabaghianb @ kashanu.ac.ir Microprocessors 1-66

Interrupt Modes Mode 0: An 8 bit opcode is Fetched from Data BUS and executed The source interrupt device must put 8 bit opcode at data bus 8 bit opcode usually is RST p instructions

Mode 1: A jump is made to address 0038h No value is required at data bus

Mode 2: A jump is made to address (register I 256 + value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vectorhsabaghianb @ kashanu.ac.ir Microprocessors 1-67



Z80 CPU Instruction Description158 different instruction types Including all 78 of the 8080A CPU. Instruction groups Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output Basic CPU ControlMicroprocessors 1-69


Addressing Modes Immediate Immediate Extended Modified Page Zero Addressing (rst p) Relative Addressing Jump Relative (2 byte) One Byte Op Code 8-Bit Twos Complement Displacement (A+2)

Extended Addressing Absolute jump One byte opcode 2 byte address

Indexed Addressing (Index Register + Displacement) (IX+d) 2 byte opcode 1 byte displacementhsabaghianb @ kashanu.ac.ir Microprocessors 1-70

Addressing Modes(cont.)Register AddressingLD C,B

Implied AddressingOp Code implies other operand(s) ADD E

Register Indirect Addressing16-bit CPU register pair as pointer (such as HL) ADD (HL)

Bit Addressingset, reset, and test instructions. SET 3,A RES 7,Bhsabaghianb @ kashanu.ac.ir Microprocessors 1-71

Minimal Configuration of a Z80 MicrocomputerClock Generator Memory (ROM, RAM) Power Supply

Address Bus

Z - 80 CPU

Data Bus Control Bus

Input Output (I/O)

Out In



Z80 Memory connectionCPU 16 bit address bus 64 k memory(max) CPU 8 bit data bus 8 bit data width Generally should be connectedData to data Address to address Wr to wr Rd to rd Mreq to cs



Memory connection (cont.) If only one RAM chip Full size (64 kb capacity)

D7~D0

D7~D0

RAM 64 kb A15~A0A15~A0

Z80 CPURD WR

RD

WR CS

MREQ



Memory connection (cont.) If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFhD7~D0D7~D0

RAM 32 kb A14~A0A14~A0

Z80 CPURD WR

RD

WR CS

A15

MREQ



Memory connection (cont.)There is two 32 kb RAM Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line A15 as an arbiter. If A15 outputs a logic 1 the upper memory is enabled (and the lower memory is disabled) and vice-versa.



Memory connection (cont.) There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1)D7~D0

D7~D0RAM 32 kb

D7~D0

RAM 32 kb

A14~A0

A14~A0RDWR CS

A14~A0RDWR CS

Z80 CPURD WR

A15

MREQ



Memory connection (cont.) 32 kb ROM and 32 kb RAM ROM doesnt have wr signal

D7~D0

D7~D0 ROM 32 kb

D7~D0

RAM 32 kb

A14~A0

A14~A0OECS

A14~A0RDWR CS

Z80 CPURD WR

A15

MREQ



Memory connection (cont.)There is 4 memory chip A14 and A15 applied to chip selection

D7~D0

D7~D0 ROM 16 kb A13~A0OECS

A13~A0 Z80 CPU

RAM RAM RAM 16 kb 16 kb 16 kb A13~A0 A13~A0 A13~A0RDWR CS

D7~D0

D7~D0

D7~D0

RD

WR CS

RD

WR CS

RD WR


A14 A15

MREQ

En S0 S1Microprocessors 1-79

Address Bit MapSelects chipA15 to A0 (HEX)0000h

Selects location within chipsAAAA 1198 100000

AA AA 11 11 54 3200 00

AAAA 76540000

AAAA 32100000

Memory ChipROM RAM1

3FFFh4000h 7FFFh 8000h BFFFh C000h FFFFhhsabaghianb @ kashanu.ac.ir

00 1101 00 01 11 10 00 10 11 11 00 11 11

11110000 1111 0000 1111 0000 1111

11110000 1111 0000 1111 0000 1111

11110000 1111 0000 1111 0000 1111

RAM2RAM3Microprocessors 1-80

Memory Map Represents the memory type Address area of each memory chip Empty areaD7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0CS

0000h3FFFh 4000h 7FFFhRAM 16 kb A13~A0

ROM16k

RAM116k

D7~D0 RAM 16 kb

D7~D0 RAM 16 kb A13~A0

D7~D0

8000h BFFFh C000h

OE

RD

WR CS

RD

WR CS

RD

WR CS

RAM216k

RD WR

MREQ

En S0 S1

RAM316k


A14 A15

FFFFh


Memory Map Empty Area cannt write and read Read op. returns FFh value (usualy) Write op. cannt store any value on it

0000h3FFFh 4000h

ROM

EmptyD7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0CS

D7~D0 RAM 16 kb

D7~D0 RAM 16 kb A13~A0

7FFFh 8000h BFFFh C000h

OE

RD

WR CS

RD

WR CS

RAM2 RAM3

RD WR


A14 A15

MREQ

En S0 S1

FFFFhMicroprocessors 1-82

Memory Map Empty Area cannt write and read Read op. returns FFh value (usualy) Write op. cannt store any value on it

0000h3FFFh 4000h

ROM

EmptyD7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0CS

D7~D0 RAM 16 kb

7FFFh 8000h BFFFh C000hEmpty

OE

RD

WR CS

RAM

RD WR


A14 A15

MREQ

En S0 S1

FFFFhMicroprocessors 1-83

Full and Partial Decoding Full (exhaust) Decoding All of the address lines are connected to any memory/device to perform selection Absolute address : any memory location has one address

Partial Decoding When some of the address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses (fold back or shading). roll-over address : any memory location has more than one address



Partial Decoding A15~A12 has no connection Then doesnt play any role in addressing What is the Memory and Address Bit map?

D7~D0

D7~D0

RAM 4 kb A11~A0 A15~A12 XA11~A0

RD

WR CS

Z80 CPU

RD WR

MREQ



Partial Decoding Every memory location has more than one address For example first RAM location has addresses: 0000h 1000h 2000h 3000h Roll-over Address. .

0000h 0FFFh 1000h 1FFFh 2000h 2FFFh 3000h 3FFFh

RAM RAM RAM RAM

F000h FFFFh

RAM

F000hD7~D0

D7~D0

A15 to A0 (HEX)X000h

AAAA 1111 5432 xxxx

AAAA 1198 10 0000

AAAA 7654

AAAA 3210

Memory Chip

RAM 4 kbA11~A0A15~A12A11~A0

X

RD

WR CS

0000

0000

XFFFh

xxxx

1111

1111

1111

RAM

Z80 CPU

RD WR

MREQ



Partial Decoding A12 only connected to RAM A13 has no connection What is the memory map?

D7~D0

D7~D0 ROM 4 kb

D7~D0

RAM 8 kb

A12~A0 A13

A11~A0

A12~A0CS

X

OE

RD

WR CS

Z80 CPUA15 A14hsabaghianb @ kashanu.ac.ir

RD WR

MREQ


Partial Decoding 8 roll-over address for ROM 4 roll-over address for RAM

D7~D0

D7~D0

D7~D0

ROM 4 kbA12~A0 A11~A0 A12~A0

RAM 8 kb

AAAA 1111 5432 0xxx

AAAA 1198 10 0000

AAAA 7654

AAAA 3210

Memory Chip

Z80 A13 CPURD WR

X

OE

CS

RD WR CS

0000

0000

0xxxX0x0 X0x1

11110000 1111

11110000 1111

11110000 1111

ROM RAM


A15 A14

MREQ


Partial DecodingD7~D0 D7~D0 D7~D0

0000h

0000h

RAM1FFFh 2000h

0FFFh

ROM ROM ROM ROM ROM ROM ROM ROM

Conflict1000h 1FFFh 2000h 2FFFh 3000h 3FFFh 4000h 4FFFh 5000h 5FFFh 6000h 6FFFh 7000h 7FFFh F000h

RAMRAM 8 kb3FFFh 4000h

ROM 4 kbA12~A0 A11~A0 A12~A0

Z80 A13 CPURD WR

X

OE

CS

RD WR CS5FFFh 6000h

AAAA 1111 5432 0xxx 0xxx X0x0 X0x1


A15 A14

MREQ

7FFFh 8000h

RAM AAAA 1198 10 0000 1111 0000 1111 AAAA 7654 AAAA 3210 Memory Chip4k9FFFh A000h

RAM 0000 1111 0000 1111 0000 1111 0000 1111BFFFh C000h

ROM8k

RAM

DFFFh E000h FFFFh

FFFFh


Partial DecodingD7~D0 D7~D0 D7~D0

0000h

0000h 0FFFh 1000h 1FFFh 2000h 2FFFh 3000h 3FFFh 4000h

ROM ROM ROM ROM ROM ROM ROM ROM

1FFFh 2000h

ROM 4 kbA12~A0 A11~A0 A12~A0

RAM 8 kb

3FFFh 4000h

Z80 A13 CPURD WR

X

OE

CS

RD WR CS5FFFh 6000h

RAM

4FFFh 5000h 5FFFh 6FFFh 7000h 7FFFh F000h 6000h

ConflictRAM

AAAA 1111 5432 0xxx 0xxx X1x0 X1x1


A15 A14

MREQ

7FFFh 8000h

AAAA 1198 10 0000 1111 0000 1111

AAAA 7654

AAAA 3210

Memory Chip4k

9FFFh A000h

0000 1111 0000 1111

0000 1111 0000 1111

BFFFh C000h

ROM8k

RAM RAMDFFFh E000h

RAMFFFFh

FFFFh


Full (exhaustive) decodingAAAA 1111 5432 0000 0001 0010 AAAA 1198 10 0000 1111 0000 AAAA 7654 0000 1111 0000 AAAA 3210 0000 1111 0000 Memory Chip

A12~A0ROM

A12~A0 D7~D02764 EPROM 8k8

0010

0111

1111

1111

RAM

OE

CE

D7~D0 A13 A12 A11 C B A Y0 Y1 Y20000h-07FFh 0800h-0FFFh 1000h-17FFh 1800h-1FFFhRD

7421A10~A0 A10~A0 D7~D06116 RWM 2k8

74138A15 A14MREQ

Y3 Y4 Y5 Y6 Y7

2000h-27FFh

G2A G2B G1

RD WR CS

RD WR



Partial decodingAAAA 1111 5432 0000 0001 001x AAAA 1198 10 0000 1111 x000 AAAA 7654 0000 1111 0000 AAAA 3210 0000 1111 0000 Memory Chip

A12~A0ROM

A12~A0 D7~D02764 EPROM 8k8

001x

x111

1111

1111

RAM

OE

CE

D7~D0 A15 A14 A13 C B A Y0 Y1 Y20000h-1FFFh 2000h-3FFFhRD

A10~A0

74138MREQ

Y3 Y4 Y5 Y6 Y7

A10~A0 D7~D06116 RWM 2k8

G2A G2B G1

GND VCC

RD WR CS

RD WR



1 Bit Memory With Separated I/OD7-D0 D7 D1 D0

DinA11-A0 A11~A02147 RWM 4k1

DinA11-A0 A11~A02147 RWM 4k1

DinA11~A0 A11-A02147 RWM 4k1

Dout

Dout

Dout

WR / RD

CS

WR / RD

CS

WR / RD

CS

WR / RD

CS



What is the memory(addr. bit) mapA12~A0 D7~D0 2764 EPROM 8k8

OE

CE

RD

A15 A14

C B A

Y0 Y1 Y2

0000h-1FFFh 2000h-3FFFh D7-D0D7 D1 D0

A13

74138MREQ

Y3 Y4A11-A0

DinA11~A0 Dout2147 RWM 4k1

DinA11-A0 A11~A0 Dout2147 RWM 4k1

DinA11-A0 A11~A0 Dout2147 RWM 4k1

G2A G2B G1WR

Y5 Y6 Y7WR

GND VCC

WR / RD CS

WR / RD CS

WR / RD CS

RD



Adding RAM & ROM



Minimum Z80 Computer System



Z80-P-Family (Typical Environment)PIOINT -

+5V INT -

DMAIEI RDY

System Buses (Address, Data, Control)

INT -

INT -

INT IEO IEI

IEO

W/RDYB -

Z80 CPU+5V IEI

CTCZC/TO1 ZC/TO2

SIOTxCA TxCB RxCA RxCB -



Z80 Input Output Z80 at most could have 256 input port and 256 output 8 bit port address is placed on A7A0 pin to select the I/O device OUT (n), A n is 8 bit port address OUT (C), r Content of C is a port address IN A, (n) n is 8 bit port address IN r (C) Content of Reg C is a port addresshsabaghianb @ kashanu.ac.ir

Content of A is data

r is a data register

Data is transfered to A

Input data is transfered to r (data reg)Microprocessors 1-98

Remember IO read/write cycle



Z80 and simple output portA15 A14 : A0 D7 D6 D5 D4 D3 D2 D1 D0

OUT (03), AD0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 74LS373 Q4 D5 Q5 D6 Q6 D7 Q7 LE OE

Z80 CPU


WR IORQIOWR A AAA AA AA 7 654 32 10


Z80 and simple input portA15 A14 : A0 D7 D6 D5 D4 D3 D2 D1 D0

IN A, (02)Y0 A0 Y1 A1 Y2 A2 Y3 A3 Y4 74LS244 A4 Y5 A5 Y6 A6 Y7 A7 G1 G2

5V

Z80 CPU


RD IORQIORD AAAA AAAA 7654 3210


8088 and simple output portA19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 74LS373 Q4 D5 Q5 D6 Q6 D7 Q7

8088 Minimum Mode

LEIOR IOW

OE

AAAAAAAAAAAAAAAAIOW 1 111 119 876 54 3210 5 432 10



8088 and simple input portA19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 Y0 A0 Y1 A1 Y2 A2 Y3 A3 Y4 74LS244 A4 Y5 A5 Y6 A6 Y7 A7 G1 G2 IOR IOW5V

What is this?

8088 Minimum Mode

AAAAAAAAAAAAAAAAIOW 1 1 1 1 1 19 8 7 6 5 4 32 1 0 5 432 10



Simplified Drawing of 8088 Minimum ModeA7 - A0 DEN DT / R E DIR B7 - B0

D7-D0

74LS245A7-A0Q7 - Q0

AD7 - AD0 GND

D7 - D0 OE LE

74LS373Q7 - Q0

A15 - A8

D7 - D0 GND OE LE

A15-A8

8088A19/S6 - A16/ S3

74LS373Q7 - Q4 Q3 - Q0

D7 - D4 D3 - D0 GND OE LE

A19-A16

ALE RD IO / M

74LS373MEMR MEMW

WR

IOR IOW



Minimum Mode220 bytes or 1MB memory

D7 - D0

D7 - D0

A19 - A0

A19 - A0

Simplified Drawing of 8088 Minimum ModeMEMRMEMW

1 MB Memory

RDWR

CS



What are the memory locations of a 1MB (220 bytes) Memory?A19 to A0 (HEX) 00000 FFFFF AAAA 1111 9876 0000 1111 AAAA 1111 5432 0000 1111 AAAA 1198 10 0000 1111 AAAA 7654 0000 1111 AAAA 3210 0000 1111

Example: 34FD0 0011 0100 11111 1101 0000



Minimum Mode512 kB memory

D7 - D0 A19 A18 - A0

D7 - D0

What do we do with A19?A18 - A0

Simplified Drawing of 8088 Minimum ModeMEMRMEMW

1) 2)

Dont connect it Connect to cs512 kB Memory

What is the difference?

RDWR

CS



512 kB Memory Map Dont connect it00000h 7FFFFh

A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic 1,the memory cannot see it. A19=0 is the same as A19=1 for Memory

512k Mem

80000h FFFFFh

512k Mem

Connect to cs

00000h 7FFFFh

If A19=0 Memory chip act normal fanction

512k Mem

80000h FFFFFh

Empty



2 512 kB memory

D7 - D0 A19 A18 - A0MEMR

D7 - D0

512 kB RAM1A18 - A0 RD WR

MEMR MEMWMEMW

CS

D7 - D0

Simplified Drawing of 8088 Minimum Mode

512 kB RAM2A18 - A0MEMR MEMW

RD WR

CS



2 512 kB memoryWhat are the memory locations of two consecutive 512KB (219 bytes) Memory?AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip

00000h

512k RAM1

7FFFFh 80000h

00000111 1000

00001111 0000

00001111 0000

00001111 0000

00001111 0000

ROM RAMFFFFFh

512k RAM2

1111

1111

1111

1111

1111



Interfacing four 256K Memory Chips to the 8088 MicroprocessorA19 A18 A17:

A17:

A0 D7:

D0 RD WR

256KB #4

CSA17:

A0 D7:

A0 D7:

D0 MEMR MEMW

D0 RD WR CS A17:

256KB #3

8088 Minimum Mode

A0 D7:

D0 RD WR CS A17:

256KB #2

A0 D7:

D0 RD WR CS

256KB #1



Interfacing four 256K Memory Chips to the 8088 MicroprocessorA19 A18 A17:

A17:

A0 D7:

D0 RD WR CS A17:

256KB #4

A0 D7:

A0 D7:

D0 MEMR MEMW

D0 RD WR CS A17:

256KB #3

8088 Minimum Mode

A0 D7:

D0 RD WR CS A17:

256KB #2

A0 D7:

D0 RD WR CS

256KB #1



Memory chip#__ is mapped to:AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210

Memory ChipRAM#1 RAM#2 RAM#3 RAM#4



A12:

Interfacing several 8K Memory Chips to the 8088 P

A19 A18 A17 A16 A15 A14 A13 A12:

A0 D7:

D0 RD WRCS

8KB #?

A0 D7:

8088 Minimum Mode

D0 MEMR MEMW

: :A12:

A0 D7:

D0 RD WR CS A12:

8KB #2

A0 D7:

D0 RD WR CS

8KB #1



Interfacing 128 8K Memory Chips to the 8088 P8088 Minimum Mode

A12:

A19 A18 A17 A16 A15 A14 A13A12:

A0 D7:

D0 RD WRCS

8KB #128

A0 D7:

D0 MEMR MEMW

: :A12:

A0 D7:

D0 RD WR CS A12:

8KB #2

A0 D7:

D0 RD WR CS

8KB #1



A12:

Interfacing 128 8K Memory Chips to the 8088 P

A19 A18 A17 A16 A15 A14 A13 A12:

A0 D7:

D0 RD WR CS

8KB #128

A0 D7:

8088 Minimum Mode

D0 MEMR MEMW

: :A12:

A0 D7:

D0 RD WR CS A12:

8KB #2

A0 D7:

D0 RD WR CS

8KB #1



Memory chip#__ is mapped to:AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210

Memory Chip RAM#1 RAM#2

RAM#126 RAM#127 RAM#128



What is the Memory and Address Bit map?A12~A0 A12~A0 D7~D02764 EPROM 8k8

OE

CE

D7~D0

A14

C B A

7408Y0 Y1

RD

A13A12

Y2

A10~A0

74138MREQ

Y3

A10~A0 D7~D06116 RWM 2k8

Y4G2A G2B G1 Y5 Y6 Y7

74244 inputG1G 2

A15VCC

RD WR CS

RD WR



micro lec note1

Documents