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FUJITSU SEMICONDUCTORCONTROLLER MANUAL CM71-10401-1E

FR FAMILY EVALUATION BOARD For MB91401

MB91941EBREFERENCE MANUAL

PREFACE

OverviewThis manual is a reference manual for the evaluation board (part number: MB91941EB) intended to evaluate and develop software for the network security LSI (MB91401) incorporating a Fujitsu's pro-prietary 32-bit RISC CPU core, 10/100Base-T MAC controller, and encryption/authentication mac-ros.

Purpose of this document and intended readerThis manual is intended for engineers who develop products incorporating MB91401, especially who develop programs. It also describes the functions and operation of the evaluation board for MB91401.

Organization of this document

1. Configuration

This chapter explains the features and basic specifications of the evaluation board.

2. Setting

This chapter explains the setting of the evaluation board.

3. Hardware Specification

This chapter explains each specification and function of the evaluation board.

i

©2005 FUJITSU LIMITED Printed in Japan

• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented sole-ly for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the infor-mation.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party’s intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire pro-tection, and prevention of over-current levels and other abnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certain restrictions on export un-der the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

ii

1. Configuration

1.1 Configuration of evaluation board

Figure 1 Configuration diagram of MB91401 evaluation board (MB91941EB)

SRAM256Kx16bit

NetworkController

MB91401(240BGA)

0.5 mm pitch

VDDI = 1.8 VVDDE = 3.3 V

MAX3232

OSC48 MHz

D-sub9

D-sub9

USBSeriesB

Exp

.C

onn.

Mic

tor

Con

n.E

xp.

Con

n.

SW1. OSC12.5 MHz

LED

PHYBCM5221

TransS558-

5999-W2RJ45Conn.

FPGAAPEX20KE1000

(FC672)VDDI = 1.8 VVDDE = 3.3 V Le

vel

Shi

fter

LANControllerMB86967SQFP100

5 V

DC/DC

ACAdapter

ICE Conn.

SD

Con

n.C

FC

onn.

VDD PHY32 bit@50 MHz

DC5 V/4 AConn.5 V

3.3 V2.8 V1.8 V

FH10A-30S-1SH

4

20 I2C

48

INT

32CS#22 CS#0 CS#132 32

90

16

16

8

8

CSX

INTX

5VLED OSC

20 MHz

EPC16(BGA88)

MictorConn. JTAG Conn. AVDD_LAN

RJ45Conn.

SRAM4 MB

(1 M × 32 bit)

Flash4 MB

(2 M × 32 bit)

SR

AM

32 K

× 8

bit

TransS556-

9003-09

LED

SW

2,S

W3.

4

1

Table 1 Hardware main loading parts

Category Device Supplier Qty Package Notes

Network Controller MB91401 Fujitsu 1BGA240 (0.5 mm pitch)

FPGA APEX20KE1000EFC-1X Altera 1 Fineline672

Configuration EPC16 Altera 1 BGA88

JTAC Connector PS-10PE-D4T1 JAE 1 DIP10

Flash memory MBM29LVT-160T-80K Spansion 4 TSOP48 TSOP (I)8 MB (1 M × 16 bits) × 4 pcs.

Socket IC197-4807-2000 Yamaichi 4 TSOP48

SRAM GS74116 GSI 8 TSOP44 TSOP (II)4 MB (256 K × 16 bits) × 8 pcs.

Extended LAN Controller MB86967 Fujitsu 1 SQFP100 5V product

Buffer SRAM TC55257 Toshiba 1 TSOP28 32 KB (32 K × 8 bits)

Pulse Trans S556-9003-09 BEL Fuse 1

Chip LED Green × 4 pcs. ROHM 4 2125

OSC 20 MHz EPSON 1 DIP4

PHY BCM5221 Broadcom 1

Chip LED Green × 4 pcs. ROHM 4 2125

OSC 25 MHz EPSON 1 DIP4

Pulse Trans S558-5999-W2 BEL Fuse 1

Level ShifterPI5C3244 Pericom 4 SSOP20 5 V <->3.3 V

QS3V245Q IDT 2 SSOP20 3.3 V <->2.8 (2.5) V

Regulator MIC29302BU Micrel 3 TO-263-5 1.8 V/ 3.3 V/ 2.8 V

Serial Driver MAXS3232E MAXIM 1

Con

nect

or

RJ45 (LAN) TM11R-5L-88 HIROSE 2

USB 67068-0001 MOLEX 1

Serial RDED-9P-LNA HIROSE 2

Mictor 2-767004-2 AMP 6

ExtendedXG4C-4031 OMRON 1

XG4C-6431 OMRON 2

Power AC adapter NT24-1S0540 Akizuki 1

Connector MJ-179P EST 1

ICE FH10A-30S-1SH HIROSE 1

SW

Power MS12AAP1 NKK 1

Reset GB-15AH NKK 1

DIP SW CHS-08B COPAL 3 SMT16

2

.

1.2 Address map

The chip select signals (CSX0, CSX1, CSX6) output from MB91401 to external device are assigned as follows. The extended LAN controller and extended bus connector are assigned to the FPGA (CSX6), requiring decoding inside the FPGA.

Allocation of CSTable 2 shows the allocation of CS.Peripheral module registers and processing areas are mapped to the CS2-5 and CS7 areas, including the internal encryption/authentication macros, MAC interface, and External interface.

Table 2 Allocation of CS

Address mapBefore setting the register for each module, set the ASR (Area Select Register), ACR (Area Config-uration Register), and AWR (Area Wait Register) of the CPU core to define individual CS areas. Figure 2 shows an address map viewed from the CPU core.

Figure 2 Address map

CS# Device Bus width Size Device Bus width Size

CS0Boot Flash 32 bits 4 MB Extended LAN controller 16 bits −Code Flash 32 bits 4 MB FPGA extended connector − −

CS1 SRAM 32 bits 4 MB

CS6 FPGA − −

CPU Core Area

User Area

Mode VectorReset Vector

User Area

I2C IFMAC/MII IFencryption,

authentication processblock

External IF(GPIO)

DH process block

User Area

User Area

CARD IF/USB IF

CS2

CS3

CS4

CS5

CS7

64 KB

64 KB

256 KB

16 KB

Any user area can be set.

Each CS area is defined by following registers.ASR (Area Select Register)ACR (Area Configuration Register)AWR (Area Wait Register)

64 KB

CS# Device Bus width Size

CS0Boot Flash 32 bits 4 MB

Code Flash 32 bits 4 MB

CS1 SRAM 32 bits 4 MB

CS6

FPGA − −

Extended LAN 16 bits −

FPGA extended connector

− −

0000_0000H

0004_0000H

000F_FFF8H

000F_FFFCH

010F_0000H

0110_0000H

0114_0000H

0115_0000H

0116_0000H

0500_0000H

0600_0000H

FFFF_FFFFH

3

2. Setting2.1 Jumper pin setting

The jumper pin settings for the board are shown below.

Table 3 Jumper pin setting

J1 Select EXD Data bit width (EXIS16)

Set the data bus width of the extended bus.

Open 16 bits (Enabled EXD [15:0])

Short8 bits (Enabled EXD [15:8])Note : EXD [7:0] = GPIO [7:0]

J2, J3 FPGA Configuration

Select the configuration destination at ISP Programming mode. 1-2 Configuration to FPGA direct

3-2 Configuration to Configuration Device

J4, J5 Select Boot Flash ROM

Select Flash ROM for Boot. Non-selected Flash ROM is mapped as Code ROM.

J4 J5 Boot ROM Code ROM

1-2 1-2 Flash#0 Flash#1


1-2 3-2 Setting disabled −3-2 1-2 Setting disabled −

J7 USB Clock Select

Select the CLK source to USB interface of MB91401.Open External CLK input (X5 :48 MHz)

Short Internal system clock

J8 USB D+ line pull-up CTL

Select the signal of controlling pull-up of USB D+ line. 1-2 Using the output signal from FPGA

3-2 Using V-bus signal

J9,J10 Exp. Connector (CN11) power supply

Select power supply (+3.3 V) connecting/cutting to the extend-ed connector (CN11).

Open Cutting

Short Connecting



Open Cutting

Short Connecting



Open Cutting

Short Connecting

J15 Spare power connector

Spare power supply pin.1pin GND

2pins +5V

J17 Spare Reset

Reset pin. After short, the system is reset by Hardware. Open Normal

Short Reset

J18 System RST select

Select system reset. As using ICE, set "3-2" side.1-2 System RST

3-2 ICE RST

4

22.2 DIP switch setting

The following settings are available by setting the on-board DIP switches. SW1: Used to control the CLK system of the MB91401.SW2: Connected to FPGA.SW3: Connected to FPGA.

Note : • The maximum operating frequency of the MB91401 is 50 MHz. No operation is guaranteed if the maximum operating frequency is exceeded.

• The SD card function is optional.

Table 4 SWITCH1 setting

Table 5 Relationship between the input CLK and the external (core) CLK

SW1No. Signal Description

Switch

ON (0) OFF (1)

1 PLLSET1 Selecting divide ratio of MB91401 input CLK ×1/1 ×1/2

2 PLLSET0Selecting divide ratio to the FB terminal of MB91401 internal PLL

×1/2 ×1/4

3 PLLBYPASS Selecting PLL bypass of MB91401 Using PLL Using PLL

4 CLKSEL Switching input CLK to MB91401 XINI (X1) OSC (X2)

5 SDSEL Selecting SD card or CF. CF SD

6 OSCOFF Crystal oscillator control of MB91401 Oscillation Stop

7 Rsvd. Reserved TBD TBD

8 Rsvd. Reserved TBD TBD

PLLSET1SW1.1

PLLSET0SW1.2

PLLBYPASSSW1.3

CORE(XINI)

External(MCLKO) I2C Remark

0 0 0 ×2 ×2 ×1/2

Using PLL0 1 0 ×4 ×4 ×1/1

1 0 0 ×1 ×1 ×1/4

1 1 0 ×2 ×2 ×1/2

0 x 1 ×1 ×1 ×1/4 Non-using PLL

1 x 1 ×2 ×1/2 ×1/2

5

3. Hard Ware Specification

3.1 MB91401MB91401 is a network security LSI incorporating a Fujitsu proprietary 32-bit RISC CPU core, 10/100Base-T MAC controller, and encryption and authentication macros. This LSI contains an encryp-tion/authentication hardware accelerator that enables the high-speed processing for encryption/au-thentication communication (IKE/IPsec/SSL). The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount of packet processing. In addition, the board has the external interface for high-speed data communication with various external hosts, USB interface as general-purpose interfaces, and various card interfaces, supporting a variety of applica-tions.

Block diagram

Figure 3 Block diagram

Serial IF(2 ch)

INT/NMI

E

B

T

D-RAM (8 KB)

R

UART

INT

Timer

I-Cache (4 KB)

DMAC

CPUcore

OSC

CLKCont

PLL

DSU

Crystal Unit

CLKINUSB CLK (48 MHz)

DSU IF

PHY

USB IF

CompactFlash IF

I2C Bus

IPsec Accelerator/IKE Accelerator

DES/3DES

HMAC-MD5/SHA1

DH

External IF

GPIO

Ext. IF/PORT

MU

X

MB91401

10/100 EthernetMAC Controller

L2/L3/L4 Filtering

USB Function Rev 1.1

CARD IF

I2C IF

Flash SRAM

6

3.2 Flash memory

For the CS0 area, ROM areas of boot and code are allocated, each of which is 4M bytes (1 M × 32 bits). Each can be set as boot ROM or code ROM depending on the settings of these on-board jumper pins.

Table 6 Relationship between J4/J5 and Boot ROM/Code ROM

Each Flash Memory is socket mounted and removable.• Part number : MBM29LV160T-80PFTN (Spansion)

• Capacity : 64 Mbits (1 M × 16 bits × 4 pcs.)

• Bus width : 32 bits

• Power supply voltage : +3.3 V

• Package : 48-pinTSOP (TSOP(I))

• Socket number : IC197-4807-2000 (Yamaichi)

Figure 4 J4/J5 setting

Note : The board uses the HD74LVC139 as a Flash CS decoder. Pay attention to the Flash Memory access timing in

consideration of the following transmission delay times (tPLH, tPHL).

Table 7 AC characteristics of HD74LVC139

J4, J5 Select Boot Flash Memory

J4 J5 Boot ROM Code ROM



1-2 3-2 Setting disabled

3-2 1-2 Setting disabled

Parameter Symbol VCCTa = −40 °C to +85°C

Min Typ Max Unit

Transmission delay timetPLHtPHL

3.3 V ± 0.3 V 1.5 5.0 9.0 ns

3 3 3 3

1 1 1 1

_

J4 J5 J4 J5

At J4/J5:1-2

U18Flash#1_L

U19Flash#1_H

U16Flash#0_L

U17Flash#1_H

U17Flash#1_H

U19Flash#1_H

U16Flash#0_L

U18Flash#1_L

At J4/J5:3-2

Boot ROM

J4/J5:1-2 J4/J5:3-2

Boot ROM

Boot ROMBoot ROMCode ROMCode ROM

Flash#0 (U16,U17)Flash#1 (U18,U19)

Flash#1(U18,U19)Flash#0(U16,U17)

7

3.3 SRAM

4M bytes (1 M × 32 bits) of high-speed SRAM are connected to the CS1 area.• Part number : GS74116TP-10 (GSI Technology.)

• Capacity : 4 MB

• Bus width : 32 bits


• Package : 44-pin TSOP (TSOP (II))

The board uses the HD74LVC139 as a SRAM CS decoder and generates byte-enable signals effec-tive to read mounted high-speed SRAM from WRX (3:0), RDX, and CSX1. Pay attention to the ac-cess timing because these cause control signals (SRAMCSX (3:0), SRAMBEX (3:0), and SRAMWRX) to SRAM to arrive delayed from MB91401 output as shown below.

• CSX : 1.0 ns < tPD < 9 ns

• BEXn, WRX : 3.0 ns < tPD < 11 ns

Figure 5 Connection with MB91401

D[31:0]

74LVC139

A[21:2]

CSX1

RDXMRX[3:0]

MB91401

A20

A21SRAMCSX3

SRAMCSX2

SRAMCSX1

SRAMCSX0

SRAMBEX0

SRAMBEX1WRXRDX

SRAMCSX3

D[31:16] D[15:0]

•••1 MB

SRAMBEX2SRAMBEX3

D[15:0]A[17:0]

UBXLBXWE#

OE#CE#GS71164 GS71164

D[15:0]A[17:0]

LBXUBX

WE#OE#CE#

SRAM5

SRAM3SRAM1 SRAM0

SRAM2SRAM4

A20 A211

0

SRAMCSX3

SRAMCSX2SRAMCSX1SRAMCSX0

100

101 TC74LCX08/32

TC74LVC139

Ta = −40ºC to +85ºC VCC = 3.3 V ± 0.3 V

~SRAMBEX[3:0]=~CSX1 &(~WRXn |~RDX):(n=0,1,2,3)

~SRAMWRX=~WRX3 |~WRX2 |~WRX1|~WRX0;

Symbol Min Typ Max Unit

UnitMaxTypMinSymbol

tPD

tPD 1.5

1.5 -

5.0

5.5

9.0

ns

ns

WRX0

WRX1WRX2WRX3

SRAMCSX2SRAMCSX1

SRAMCSX0LCX08 LCX32

SRAMBEX[3:0]

SRAMWRX

A[19:2]

•••1 MB

•••1 MB •••1 MB

8

3.4 FPGA

FPGA is mapped to the CS6 area. Following extended LAN controller and FPGA extended connec-tor are accessed through the FPGA.

Figure 6 Block diagram

Connection figureFor writing to either of the FPGA (APEX20KE1000) and Configuration Device (EPC16), the JTAG/ISPIF (CN2) is used and the device to write to is selected by the jumpers (J2 and J3). Once data is written to EPC16 selected as the write destination, it is loaded automatically to the FPGA in the serial configuration mode after a power-on reset.

Figure 7 Connection with configuration device

MEMBUS

MEMCSX2

MEMBUS IF(Address Decoder)

Extended BusConnector

Extended BusConnector

Extended LANController

I/F

DebugPort

ConfigurationBlockEP20K1500EFC EPC16

RJ45

JTAG/ISPInterface

Extended LAN

MB86967

Device : APEX20KE (EP20K1000EFC33-1X) PKG Type : 1020 pin Fine Line BGA Power supply voltage : I/O +3.3 V, Core +1.8 V

TDITMSTDO

TCK

JTAG Pin header

Serial Configuration Mode

TDI

TMS

TDO

TCKJ3

J23

3

1

1

EPC16

DATA0

DCLK

PGM[2:0]

nCS

nINIT CONFOE

TDO

TCK

TDI

TMS

DATA0

DCLK

nCEOnSTATUS

TRST

APEX20KE

INIT DONEnCINFIG

CONF DONE

J2, J3

PIN

3-21-2

Select Programming Deviceduring ISP Mode

Configuration Device (EPC16)FPGA (APEX20KE)

nINIT_CONF,OE and nCS pins of EPC16 should be used when the internal pull-up resistor sets ON (default:ON).

9

3.5 Extended LAN controller

The board has the built-in MB86967 as an external extended LAN controller in addition to the LAN controller built in MB91401. MB86967 is connected to the CS6 area via the FPGA.

• Part number : MB86967 (Fujitsu)

• Bus width : 16-bits


• Package : 100-pin QFP

For details of the extended LAN controller, refer to the "MB86967 Data Sheet".

Features• 10BASE-T external loop-back function (full-duplex operation)

• Byte swap of word data according to the host CPU

• High-speed burst DMA transfer and single DMA transfer functions (slave operation)

• Internal Manchester encoder/decoder and 10BASE-T transceiver conforming to the IEEE

802.3 standard

• Built-in Jabber control, link test, and SQE test functions

• Built-in polarity reversal detection/auto-correction function

• Built-in LED driver for monitoring network status: link test, collision, transmitting, and re-

ceiving

• 2-bank transmission buffer and ring-type reception buffer (Max 32 KB) that can be set for pro-

gram.

• Internal 64-bit hash table for multicast address filter

• Function to eliminate received long packets (received packets more than 1792 bytes)

• Standby mode and shutdown mode supported

Figure 8 Peripheral circuit of extended LAN controller

LEDThe board has the following LEDs for monitoring the network status.

Table 8 Description of LED

LED SLK Description

LED2 COL Collision generating

LED3 LINK Link testing status

LED4 TX Now sending

LED5 RX Now receiving

FPGA LANMB86967

TRANS RJ45

CN3

CSLA[4:0]LD[15:0]

SBXREADY

IOWIOWX

DHEXDREQ

DACKEOP

OSC20 MHz SRAM

Network Status LED

8

COL

LINK

TXRX

10

3.6 FPGA extended connector

Tow box type pin headers (32 pins × 2 rows each) are attached to the FPGA to connect 90 extended bus lines (EXA (39:0), EXB (49:0)) from the FPGA.

Figure 9 Pin assignment

FPGA

EXA

EXB

40

60

CN13

CN14

2.54 mm

2.54 mm

1 2

63 64

Connector : XG4G6431 (OMRON)

CN13 CN14Signal Pin Pin Signal Signal Pin Pin SignalVCC 64 63 VCC VCC 64 63 VCC GND 62 61 GND GND 62 61 GNDN.C. 60 59 N.C. EXB49 60 59 EXB48N.C. 58 57 N.C. EXB47 58 57 EXB46N.C. 56 55 N.C. EXB45 56 55 EXB44N.C. 54 53 N.C. EXB43 54 53 EXB42N.C. 52 51 N.C. EXB41 52 51 EXB40GND 50 49 GND GND 50 49 GND

EXA39 48 47 EXA38 EXB39 48 47 EXB38 EXA37 46 45 EXA36 EXB37 46 45 EXB36 EXA35 44 43 EXA34 EXB35 44 43 EXB34EXA33 42 41 EXA32 EXB33 42 41 EXB32 EXA31 40 39 EXA30 EXB31 40 39 EXB30 GND 38 37 GND GND 38 37 GND

EXA29 36 35 EXA28 EXB29 36 35 EXB28 EXA27 34 33 EXA26 EXB27 34 33 EXB26 EXA25 32 31 EXA24 EXB25 32 31 EXB24EXA23 30 29 EXA22 EXB23 30 29 EXB22EXA21 28 27 EXA20 EXB21 28 27 EXB20GND 26 25 GND GND 26 25 GND

EXA19 24 23 EXA18 EXB19 24 23 EXB18 EXA17 22 21 EXA16 EXB17 22 21 EXB16 EXA15 20 19 EXA14 EXB15 20 19 EXB14EXA13 18 17 EXA12 EXB13 18 17 EXB12EXA11 16 15 EXA10 EXB11 16 15 EXB10VCC 14 13 VCC VCC 14 13 VCCEXA9 12 11 EXA8 EXB9 12 11 EXB8EXA7 10 9 EXA6 EXB7 10 9 EXB6EXA5 8 7 EXA4 EXB5 8 7 EXB4EXA3 6 5 EXA2 EXB3 6 5 EXB2EXA1 4 3 EXA0 EXB1 4 3 EXB0GND 2 1 GND GND 2 1 GND

11

3.7 UART

Serial signal of MB91401 is connected to external part of board via level conversion IC.• 2ch

- Full-duplex double buffer.- Only asynchronous (start-stop synchronization) is supported. CLK synchronous commu-

nication cannot be used.- The data length between 7 and 9 bits and the presence or absence of parity can be set.- The baud rate can be set arbitrarily with the internal U-TIMER (see the figure 11).

• DTR-DSR and RTS-CTS are connected each other on board.

• Cable: Use a cross cable for connection to the host machine.

• Connector: D-Sub 9 pins (male)

Figure 10 Connection to MB91401 and level conversion IC (MAX3232)

RegisterFigure 11 shows UART related registers.For details on register settings, refer to MB91401 Hardware Manual.

Figure 11 UART relation register

SOUT0SIN0

SCK0

SOUT1

SIN1SCK1

MB91401MAX3232

Ch0

Ch1

Signal Remark1 DCD Detecting carrier2 RxD Receiving data3 TxD Sending data4 DTR Data terminal ready5 GND Ground6 DSR Data set ready7 RTS Sending request8 CTS Sending enable9 RI Displaying be received

SMR (Serial Mode Register)Set the operation mode of UART.

SCR (Serial Control Register)Control the transmitting protocol at serial transmitting.

SIDR (Serial Input Data Register)SODR (Serial Output Data Register)

Data buffer of sending/receivingSSR (Serial Status Register)

It is configured by the flag that shows UART operating status.DRCL (DMA Register Clear)

It is the register for clearing the interrupt source of DMAC.This register must be accessed by byte.

UTIM (U-TIMER)It shows the timer value (half word access only).

UTIMR (reload Register)It is the register that stores the reload value to UTIM at UTIM underflowing (half word access only).

UTIMC (U-TIMer Control Register)UTIMER control register (word access only).

15 8 7 00X0000_0060 SSR SIDR/SODR

ch00X0000_0062 SCR SMR0X0000_0064 UTIM(R)/UTIMR(W)0X0000_0066 DRCL UTIMC0X0000_0068 SSR SIDR/SODR

ch10X0000_006A SCR SMR0X0000_006C UTIM(R)/UTIMR(W)0X0000_006E DRCL UTIMC

Setting example of baud rate and reload value of U-TIMER

At UCC1 = 0

At UCC1 = 1

n : UTIMER (reload value)φ : Peripheral machine clock frequency(⋅≥34 MHz)

baud rate (bps)

25 MHz 20 MHz 12.5 MHzUTIMR UCC1 UTIMR UCC1 UTIMR UCC1

1200 650 0 520 0 324 12400 324 1 259 1 162 04800 162 0 129 0 80 19600 80 1 64 0 39 1

19200 39 1 31 1 19 138400 19 1 - -

bps =φ

(2n + 2) × 16

bps =φ

(2n + 3) × 16

12

3.8 USB

Series-B type connector which conforms to USB 2.0 FS (12 Mbps) is mounted.The CLK signal for the USB can be supplied selectively either from an external 48 MHz source or from the internal CLK. Use the on-board jumper (J7) to select either.

Type : Series-B (Function)

Figure 12 Connection to MB91401 and resistors

To satisfy USB specification requirements, stop pulling up the D+ line on the device side in order to prevent an incoming current via the D+ line from adversely affecting the device when no voltage is applied to the V-bus with the host and hub off. The board is designed on the assumption that the US-BINS pin of MB91401 inputs the V-bus signal regulated at 3.3 V as an interrupt signal and that D+ is pulled up upon completion of initialization setting for the USB macro in the interrupt routine. This is because it is needed to prevent firmware from pulling up D+ until the end of the initialization rou-tine because the function device must be ready to accept a transaction within 100 ms after the host (hub) senses a port connection (D+ pull-up). This measure is not required when the initialization rou-tine does not require 100 ms. In this case, the V-bus signal can be used to pull-up D+ as it is.The board uses either of the above control signal (UDPUP) from the FPGA or the V-bus signal by jumper-selecting as the D+ pull-up ON/OFF control signal.

J7 USB Clock Select

Open External CLK input (X5: 48 MHz)

Short Internal system clock

J8 USB D+ line pull-up CTL

1-2 Using the output signal from FPGA

3-2 Using V-bus signal

OSC48 MHz

USBINS

UDMUDP

USCKI

UCLKSEL

22Ω

FPGAUDPUP

USBINS 1.5K

1

2

34

120 kΩ47pFRC

V-Bus

D+GND

UCLKSEL1:Ext.CLK In (48 MHz)0:Internal System CLK

12

3 4

Series-B :Function

Pin assignmentpin#

1 V-bus2 D−3 D+4 GND

MB91401

D−

13

3.9 Ethernet MAC interface

The board has 10Base-T/100Base-T interface to be connected to the Ethernet MAC interface of MB91401. The Ethernet MAC interface built in MB91401 has the following features.

• Built-in 10/100M MAC compliant to IEEE 802.3

• RMII/MII interface (full-duplex/half-duplex supported)

• PHY device control SMI interface

• Packet filtering function integrated

- Reducing the CPU load using L2/L3/L4 packet filtering function

Figure 13 Connection with PHY device

LEDThe board has the following LEDs for monitoring the network status.

Table 9 Description of LED

LED SILK Description

LED6 SPEEDIt shows the state of 100BASE-T/10BASE-T. (ON: 100BASE-T / OFF: 10BASE-T)

LED7 LINK Display link status.

LED8 XMT Display the detail of sending status.

LED9 RCV Display the detail of receiving status.

PHYBCM5221KPTMB91401

OSC25 MHz

TRANS RJ45

SPEEDLINK

XMTRCV

Network Status LED

CN5

MDCLKMDIOTxD[3:0]

TxCLK

TxENRxD[3:0]

RxCLKRxDVRxERRxCRS

COL

14

3.10 External interface

The external interface signal pin (pin 22) of MB91401 is connected to the open pin header with 20 pins × 2 lines (2.54 mm pitch).

Figure 14 Pin assignment

The data bus width is determined depending on the EXIS16 state. The bit width is 16 or 8 bits when EXIS16 is "1" or "0", respectively. In 8 bits, EXD (15:8) is enabled and EXD (7:0) serves as an I/O pin for GPIO (7:0). The board allows the EXIS16 state to be selected with J1.

J1 Select EXD Data bit width (EXIS16)

Open 16 bits (Enabled EXD [15:0])

Short8 bits (Enabled EXD [15:8]) Note: EXD [7:0] = GPIO [7:0]

MB91401

EXD[15:0]

J1

CN11

1 2

4039

EXCSXEXWRXEXRDX

EXADREQTXDREQRX

EXIS16

Signal Pin Pin Signal VCC(+3.3V) 1 2 VCC(+3.3V)

EXD15 3 4 EXD14EXD13 5 6 EXD12EXD11 7 8 EXD10EXD9 9 10 EXD8GND 11 12 GND

EXD7/GPIO7 13 14 EXD6/GPIO6EXD5/GPIO5 15 16 EXD4/GPIO4EXD3/GPIO3 17 18 EXD2/GPIO2EXD1/GPIO1 19 20 EXD0/GPIO0

GND 21 22 GNDEXCSX 23 24 EXRDX EXA 25 26 EXWRXN.C. 27 28 N.C.N.C. 29 30 N.C.GND 31 32 GND

DREQRX 33 34 N.C.DREQTX 35 36 N.C.

N.C. 37 38 N.C.GND 39 40 GND

Connector : XG8W-4031 (OMRON)

2.54 mm

2.54 mm

15

3.11 Card interface

A Compact Flash card slot and an SD card slot are provided on the front and rear sides, respectively, as card interfaces. Each card slot is selected exclusively depending on the setting of the DIP switch (SW1.5pin : SDSEL).SW1.5pin : SDSEL

• ON (0) SD Card selected (Setting prohibited: MB91401) is not supported

• OFF (1) CF Card selected

CF card interfaceSelected when DIP switch (SW1.5pin : SDSEL) is OFF(1) at a reset.MB91401 supports memory mode and 3.3-V products only.

Table 10 PC card memory mode

* : Pull-up inside MB91401.

Note : I/O is polarity viewed from MB91401 side.

Pin No.

Signal Name Pin Type Connecting

destination Note Pin No.

Signal Name

Pin Type

Connecting destination Note

1 GND - - Ground 26 CD1X I CFCD1X *

2 D03 I/O CFD3 27 D11 I/O CFD11

3 D04 I/O CFD4 28 D12 I/O CFD12

4 D05 I/O CFD5 29 D13 I/O CFD13

5 D06 I/O CFD6 30 D14 I/O CFD14

6 D07 I/O CFD7 31 D15 I/O CFD15

7 CE1X O CFCE1X 32 CE2X O CFCE2X

8 A10 O CFA10 33 VS1X I CFVS1X *

9 OEX O CFOEX 34 IORDX O CFIORDX

10 A09 O CFA9 35 IOWRX O CFIOWRX

11 A08 O CFA8 36 WEX O CFWEX

12 A07 O CFA7 37 RDY/BSY I CFRDY *

13 VCC - Power 38 VCC - - Power

14 A06 O CFA6 39 CSELX O - PU 10 kΩ15 A05 O CFA5 40 VS2X I - PU 10 kΩ16 A04 O CFA4 41 RESET O MRSTX

17 A03 O CFA3 42 WAITX I CFWAITX *

18 A02 O CFA2 43 INPACKX I - PU 10 kΩ19 A01 O CFA1 44 REGX O CFREGX

20 A00 O CFA0 45 BVD2 I/O - PU 10 kΩ21 D00 I/O CFD0 46 BVD1 I/O - PU 10 kΩ22 D01 I/O CFD1 47 D08 I/O CFD8

23 D02 I/O CFD2 48 D09 I/O CFD9

24 WP I - PU 10 kΩ 49 D10 I/O CFD10

25 CD2X I CFCD2X * 50 GND - - Ground

16

SD card interface (setting prohibited: MB91401 is not supported)Selected when DIP switch (SW1.5pin : SDSEL) is ON (0) at a reset.A connector is mounted which conforms to SD Memory Card "Physical Layer Specification 1.0".

Table 11 Pin assignment

Pin No. Signal Name Pin Type Connecting destination

1 CD/DAT3 I/O CFA3

2 CMD I/O CFA5

3 VSS1 Power GND

4 VDD Power +3.3V

5 CLK I CFA8

6 VSS2 Power GND

7 DAT0 I/O CFA0

8 DAT1 I/O CFA1

9 DAT2 I/O CFA2

10 LOCK - GND

11 WP - CFA6

12 CD - CFCD1X

17

3.12 Debug port

A high-density Mictor connector is mounted as a logic analyzer connector.

Figure 15 Connection of Mictor connector

MB91401 FPGA

D[31:0]A[23:0]WRX[3:0]RDXCSX0CSX1CSX6MCLK0CKE*ERAS*CAS*WEX*RDY*NMIX*INT[7:5]*

EXD[15:0]XAXCSXXRDXXWRXREQRXREQTX

FPGAEXA[31:0]**EXB[31:0]**EXC[31:0]***

* : It is only connected to TP(test point)pin.** : It is only connected each 32-line from EXA[39:0] and EXB[49:0] that

are connected to extended connector.*** : It is only connected to FPGA-Mictor connector.

CN15 CN16 CN17

ME

MD

Signal Pin Pin Signal

ME

MA

.ME

M_C

TL


EX

T.B

us

Signal Pin Pin SignalN.C. 1 2 N.C. N.C. 1 2 N.C. N.C. 1 2 N.C. GND 3 4 N.C. GND 3 4 N.C. GND 3 4 N.C.CSX0 5 6 CSX1 MCLK0 5 6 CSX6 N.C. 5 6 N.C.D31 7 8 D15 N.C. 7 8 A15 EXCSX 7 8 EXD15D30 9 10 D14 N.C. 9 10 A14 EXA 9 10 EXD14D29 11 12 D13 N.C. 11 12 A13 EXRDX 11 12 EXD13D28 13 14 D12 RDX 13 14 A12 EXWRX 13 14 EXD12D27 15 16 D11 WRX0 15 16 A11 DREQRX 15 16 EXD11D26 17 18 D10 WRX1 17 18 A10 DREQTX 17 18 EXD10D25 19 20 D9 WRX2 19 20 A9 P22 19 20 EXD9D24 21 22 D8 WRX3 21 22 A8 P23 21 22 EXD8D23 23 24 D7 A23 23 24 A7 P24 23 24 EXD7D22 25 26 D6 A22 25 26 A6 P25 25 26 EXD6D21 27 28 D5 A21 27 28 A5 P26 27 28 EXD5D20 29 30 D4 A20 29 30 A4 P27 29 30 EXD4D19 31 32 D3 A19 31 32 A3 P28 31 32 EXD3D18 33 34 D2 A18 33 34 A2 P29 33 34 EXD2D17 35 36 D1 A17 35 36 A1 P30 35 36 EXD1D16 37 38 D0 A16 37 38 A0 P31 37 38 EXD0

CN18 CN19 CN20

EX

A to

FP

GA


EX

B to

FP

GA


EX

C to

FP

GA

Signal Pin Pin SignalN.C. 1 2 N.C. N.C. 1 2 N.C. N.C. 1 2 N.C. GND 3 4 N.C. GND 3 4 N.C. GND 3 4 N.C.

EXA33 5 6 EXA32 EXB33 5 6 EXB32 N.C. 5 6 TP11EXA31 7 8 EXA15 EXB31 7 8 EXB15 EXC31 7 8 EXC15EXA30 9 10 EXA14 EXB30 9 10 EXB14 EXC30 9 10 EXC14EXA29 11 12 EXA13 EXB29 11 12 EXB13 EXC29 11 12 EXC13EXA28 13 14 EXA12 EXB28 13 14 EXB12 EXC28 13 14 EXC12EXA27 15 16 EXA11 EXB27 15 16 EXB11 EXC27 15 16 EXC11EXA26 17 18 EXA10 EXB26 17 18 EXB10 EXC26 17 18 EXC10EXA25 19 20 EXA9 EXB25 19 20 EXB9 EXC25 19 20 EXC9EXA24 21 22 EXA8 EXB24 21 22 EXB8 EXC24 21 22 EXC8EXA23 23 24 EXA7 EXB23 23 24 EXB7 EXC23 23 24 EXC7EXA22 25 26 EXA6 EXB22 25 26 EXB6 EXC22 25 26 EXC6EXA21 27 28 EXA5 EXB21 27 28 EXB5 EXC21 27 28 EXC5EXA20 29 30 EXA4 EXB20 29 30 EXB4 EXC20 29 30 EXC4EXA19 31 32 EXA3 EXB19 31 32 EXB3 EXC19 31 32 EXC3EXA18 33 34 EXA2 EXB18 33 34 EXB2 EXC18 33 34 EXC2EXA17 35 36 EXA1 EXB17 35 36 EXB1 EXC17 35 36 EXC1EXA16 37 38 EXA0 EXB16 37 38 EXB0 EXC16 37 38 EXC0

EXC

Memory bus IF

Extended bus IF

EXAEXB

Extended connector

CN17

CN15CN16

Mictor

Mic

tor

Mic

tor

Mic

tor

Ext

ende

d co

nnec

tor

CN18

CN19

CN20

18

3.13 LED/DIP switch

8 LEDs and 2 DIP switches are connected to the FPGA for extension purposes.

Figure 16 Setup of SW2 and SW3, and connection of LED

FPGA16

8

DIPSWSW2

FPGAPin#

DIPSWSW3

FPGAPin# LED FPGA

Pin#DIPSW0 AC14 DIPSW8 AF17 LED11 AD19DIPSW1 AB14 DIPSW9 AE17 LED12 AC19DIPSW2 AC15 DIPSW10 AD17 LED13 AB19DIPSW3 AB15 DIPSW11 AC17 LED14 AD20DIPSW4 AF16 DIPSW12 AB17 LED15 AC20DIPSW5 AE16 DIPSW13 AD18 LED16 AD21DIPSW6 AC16 DIPSW14 AC18 LED17 AB23DIPSW7 AB16 DIPSW15 AB18 LED18 AB24

19

3.14 Interrupt

The CPU core of MB91401 has eight external interrupt pins, five of which are used for MB91401 internal interrupts and the other three are connected to the FPGA as external interrupt signal (INT(2:0)) and NMIX pins. The FPGA is input interrupt requests from the extended LAN controller (LAN_INTX) and extended connector (EXT_INTX) and inputs them to MB91401 via FPGA. Inter-rupt signals input to the CPU core are assigned as following table. To set external interrupt enables, interrupt requests, and detection of interrupt requests, use the ENIR (external interrupt enable register), EIRR (external interrupt source register), and ELVR (request level setting register) of MB91401.For interrupt sources from each macro, refer to the relevant manual.

Figure 17 Connection of interrupt signal

Table 12 Interrupt source

External interrupt pin name of CPU core Interrupt source Active level

NMIX NMIX (connecting to FPGA) Low

INT[7] External interrupt pin INT[7] (connecting to FPGA) -



INT[4]Logical sum from USB controller, I2C interface, and CARD interface

High

INT[3] Logical sum from External interface and GPIO High

INT[2] Logical sum from IPsec accelerator and encryption macro. High

INT[1] Authentication macro High

INT[0] Ethernet MAC interface High

FR70E Core

INT[7]

INT[6]INT[5]

INT[4]

INT[3]

INT[2]INT[1]

INT[0]

INT5INT6INT7

NMIX

FPGA

EXT INTX

LAN INTX

ExternalConnector

LANMB86967

USBC | I2C | CARD IFEXIF | GPIOIPsec Accelerator | Encryption macro

Ethernet MAC IFAuthentication macro

MB91401

20

3.15 Reset

The board can generate a hardware reset under the following conditions.• At power ON (power-on reset)

• Set SW5 (reset switch) to ON (momentary operation).

• Be shorted J17

• Reset request from hardware emulator debugger (during use)

If any of these resets occurs, the reset applies to all the devices that have an on-board reset pin. The reset is released (Min) 280 ms after the power supply becomes stable at a power-on reset or after the reset source is removed otherwise.

Figure 18 Reset timing

To use the hardware emulator debugger, set J18 to the "3-2" side to generate PLLRST and system reset signals using the ICERSTX output as the source. For normal use, set J18 to the "1-2" side.

Figure 19 Reset circuit

MB91401 can also generate a software reset by setting the watchdog timer or internal register set-ting. A software reset does not reset to any external device. For details, refer to “MB91401 Hardware Manual”.

J17 Spare Reset

OpenNormal

Reset

J18 System RST select

1-2 System Reset

3-2 ICE RST

PLLRST is set transition to “H” after 140-ms has passed after power supply stabilization (3.3 V).System reset (MRSTX) is set transition to “H” after 140 ms has passed after PLLRST releasing.

140 ms

140 ms

3.3 V

PLLRST

MRSTX

3.3 V2.93 V

EmulatorConnector

SW5J17

INITRSTX

ICERSTX

Power supplymonitor circuit

Power supplymonitor circuit

PLLRST

MRSTX

MRST

MB91401

MB91401

Flash

BCM5221

LAN Controller (MB86967)

J18

21

3

INIT_DONE

21

3.16 Emulator interfaceThe board has an interface connector for the Fujitsu DSU-FR20/30 emulator (MB2197-01) for eval-uation and verification purposes.For details of the DSU-FR20/30 emulator, refer to the following relevant documents.

• DSU-FR20/30 emulator debugger manual

• DSU-FR20/30 emulator debugger hardware manual

• DSU-FR20/30 emulator debugger install manual

Note : Power-on and shutdown sequences.• The power-on sequence must be performed in the order described in the DSU-FR20/30 emu-

lator debugger manual. The device malfunction can be caused.

• Once you have turned on the emulator, do not turn off and on the power to the board. The de-

vice malfunction can be caused.

• After turning the power on, do not carry or apply shock or vibration to it. The device malfunc-

tion can be caused.

• To power on, turn on the host machine → emulator → this board in this order after all oper-

ations of the connection is terminated.

• To shut down, turn off this board → emulator → host machine in this order.

22

3.17 Power supplyThe following 5V/4A switching AC adapter is attached to the board.AC adapter

• Part number: NT24-1S0540 (Akizuki)

• Input: 100V 50/60 MHz 50-60 VA

• Output: DC 5 V-4 A

Each power supply (3.3 V, 2.8 V, and 1.8 V) is generated by the on-board regulator. The total power supply and current rough estimations by major devices are shown below (The cal-culation for MB91401 assumes about 500 mA).

Table 13 Power supply assignment

Device QtyPower supply

5 V 3.3 V 1.8 V

Network Controller MB91401 1 −(External) (Internal)

FPGAAPEX20KE1000EFC-1X 1 −

EPC16 1 − −

Flash MBM29LVT-160T-80K 4 − −

SRAM GS74116 8 − −

LAN Controller

MB86967 1 − −

TC55257 1 − −

S556-9003-09 1 − −

PHY BCM5221 1 − −

Pulse Trans S558-5999-W2 1 − −

Level Shifter PI5C3244 4 − −

Regulator MIC29302BU 3 3 − −

Serial MAXS3232E 1 − −

23

CM71-10401-1E

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

FR FAMILYEVALUATION BOARD For MB91401MB91941EBREFERENCE MANUAL

August 2005 the first edition

Published FUJITSU LIMITED Electronic Devices

Edited Business Promotion Dept.

mb91941eb reference manual - · pdf filemb91941eb reference manual . i preface overview this...

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