max5051 parallelable, clamped two-switch power-supply ... · flyback configurations with input...

General DescriptionThe MAX5051 is a clamped, two-switch power-supply controller IC. This device can be used both in forward or flyback configurations with input voltage ranges from 11V to 76V. It provides comprehensive protection mechanisms against possible faults, resulting in very high reliability power supplies. When used in conjunction with secondary side synchronous rectification, power-supply efficiencies can easily reach 92% for a +3.3V output power supply operated from a 48V bus. The integrated high- and low-side gate drivers provide more than 2A of peak gate-drive current to two external N-channel MOSFETs. Low startup current reduces the power loss across the bootstrap resistor. A feed-forward voltagemode topology provides excellent line rejection while avoiding the pitfalls of tradi-tional current-mode control.The MAX5051 power-supply controller is primary as well as secondary-side parallelable, allowing the design of scaleable power systems when necessary. When paral-leling the primary side, dedicated pins allow for simultane-ous wakeup or shutdown of all paralleled units, thus pre-venting current-hogging during startup or fault conditions.The MAX5051 generates a lookahead signal for driving secondary-side synchronous MOSFETs. Special primary-side synchronization inputs/outputs allow two primaries to be operated 180° out of phase for increased output power and lower input ripple currents.The MAX5051 is available in a 28-pin TSSOP-EP pack-age and operates over a wide -40°C to +125°C tempera-ture range.Warning: The MAX5051 is designed to work with high voltages. Exercise caution.

Applications High-Efficiency, Isolated Telecom/Datacom

Power Supplies 48V and 12V Server Power Supplies 48V Power-Supply Modules Industrial Power Supplies

Features Wide Input Voltage Range, 11V to 76V Voltage Mode with Input Voltage Feed-Forward Ripple-Phased Parallel Topology for High Current/

Power Output 2A Integrated High- and Low-Side MOSFET Drivers SYNCIN And SYNCOUT Pins Enable 180° Out-Of-

Phase Operation Programmable Brownout and Bootstrap UVLOs High-Side Driver Bootstrap Capacitor Precharge

Driver Low Current-Limit Threshold for High Efficiency Programmable Switching Frequency Reference Voltage Soft-Start for Startup Without

Overshoots Startup Synchronization with Multiple Paralleled

Primaries Programmable Integrating Current-Limit Fault

Protection Look-Ahead PWM Signal for Secondary-Side

Synchronous Rectifier Drivers Look-Ahead Drivers for Either A High-Speed

Optocoupler or Pulse Transformer Wide -40°C to +125°C Operating Range Thermally Enhanced 28-Pin TSSOP Package

Pin Configuration appears at end of data sheet.

*Contact factory for availability.**EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX5051AUI* -40°C to +85°C 28-TSSOP-EP**

MAX5051 Parallelable, Clamped Two-Switch Power-Supply Controller IC

19-2964; Rev 2; 5/14

Ordering Information

EVALUATION KIT AVAILABLE

AVIN, PVIN, XFRMRH to GND .............................-0.3V to +80VBST to GND ..........................................................-0.3V to +95VBST, DRVH to XFRMRH .......................................-0.3V to +12VREG9, DRVDD, DRVL to GND .............................-0.3V to +12VDRVB, LXVDD, LXL, LXH to GND ........................-0.3V to +12VUVLO, STT, COMP, CON to GND.........................-0.3V to +12VFLTINT, RCFF to GND ..........................................-0.3V to +12VREG5, CS, CSS, FB to GND ..................................-0.3V to +6VSTARTUP, SYNCIN to GND ....................................-0.3V to +6VSYNCOUT, RCOSC to GND ...................................-0.3V to +6VPGND to GND ......................................................-0.3V to +0.3VLXL, LXH Current Continuous ..........................................±50mADRVL, DRVH Current Continuous .................................±100mA

DRVL, DRVH Peak Current (<500ns) ...................................±5APVIN, REG9 Continuous Current ...................................+120mAREG5 Continuous Current ...............................................+80mADRVB, RCFF, RCOSC, CSS Continuous Current ...........±20mACOMP, SYNCOUT Continuous Current ...........................±20mAREG9, REG5, and COMP Short to GND ..................ContinuousContinuous Power Dissipation (TA = +70°C) 28-Pin TSSOP (derate 23.8mW/°C above +70°C) ....1905mWOperating Temperature Range ......................... -40°C to +125°CMaximum Junction Temperature (TJ) ..............................+150°CStorage Temperature Range ............................ -65°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

(Note 1)TSSOP

Junction-to-Ambient Thermal Resistance (θJA) ..........42°C/W

(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 = 4.7μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. All driver, voltage-regulator, and refer-ence outputs unconnected except for bypass capacitors.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSSUPPLY CURRENT (AVIN, PVIN)

AVIN Standby Current IASTBYVAVIN = VPVIN = 11V to 76V; VSTARTUP = VCS = 0V; VBST = VXFRMRH = VDRVDD = VREG9; RCFF floating

300 450 µA

PVIN Standby Current IPSTBY 400 650 µA

AVIN Supply Current IAVINVAVIN = VPVIN = 11V to 76V; VCS = 0V; VBST = VDRVDD = VREG9; VXFRMRH = 0V; STARTUP, RCFF floating

0.65 1 mA

PVIN Supply Current IPVIN 8 12 mA

AVIN Input Voltage Range Inferred from AVIN supply current test 11 76 V

+9V LDO (REG9)PVIN Input Voltage Range VPVIN Inferred from PVIN supply current test 11 76 V

REG9 Output-Voltage Set Point VREG9 VPVIN = 11V 8.3 9.0 V

REG9 Line Regulation VPVIN = 11V to 76V 0.1 mV/V

REG9 Load Regulation IREG9 = 0 to 80mA 250 mV


www.maximintegrated.com Maxim Integrated 2

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

Package Thermal Characteristics

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.


REG9 Dropout Voltage IREG9 = 80mA 0.5 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSREG9 Undervoltage Lockout Threshold VREG9 falling 5.7 6.7 V

REG9 Undervoltage Lockout Threshold Hysteresis 750 mV

+5V LDO (REG5)

REG5 Output-Voltage Set Point VREG5 4.8 5.1 V

REG5 Load Regulation IREG5 = 0 to 40mA 50 mV

REG5 Dropout Voltage IREG5 = 40mA, measured with respect to VREG9

0.5 V

SOFT-START/REFERENCE (CSS)

Reference Voltage VCSS 1.125 1.235 1.255 V

Soft-Start Pullup Current ICSS 70 µA

ERROR AMPLIFIER (CSS, FB, COMP)

FB Input Range VFB Inferred from FB offset voltage test 0 3 V

FB Input Current IFB VFB = VREF ±250 nA

COMP Output Range Inferred from FB offset voltage test 2.1 6.0 V

COMP Output Sink Current VFB = 3V 20 mA

COMP Output Source Current VFB = 0V 30 mA

Open-Loop Gain GA 2.1V < VCOMP < 6V 80 dB

Unity-Gain Bandwidth BW CCOMP = 50pF, ICOMP = ±5mA 3 MHz

FB Offset Voltage VOSVFB = 0 to 3V; VCOMP = 2.1V to 6V; ICOMP = -5mA to +5mA -3 +3 mV

COMP Output Slew Rate SR CCOMP = 50pF 1 v/µs

PVIN UNDERVOLTAGE LOCKOUT (STT)

PVIN Undervoltage Lockout VPVIN rising 22 23.5 25 V

STT Threshold VSTT VSTT rising 1.18 1.24 1.30 V

STT Input Impedance RSTT 100 kΩ

INTEGRATING FAULT PROTECTION (FLTINT)

FLTINT Source Current IFLTINT μA

FLTINT Shutdown Threshold VFLTINTSD V

FLTINT Restart Hysteresis VFLTINTHY V



Electrical Characteristics (continued)


PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSCILLATOR (RCOSC, SYNCIN, SYNCOUT)

PWM Period tS RRCOSC = 24kΩ, CRCOSC = 100pF 3.9 μs

Maximum PWM Duty Cycle DMAX RRCOSC = 24kΩ, CRCOSC = 100pF 48 %

Maximum RCOSC Frequency fRCOSCMAX 1 MHz

Maximum SYNCIN Frequency fSYNCIN 50% duty cycle 500 kHz

SYNCIN High-Level Voltage VHSYNCIN Pulse rising 2.1 V

SYNCIN Low-Level Voltage VLSYNCIN Pulse falling 0.8 V

SYNCIN Pulldown Resistor 100 kΩ

SYNCIN Rising to SYNCOUT Falling Delay 30 ns

SYNCIN Falling to SYNCOUT Rising Delay 70 ns

SYNCOUT Voltage High Sourcing 1.2mA 4.5 5.1 V

SYNCOUT Voltage Low Sinking 2.4mA 0.3 V

RCOSC Peak Trip Level VTH 2.5 V

RCOSC Valley Trip Level 0.2 V

RCOSC Input Bias Current -0.3 μA

RCOSC Discharge MOSFET RDS(ON)

Sinking 10mA 50 100 Ω

RCOSC Discharge Pulse Width 50 ns

UNDERVOLTAGE LOCKOUT (UVLO)

UVLO Threshold VUVLO VUVLO rising 1.18 1.24 1.30 V

UVLO Hysteresis VHYS 130 mV

UVLO Input Bias Current IBUVLO VUVLO = 2.5V -100 +100 nA

PWM COMPARATORRCFF Input Voltage Range 0 3 V

Feed-Forward Discharge MOSFET RDS(ON)

RDS(RCFF) Sinking 10mA 50 100 Ω

CON Input Voltage Range 0 6 V

RCFF Level-Shift Voltage VCPWM 2.2 2.4 V






CON Input Bias Current ICON -2 +2 μA

Propagation Delay to Output tdCPWMDRVH, DRVL = unconnected, overdrive = 50mV, measured from CON to DRVL 90 ns

SYNCHRONOUS RECTIFIER PULSE TRANSFORMER DRIVER (LXVDD, LXH, LXL)

High-Side MOSFET R DS(ON) RDSLXH LXH sourcing 10mA, VLXVDD = VREG5 3 6.5 12 Ω

Low-Side MOSFET RDS(ON) RDSLXL LXL sinking 10mA, VLXVDD = VREG5 2.0 5 10 Ω

LXH Rising to DRVL Rising Delay 90 ns

CURRENT-LIMIT COMPARATOR (CS)

Current-Limit Threshold Voltage VILIM 144 154 164 mV

Current-Limit Input Bias Current IBILIM 0 < VCS < 0.3V -2 +2 μA

Propagation Delay to Output tdILIMDRVH, DRVL = unconnected, overdrive = 10mV, measured from CS to DRVL 100 ns

LOW-SIDE MOSFET DRIVER (DRVDD, DRVL, PGND)

Peak Source Current VDRVL = 0V, pulse width < 100ns; VDRVDD = VREG9

2 A

Peak Sink Current VDRVL = VREG9, pulse width < 100ns; VDRVDD = VREG9

3 A

DRVL Resistance Sourcing IDRVL = 50mA, VDRVDD = VREG9 1.7 3.5 Ω

DRVL Resistance Sinking IDRVL = -50mA, VDRVDD = VREG9 0.6 1.4 Ω

HIGH-SIDE MOSFET DRIVER (BST, DRVH, XFRMRH)

Peak Source Current VDRVH = GND, pulse width < 100ns, VBST = VREG9, VXFRMRH = 0V 2 A

Peak Sink Current VDRVH = VBST, pulse width < 100ns, VBST = VREG9, VXFRMRH = 0V 5 A

DRVH Resistance Sourcing IDRVH = 50mA, VBST = VREG9, VXFRMRH = 0V 1.7 3.5 Ω

DRVH Resistance Sinking IDRVH = -50mA, VBST = VREG9, VXFRMRH = 0V 0.6 1.4 Ω

Skew Between Low-Side and High-Side Drivers 0 ns





(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7μF, CREG5 = 4.7μF, TA = +25°C, unless otherwise noted.)


BOOST CAPACITOR CHARGE MOSFET (DRVB)

DRVB Resistance Sourcing IDRVB = 50mA 8 35 Ω

DRVB Resistance Sinking IDRVB = 50mA 5 35 Ω

Delay from Clock Fall 200 ns

One-Shot Pulse Width 300 ns

STARTUP (STARTUP)

Startup Threshold VSTARTUP VSTARTUP rising 1.4 2.1 V

Startup Threshold Hysteresis 330 mV

Internal Pullup Current ISTARTUP 50 100 μA

STARTUP Pulldown MOSFET RDS(ON)

Sinking 10mA Ω

OVERTEMPERATURE SHUTDOWN

Shutdown Junction Temperature Temperature rising 150 °C

Hysteresis 10 °C

AVIN STANDBY CURRENTvs. TEMPERATURE

MAX

5051

toc0

2

TEMPERATURE (°C)

AVIN

STA

NDBY

CUR

RENT

(µA)

1007525 500-25

210

220

230

240

250

260

270

280

200

190

180-50 125

VUVLO = 0V

PVIN STANDBY CURRENTvs. SUPPLY VOLTAGE

MAX

5051

toc0

3

PVIN SUPPLY VOLTAGE (V)

PVIN

STA

NDBY

CUR

RENT

(µA)

706050403020

100

200

300

400

500

600

010 80

VUVLO = 0V

AVIN STANDBY CURRENTvs. AVIN SUPPLY VOLTAGE

MAX

5051

toc0

1

AVIN SUPPLY VOLTAGE (V)

AVIN

STA

NDBY

CUR

RENT

(µA)

706040 503020

210

220

230

240

250

260

270

280

290

300

20010 80

VUVLO = 0V




Typical Operating Characteristics


PVIN STARTUP VOLTAGEvs. TEMPERATURE

MAX

5051

toc0

5

TEMPERATURE (°C)

PVIN

STA

RTUP

VOL

TAGE

(V)

1007550250-25

23.1

23.2

23.3

23.4

23.5

23.6

23.0-50 125

STT = FLOATING

REG9 OUTPUT VOLTAGEvs. REG9 OUTPUT CURRENT

MAX

5051

toc0

8

REG9 OUTPUT CURRENT (mA)

REG9

OUT

PUT

VOLT

AGE

(V)

14012080 10040 6020

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

9.0

8.00 160

REG9 OUTPUT VOLTAGEvs. PVIN VOLTAGE

MAX

5051

toc0

6

PVIN VOLTAGE (V)

REG9

OUT

PUT

VOLT

AGE

(V)

706050403020

8.793

8.796

8.799

8.802

8.805

8.97010 80

REG5 OUTPUT VOLTAGEvs. REG5 OUTPUT CURRENT

MAX

5051

toc0

9

REG5 OUTPUT CURRENT (mA)

REG5

OUT

PUT

VOLT

AGE

(V)

8070605040302010

4.4

4.8

5.2

5.6

6.0

4.00 90

PVIN STANDBY CURRENTvs. TEMPERATURE

MAX

5051

toc0

4

TEMPERATURE (°C)

PVIN

STA

NDBY

CUR

RENT

(µA)

1007550250-25

100

200

300

400

500

600

0-50 125

VUVLO = 0V

REG9 OUTPUT VOLTAGEvs. TEMPERATURE

MAX

5051

toc0

7

TEMPERATURE (°C)

REG9

OUT

PUT

VOLT

AGE

(V)

1007525 500-25

8.72

8.74

8.76

8.78

8.80

8.82

8.84

8.86

8.88

8.90

8.70-50 125


Maxim Integrated 7www.maximintegrated.com

Typical Operating Characteristics (continued)


AVIN SUPPLY CURRENTvs. TEMPERATURE

MAX

5051

toc1

1

TEMPERATURE (°C)

AVIN

SUP

PLY

CURR

ENT

(µA)

1007550250-25

100

200

300

400

500

600

700

0-50 125

VUVLO = 0V

CSS SOFT-START CURRENTvs. TEMPERATURE

MAX

5051

toc1

4

TEMPERATURE (°C)

CSS

SOFT

-STA

RT C

URRE

NT (µ

A)

1007550250-25

65

70

75

80

85

90

60-50 125

FLTINT CURRENT vs. TEMPERATURE

MAX

5051

toc1

7

TEMPERATURE (°C)

FLTI

NT C

URRE

NT (µ

A)

1007525 500-25

86

85

87

88

8990

9192

93

94

95

-50 125

PVIN SUPPLY CURRENTvs. TEMPERATURE

MAX

5051

toc1

2

TEMPERATURE (°C)

PVIN

SUP

PLY

CURR

ENT

(mA)

1007550250-25

6.7

6.8

6.9

7.0

7.1

7.2

6.6-50 125

VPVIN = 12V

UVLO THRESHOLD vs. TEMPERATURE

MAX

5051

toc1

5

TEMPERATURE (°C)

UVLO

(V)

10075-25 0 25 50

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.200-50 125

RCFF LEVEL-SHIFT VOLTAGEvs. TEMPERATURE

MAX

5051

toc1

8

TEMPERATURE (°C)

RCFF

LEVE

L-SH

IFT

VOLT

AGE

(V)

1007525 500-25

2.21

2.22

2.23

2.24

2.25

2.26

2.27

2.28

2.29

2.30

2.20-50 125

REG5 OUTPUT VOLTAGEvs. TEMPERATURE

MAX

5051

toc1

0

TEMPERATURE (°C)

OUTP

UT V

OLTA

GE (V

)

1007525 500-25

4.9914.9924.9934.9944.9954.9964.9974.9984.9995.0005.001

4.990-50 125

SOFT-START/REFERENCE VOLTAGEvs. TEMPERATURE

MAX

5051

toc1

3

TEMPERATURE (°C)

SOFT

-STA

RT/R

EFER

ENCE

VOL

TAGE

(V)

1007525 500-251.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

-50 125

STT STARTUP THRESHOLDvs. TEMPERATURE

MAX

5051

toc1

6

TEMPERATURE (°C)

STT

(V)

10075-25 0 25 50

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.200-50 125






-20

0

20

40

60

80

100 270

240

210

180

150

120

90

60

30

0

OPEN-LOOP GAIN/PHASEvs. FREQUENCY

FREQUENCY (kHz)0.01 10 100 10000.1 1 10,000

GAIN

(dB)

PHAS

E (D

EGRE

ES)

MAX5051 toc20

GAIN

PHASE

LXL AND LXH RDSONvs. TEMPERATURE

MAX

5051

toc2

3

TEMPERATURE (°C)

R DSO

N (Ω

)

8560-15 10 35

5

6

7

8

9

10

11

12

4-40 110

LXH SOURCING 10mA

LXH SINKING 10mA

SYNCIN TO SYNCOUT PROPAGATIONDELAY vs. TEMPERATURE

MAX

5051

toc2

6

TEMPERATURE (°C)

PROP

AGAT

ION

DELA

Y (n

s)

1007525 500-25

40

50

60

70

80

90

100

110

120

130

30-50 125

SYNCIN FALLTO SYNCOUT RISE

SYNCIN RISE TO SYNCOUT FALL

COMP OUTPUT VOLTAGEvs. TEMPERATURE

MAX

5051

toc2

1

TEMPERATURE (°C)

COMP

OUT

PUT

VOLT

AGE

(V)

10075-25 0 25 50

1

2

3

4

5

6

7

8

0-50 125

ISOURCE = 5mA

ISINK = 5mA

SWITCHING PERIOD vs. RRCOSC

MAX

5051

toc2

4

RRCOSC (kΩ)

SWIT

CHIN

G PE

RIOD

(µs)

1601208040

5

10

15

20

25

30

35

40

45

50

00 200

DRVH MAXIMUM DUTY CYCLEvs. TEMPERATURE

MAX

5051

toc2

7

TEMPERATURE (°C)

DRVH

DUT

Y CY

CLE

(%)

1007525 500-25

46.4

46.8

47.2

47.6

48.0

48.4

48.8

49.2

49.6

50.0

46.0-50 125

CURRENT-LIMIT THRESHOLDvs. TEMPERATURE

MAX

5051

toc1

9

TEMPERATURE (°C)

CS T

HRES

HOLD

VOL

TAGE

(mV)

1007550250-25

145

150

155

160

165

170

140-50 125

DRVH AND DRVL RDSONvs. TEMPERATURE

MAX

5051

toc2

2

TEMPERATURE (°C)

R DSO

N (Ω

)

10075-25 0 25 50

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0-50 125

DRVH AND DRVL SOURCING 50mA

DRVH AND DRVL SINKING 50mA

NORMALIZED SWITCHING FREQUENCYvs. TEMPERATURE

MAX

5051

toc2

5

TEMPERATURE (°C)

NORM

ALIZ

ED S

WIT

CHIN

G FR

EQUE

NCY

1007550250-25

0.960

0.970

0.980

0.990

1.000

1.010

1.020

0.950-50 125

SWITCHING




PIN NAME FUNCTION

1 RCOSC Reset Input. Drive RESET low to clear all latches and registers (all outputs are turned off). All OUT pulldown currents are disabled when RESET = low.

2 SYNCOUT Synchronization Output. Synchronization signal to drive SYNCIN of a second MAX5051, if used.

3 RCFF Feed-Forward Input. Connect a resistor from RCFF to AVIN and a capacitor from RCFF to GND. This is the PWM ramp.

4 CON PWM Comparator Noninverting Input. Connect CON to the optocoupler output for isolated applications, or to COMP for nonisolated applications.

5 CSS Soft-Start and Reference. Connect a 0.01μF or greater capacitor from CSS to GND. The 1.24V reference voltage appears across this capacitor.

6 COMP Internal Error Amplifier Output.

7 FB Feedback Input. Inverting input of the internal error amplifier. The soft-started reference is connected to the noninverting input of this amplifier.

8 REG5 5V Linear Regulator Output. Bypass REG5 to GND with a 4.7μF ceramic capacitor.

9 REG9 9V Linear Regulator Output. Bypass REG9 to GND with a 4.7μF ceramic capacitor.

10 PVIN

Regulator Voltage Input. Voltage input to the internal 5V and 9V linear regulators. A high-value resistor connected from the input supply to PVIN provides the necessary current to charge up the startup capacitor, and the 400μA standby current required by the MAX5051. After startup, the output of a tertiary winding is used to provide continued bias to the controller.

11 STTStartup Threshold Input. Leave STT floating for a default startup voltage of 24V at PVIN. STT can be modified by connecting external resistors. For high accuracy, choose external resistors with 50kΩ or less impedance looking back into the divider.

12 LXVDD Supply Input for the Secondary-Side Synchronous Pulse Transformer or Optocoupler Driver. LXVDD is normally connected to REG5.

CON TO DRVL PROPAGATION DELAYvs. TEMPERATURE

MAX

5051

toc2

8

TEMPERATURE (°C)

PROP

AGAT

ION

DELA

Y (n

s)

1007525 500-25

65

70

75

80

85

90

95

100

105

110

60-50 125

50mV OVERDRIVE

CS CURRENT LIMIT TO DRVHPROPAGATION DELAY vs. TEMPERATURE

MAX

5051

toc2

9

TEMPERATURE (°C)PR

OPAG

ATIO

N DE

LAY

(ns)

1007550250-25

90

100

110

120

130

140

150

80-50 125

50mV OVERDRIVE




Pin Description

PIN NAME FUNCTION

13 LXHSynchronous-Pulse Transformer Driver, PMOS Open Drain. LXH is the high-side driver for the secondaryside synchronous-pulse transformer. LXH can also drive a high-speed switching optocoupler. If not used, connect LXH to LXVDD.

14 LXLSynchronous-Pulse Transformer Driver, NMOS Open Drain. LXL is the low-side driver for the secondaryside synchronous-pulse transformer. LXL can also drive a high-speed switching optocoupler. If not used, connect LXL to PGND.

15 CS Current-Sense Input. The current-limit threshold is internally set to 156mV relative to PGND. The device has an internal noise filter. If necessary, connect an additional external RC filter.

16 DRVL Gate-Drive Output for Low-Side MOSFET. DRVL is capable of sourcing and sinking approximately 2A peak current.

17 PGND Power Ground.

18 DRVDD Supply Input for Low-Side MOSFET Driver. Bypass DRVDD locally with good quality 1μF || 0.1μF ceramic capacitors. DRVDD is normally connected to REG9.

19 DRVBGate-Drive Output for Boost MOSFET. Connect the gate of a small high-voltage external FET to this pin to enable charging of the high-side boost capacitor connected between pins 20 and 22. This FET may be necessary to keep the boost capacitor charged at light loads.

20 XFRMRH Transformer Input. Transformer primary high-side connection.

21 DRVH Gate-Drive Output for High-Side MOSFET.

22 BST

Boost Input. Boost supply connection point for the high-side MOSFET driver. Connect at least a 1μF || 0.1μF ceramic capacitor from BST to XFRMRH with short and wide PC board traces. If the voltage across the boost capacitor falls below the high-side undervoltage lockout threshold, the DRVH output stops switching.

23 AVIN Supply Voltage Input. Connect AVIN directly to the input supply line.

24 GND Analog Signal Ground

25 UVLOUndervoltage Lockout Input. An external voltage-divider from the input supply sets the startup voltage; the threshold is 1.24V with 130mV hysteresis. UVLO can also be used as a shutdown input. If unused, connect UVLO to REG5

26 STARTUPStartup Input. STARTUP coordinates simultaneous startup of multiple units from faults, during initial turnon, and UVLO recovery. When paralleling the secondaries of two MAX5051’s, the STARTUP inputs of each device must be connected together.

27 FLTINT

Fault Integration Input. During persistent current-limit faults, a capacitor connected to FLTINT is charged with an internal 90µA current source. Switching is terminated when the voltage reaches 2.9V. An external resistor connected in parallel discharges the capacitor. Switching resumes when the voltage drops to 2V.

28 SYNCIN

Synchronization Input. SYNCIN accepts the synchronization signal from SYNCOUT of another MAX5051 and shifts the switching of the synchronized unit by 180° allowing the reduction of input bypass capacitors. The MAX5051 switches at the same frequency at SYNCIN. SYNCIN must be 50% duty cycle. Leave SYNCIN floating if unused.



Pin Description (continued)

MAX5051

CPWM

E/A

1

SSA

9VLDO

5VLDO

REG5 OK

80µA

REG9

REG5

BST

DRVH

XFRMRH

DRVL

PGND

LXVDD

LXHLXL

FLTINT

CS

AVIN

UVLO

STT

OSCRCOSC

RCFF

FB

COMP

CSS

CILIM

SYNCIN

SYNCOUT

STARTUP

50µA

GND

64µA

R

18R

1.25V1.125V

1.25V1.125V

DRVDD

PVIN

REG9 OK

CON

1.25V

OVERTEMP

SHDN

2.34V 156mV 10MHz

DS

R

Q

INTERNALREGULATOR

INTERNALSUPPLY

1.25VREFERENCE

THERMALSHUTDOWN

2.7V/1.8V

2.7V/1.8V

DRVB200ns

RISING-EDGEDELAY

DRVDD

SHDN

Q

300nsONE

SHOT

LEVELSHIFT

LEVELSHIFT

LEVELSHIFT

60nsRISING-EDGEDELAY

25µsRISING-EDGEDELAY

SHDN



Functional Diagram

Detailed DescriptionThe MAX5051 controller IC is designed for two-switch forward converter power-supply topologies. It incorpo-rates an advanced set of protection features that makes it uniquely suitable when high reliability and comprehen-sive fault protection are required, as in power supplies intended for telecommunication equipment. The device operates over a wide 11V to 76V supply range. By using the MAX5051 with a secondary-side synchronous rectifier circuit, a very efficient low output voltage and high output-current power supply can be designed.In a typical application, the AVIN pin is connected directly to the input supply. The PVIN pin is connected to the input supply through a bleed resistor. This is used to charge up a reservoir capacitor. When the voltage across this capac-itor reaches approximately 24V, then primary switching commences. If the tertiary winding is able to supply bias to the IC, then self boot-strapping takes place and opera-tion continues normally. If the voltage across the reser-voir capacitor connected to PVIN falls below 6.2V, then switching stops and the capacitor starts charging up again until the voltage across it reaches 24V.This device incorporates synchronization circuitry, enabling the direct paralleling of two devices for higher output power and lower input ripple current. Using a single pin, the circuitry synchronizes and shifts the phase of the second device by 180°. To enable simultaneous wakeup and shutdown, a STARTUP pin is provided. Connect all the STARTUP pins of all MAX5051 devices together to facilitate parallel operation in the primary side. When each power supply generates different output volt-ages, connecting the STARTUP pins is not necessary.

Power TopologyThe two-switch forward-converter topology offers out-standing robustness against faults and transformer satu-ration while allowing the use of SO-8 power MOSFETs with a voltage rating equal to only that of the input supply voltage.Voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle, similar to that of current-mode controlled topologies. This control method offers some significant benefits not possible with current-mode control. These benefits are:

No minimum duty-cycle requirement because of current-signal blanking;

Clean modulator ramp and higher amplitude for increased stability;

Stable operating current of the optocoupler LED and phototransistor for maximized control-loop bandwidth (in current-mode applications, the optocoupler bias point is output-load dependent);

Predictable loop dynamics simplifying the design of the control loop.

The two-switch power topology has the added benefit of recovering practically all magnetizing as well as the leak-age energy stored in the parasitics of the isolation trans-former. The lower clamped voltages on the primary power FETs allow for the use of low RDS(ON) devices. Figure 2 shows the schematic diagram of a 48V input 3.3V/10A output power supply built around the MAX5051.

MOSFET DriversThe MAX5051’s integrated high- and low-side MOSFET drivers source and sink up to 2A of peak currents, resulting in very low losses even when switching high gate charge MOSFETs. The high-side gate driver requires its own bypass capacitor connected between BST and XFRMRH. Use high-quality ceramic capacitors close to these two pins for bypass. Under normal operating conditions, the energy stored in the transformer parasitics swings the XFRMRH pin to ground while the transformer is resetting. During this time, the charge on the boost capacitor con-nected to the BST pin is replenished. However, under cer-tain conditions, such as when the magnetizing inductance of the transformer is very high or when using conventional rectification at the output, the duty cycle with light loads may become very small. Thus, the energy stored could be insufficient to swing XFRMRH to ground and replenish the boost capacitor. Figure 3 shows the equivalent circuit during the magnetizing inductance reset interval, assum-ing synchronous rectification where the output inductor is not allowed to run discontinuous.If the magnetizing inductance is kept below the follow-ing minimum, then the boost capacitor charge will not deplete:

2 INM 2

M total S

VL 0.294 df Qg (0.005A) f+

≤

where d is the duty cycle, VIN is the input voltage, fS is the switching frequency, and Qgtotal is the total gate charge for the high-side MOSFET. The above formula is only an approximation; the actual value will depend on other parasitics as well.



If the charge stored on the boost capacitor is not ade-quately replenished then the gate-driver lockout for the high-side MOSFET is triggered, stopping the high side from switching. The low side continues switching, even-tually recharging the capacitor, at which point the high side starts switching again. To prevent this behavior, use the boost capacitor’s cycle-by-cycle charging circuit to prevent unwanted shutdowns of the high side (Figure 2). Connect the gate of a small high-voltage FET (with the same voltage rating or higher as the main FETs) to the DRVB output of the MAX5051. Connect the drain of this FET to XFRMRH, and connect the source to the primary ground. DRVB will briefly (300ns) turn this FET ON every cycle after the main PWM clock terminates. This allows the boost capacitor to be replenished under all conditions, even when switching stops completely. A suitable FET for this is BSS123 or equivalent (100V, 170mA rated). The boost-capacitor charge diode is a high-voltage, small-sig-

Figure 2. Typical Application Circuit

Figure 3. Boost Capacitor Charging Path During Transformer Reset

MAX5051 T1

U2

CON

FLTINT

GND

RCFF

RCOSC

STARTUP

FB

BST

REG9

SYNC

IN

PVIN

AVIN

CSS

STT

DRVB

XFRMRH

DRVH

DRVDD

DRVL

PGNDCS

COMP

UVLO

REG5

SYNC

OUT

LXVD

D

LXH

LXL

VIN+

3.3V10A

B210

0

T1LM: 150µH

P: 14TS: 4TT: 6T

RLOAD

MAX8515

USED FORBOOST

CAPACITORPRECHARGE

PS2913

VIN-

fs = 250kHz

R121MΩ

C12220nF

C13100pF

C14390pF

R13100kΩ

R1424.9kΩ

R151MΩ

R1139.2kΩ

C104.7µF

C91µF

R1010Ω

R82.2kΩ

R7360Ω

C6270nF

R111.5kΩ

R22.55kΩ

C147nF

C2220nF

R3475Ω

C3150nF

C43 x 270µF

L12µHD5

D2B2100

D1

N1SI4486

N2SI4486

N3BSS123

R428mΩ

C51µF

C74.7µF

R510Ω

D3BAT46W

R647Ω

C84.7µF

D4MA111CT

R915kΩ

C110.1µF

VIN REG9

IBSTIBST

LM

IGD

ILM

DRVL

DRVH

XFMRH

BST



nal Schottky type. It may be helpful to connect a resistor in series with this diode to minimize noise as well as reduce the peak charging currents. As in any other switching powersupply circuit, the gate-drive loops must be kept to a minimum. Plan PC board layout with the critical current carrying loops of the circuit as a starting point.

Secondary-Side SynchronizationThe MAX5051 has additional (LXH and LXL) outputs to make the driving of secondary-side synchronous rectifiers possible with a signal from the primary. These signals lead in time, the actual gate drive applied to the main power FETs, and allow the secondary-side synchronous FETs to be commutated in advance of the power pulse. The synchronizing pulse is generated approximately 90ns ahead of the main pulse that drives the two power FETs.Synchronization is accomplished by connecting a small pulse transformer between LXH and LXL, along with some clamp diodes (D1 and D2 in Figure 4). This is a small integrated two-switch driver configuration that allows for full recovery of the stored energy in the magne-tizing inductance of the pulse transformer, thereby signifi-cantly reducing the running bias current of the controller. It also allows for correct transfer of DC levels without requir-ing series capacitors with large time constants, assuring correct drive levels for the secondary circuit.Select a pulse transformer, T1, so the current buildup in its magnetizing inductance is low enough not to create a significant voltage droop across the internal driver FETs. Use the following formula to calculate the approximate value of the primary magnetizing inductance of T1:

dsLXH dsLXLM

SS ds S

R R t2.5 Lf 16 C f+

≤ ≤

where RdsLXH and RdsLXL are the internal high- and lowside pulse transformer driver on-resistances, fs is the switching frequency, LM is the pulse transformer primary magnetizing inductance, ts is the transition time at the drains of these FETs (typically < 40ns), and Cds is the total drain-source capacitance (approximately 10pF).Alternatively, a high-speed optocoupler (Figure 5) can be used instead of the pulse transformer. The lookahead pulse accommodates the propagation delays of the high-speed optocoupler as well as the delays through the gate drivers of the secondary-side FETs. Choose optocouplers with propagation delays of less than 50ns.

Error Amplifier And Reference Soft-StartThe error amplifier in the MAX5051 has an uncommitted inverting input (FB) and output (COMP). Use this amplifier when secondary isolation is not required. COMP can then be directly connected to CON (the input of the PWM com-parator). The noninverting input of the error amplifier is connected to the soft-start generator and is also available externally at CSS. A capacitor connected to CSS is slewed linearly during initial startup with the 70μA internal current source (see Figure 2). This provides a linearly increasing reference to the noninverting input of the error amplifier forcing the output voltage also to slew proportionally. This method of soft-start is superior to other methods because the loop is always in control. Thus, the output-voltage slew

Figure 4. Secondary-Side Synchronous Rectifier Driver Using Pulse Transformer

Figure 5. Secondary-Side Synchronous Rectifier Driver Using High-Speed Optocoupler

MAX5051

T1LXH

REG5

LXVDD

LXL

PGND

R14.7Ω

C11µFD1

D2

D31N4148

R22kΩ

T1: PULSE ENGINEERING, PE-68386.D1, D2: CENTRAL SEMICONDUCTOR, CMOSH-3.

MAX5051

LXH

REG5

LXVDD

LXL

PGND

C11µF

R14.7Ω

R22kΩ

R3560W

PS9715HIGH-SPEED

OPTO

5V

C2

U2



rate is constant at light or heavy loads. Once the soft-start ends, the voltage on CSS regulates to 1.24V. Do not load CSS with external circuitry. A suitable range of capacitors connected to CSS is from 10nF to 0.1μF. Calculate the required soft-start capacitor based on the total output volt-age startup time as follows:

CCSS = 56μF/s × tSSwhere CCSS is the capacitor connected to CSS, tSS is the soft-start time required for the output voltage to rise from 0V to the rated output voltage. This only applies when this amplifier is used for output voltage regulation.

PWM RampThe PWM ramp is generated at RCFF. Connect a capaci-tor CRCFF from RCFF to ground and a resistor RRCFF from RCFF to AVIN. The ramp generated on RCFF is in-ternally offset by 2.3V and applied to the noninverting in-put of the PWM comparator. The slope of the ramp is part of the overall loop gain. The dynamic range of RCFF is 0 to 3V, and so the ramp peak must be kept below that. As-suming the maximum duty cycle approaches 50% at mini-mum input voltage, use the following formula to calculate the minimum value of either the ramp capacitor or resistor:

INR

UCF

VLF RCF

OS R

FPP

VR C2 f V

≥

where VINUVLO is the minimum input supply voltage (typi-cally the PWM UVLO turn-on voltage), fS is the switching frequency, and VRPP is the peak-to-peak ramp voltage, typically 2V.Allow the ramp peak to be as high as possible to maximize the signal-to-noise ratio. The low-frequency smallsignal gain of the power stage, Gps (the gain from the inverting input of the PWM comparator to the output) can be calcu-lated by using the following formula:

Gps = NspRRCFFCRCFF fswhere Nsp is the secondary-to-primary power transformer turns ratio.

Internal RegulatorsThe MAX5051 has two internal linear regulators that are used to power internal and external control circuits. The 9V regulator, REG9, is primarily used to power the highand low-side gate drivers. Bypass REG9 with a 4.7μF ceramic capacitor or any other high-quality capacitor; use

low-value ceramics in parallel as necessary. A 5V regu-lator also is provided, REG5, primarily used to bias the internal circuitry of the MAX5051. Bypass REG5 with a 4.7μF ceramic capacitor similar to the one used for REG9. Both of these regulators are always powered. When using bootstrapped startup through a bleed resistor, do not load these outputs while the MAX5051 is in standby as it may fail to start. Any external loading to this output should be such that the sum of their load and the standby current through PVIN of the MAX5051 is less than the current that the bleed resistor can supply.

Startup ModesThe MAX5051 can be configured for two different startup modes, allowing operation in either bootstrapped or direct power mode.

Direct Power ModeIn direct power mode, AVIN and PVIN are connected directly to the input supply. This is typical in 12V to 24V systems. The undervoltage lockout set at STT needs to be adjusted down with an external resistor-divider to an appropriate level.

Bootstrapped StartupIn bootstrap mode, a resistor is connected from the in-put supply to PVIN, where a capacitor to GND is charged towards the input supply. When this voltage reaches the startup threshold, the device wakes up and begins switch-ing. A tertiary winding from the transformer is then used to sustain operation. The MAX5051 draws little current from PVIN before reaching the threshold, which allows a large-value bootstrap resistor and reduces its power dissipation after startup. A large startup hysteresis helps the design of the bootstrap circuit by providing longer running times during startup.After coming out of standby and before initiating the soft-start, the MAX5051 turns on the low-side FET to charge up the boost capacitor. A voltage detector has been in-corporated in the high-side driver that prevents the high-side switch from turning on with insufficient voltage. It is also used to indicate when the boost capacitor has been charged. Once the capacitor is charged, soft-start com-mences. If the duty cycle is low, the magnetizing energy in the transformer may be insufficient to keep the bootstrap capacitor charged. DRVB (see Figure 2 dotted lines) has been provided to drive a small external FET connected between XFRMRH and PGND, and is pulsed every cycle to keep the capacitor charged.



Normally PVIN is derived from a tertiary winding of the transformer. However, at startup there is no energy de-livered through the transformer, hence, a special boot-strap sequence is required. Figure 6 shows the voltages on PVIN, REG9, and REG5 during startup. Initially, PVIN, REG9, and REG5 are 0V. After the input voltage is ap-plied, C21 (Figure 8) charges PVIN through the startup resistor, R22, to an intermediate voltage. At this point, the internal regulators begin charging C3 and C4. The MAX5051 uses only 400μA (typ) of the current supplied by R22, and the remaining current charges C21, C3, and C4. The charging of C4 and C3 stops when their voltages reach approximately 5V and 9V, respectively, while PVIN continues rising until it reaches the wakeup level of 24V. Once PVIN exceeds this wakeup level, switching of the external MOSFETs begins and energy is transferred to the secondary and tertiary outputs. When the voltage on the tertiary output builds to higher than 9V, startup has been accomplished and operation is sustained. However, if REG9 drops below 6.2V (typ) before startup is complete, the device goes back into standby. In this case, increase the value of C21 to store enough energy allowing for volt-age buildup at the tertiary winding.

Startup Time ConsiderationsThe PVIN bypass capacitor, C21, supplies current imme-diately after wakeup (see Figure 8). The size of C21 and the connection of the tertiary winding determine the num-ber of cycles available for startup. Large values of C21 increase the startup time and supply gate charge for more cycles during initial startup. If the value of C21 is too small, REG9 drops below 6.2V because the MOSFETs did not

have enough time to switch and build up sufficient voltage across the tertiary output to power the device. The device goes back into standby and will not attempt to restart until PVIN rises above 24V. Use a low-leakage capacitor for C21, C3, and C4 (see Figure 8). Generally, power sup-plies keep typical startup times to less than 500ms even in low-line conditions (36VDC for telecom applications). Size the startup resistor, R22 (Figure 8) to supply both the maximum startup bias of the device and the charging cur-rent for C21, C3, and C4.

Oscillator and SynchronizationThe MAX5051 oscillator is externally programmable through a resistor and capacitor connected to RCOSC. The PWM frequency will be 1/2 the frequency at RCOSC with a 50% duty cycle, and is available at SYNCOUT. The maximum duty cycle is limited to < 50% by a 60ns internal blanking circuit in the power drivers in addition to the gate and driver delays.Use the following formula to calculate the oscillator com-ponents:

S RCOSC PCBO

TH

RC SC1

REG5( ) InRE

R2 f C C

VG5

=

+ −

where CPCB is the stray capacitance on the PC board (about 14pF), REG5 = 5V, VTH is the RCOSC peak trip level, and fs is the switching frequency.The MAX5051 contains circuitry that allows it to be syn-chronized to an external clock whose duty cycle is 50%. For proper synchronization, the frequency of this clock should be 15% to 20% higher than half the RCOSC fre-quency of the MAX5051’s internal oscillator. This is be-cause the external source SYNCIN directly drives the power stage, whereas the internal clock is divided by two. The synchronization feature in the MAX5051 has been designed primarily for two devices connected to the same power source with a short physical distance between the two circuits. Under these circumstances, the SYNCOUT from one of the circuits can be connected to the SYNCIN of the other one; this forces the power cycle of the sec-ond unit to be 180° out-of-phase. To synchronize a second MAX5051, feed the SYNCOUT of the first device to the SYNCIN of the second device. If necessary, many devices can be daisy-chained in this manner. Each device will then have 180° phase difference from the device that drives it.Figure 5. Secondary-Side Synchronous Rectifier Driver Using

High-Speed Optocoupler

40ms/div

REG95V/div

PVIN10V/div

REG55V/div



Integrating Fault ProtectionThe integrating fault protection feature allows transient overcurrent conditions to be ignored for a programmable amount of time, giving the power supply time to behave like a current source to the load. This can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. The fault integration time can be programmed externally by connecting a suitably sized capacitor to the FLTINT pin. Under sustained overcurrent faults, the voltage across this capacitor is allowed to ramp up towards the FLTINT shutdown threshold (2.9V, typ). Once the threshold is reached, the power supply shuts down. A high-value bleed resistor connected in parallel with the FLTINT capacitor allows it to discharge towards the restart threshold (1.8V, typ). Once this threshold is reached, the supply restarts with a new soft-started cycle.Note that cycle-by-cycle current limiting is provided at all times by CS with a threshold of 154mV (typ). The fault integration circuit works by forcing a 90μA current out of FLTINT every time that the current-limit comparator (Figure 1, CILIM) is tripped. Use the following formula to calculate the value of the capacitor necessary for the desired shutdown time of this circuit.

FLTINFLTI

T SHNT

I tC

0.9V=

where IFLTINT = 90μA, tSH is the desired fault integration time after the first shutdown cycle during which current-limit events from the current-limit comparator are ignored. For example, a 0.1μF capacitor gives a fault integration time of 2.25ms.Some testing may be required to fine-tune the actual value of the capacitor. To calculate the required bleed resistance RFLTINT, use the following formula:

FLTINTFLTINT

RTtR0.9V C×

=

where tRT is the desired recovery time.Typically choose tRT = 10 x tSH. Typical values for tSH range from a few hundred microseconds to a few milli-seconds.

Synchronizing Primary-Side STARTUP For Parallel OperationFigure 7 shows the connection diagram of two or more MAX5051s for synchronized primary-side operation. The

common connection of STARTUP ensures all paralleled modules wakeup and shutdown in tandem. This helps prevent startup conflicts when the secondaries of the power supplies are paralleled. Connecting SYNCOUT to SYNCIN is not necessary; however, when used, this minimizes the ripple current though the input bypass capacitors.

Applications InformationIsolated Telecom Power SupplyFigure 8 shows a complete design of an isolated synchro-nously rectified power supply with a 36V to 72V telecom voltage range. This power supply is fully protected and can sustain a continuous short circuit at its output termi-nals. Figures 9 though 14 show some of the performance aspects of this power-supply design. This circuit is avail-able as a completely built and tested evaluation kit.

RCOSC

CON

RCFF

SYNCIN

UVLO

STARTUP

SYNCOUT FLTINT

RCOSC

CON

RCFF

SYNCIN

UVLO

STARTUP

SYNCOUT FLTINT

#1

#2

MAX5051

MAX5051

Figure 7. Connection for Synchronized STARTUP of Two or More MAX5051s



Figure 8. Schematic of a 48V Input 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply

REG5

R21

24.9k

Ω1%

C110

0pF

1RC

OSC

+VIN

TP1

R25

100kΩ

C239

0pF

3RC

FF

5CS

S

4CO

M

6CO

MP

7FB

8RE

G5

2SY

NCOU

T

C5 4700

pFD8

21

R15

31.6k

Ω1%

R16

10.5k

Ω1%

C44.7

µFRE

G5

REG5

9RE

G9

C34.7

µFRE

G9

10PV

IN

C60.1

µFPV

IN

11ST

T

12LX

VDD

13LX

H

C18

100p

F

R27

10Ω

C19

1µF

LXH

TP3

14LX

L

R3 2.2kΩ

R11

360Ω C1

70.3

3µF

C24

1000

pF

4 3

1 2

U2

R20

0Ω R19

475Ω R12

100kΩ

1%

C27

0.15µ

F

C36

0.22µ

FC2

80.0

47µF

R111

.5kΩ 1%

R2 2.55kΩ

1%V O

UT

R23

10Ω

TRIM

SENS

E (+

)SEN

SE (-

)

R24

10Ω

3 5214

OUT

INPG

ND GND

FB

U3

REG9

C26

0.1µF

C22

2200

pF2k

V

SYNC

IN28

GND

24

AVIN

23

BST

22

DRVH

21

XFRM

RH20

UVLO

25

FLTIN

T27

STAR

TUP

ON/O

FF26

R4 1MΩ

1%

R6 1MΩ

1%

C70.2

2µF

+VIN

+VIN

REG9

+VIN

R538

.3kΩ

1%

D1R7 0Ω

R8 8.2Ω

2C8 4.7

µF XFRM

RHDR

VB19

DRVD

D18

PGND

17

DRVL

16

CS15

IC_P

ADDL

E

DRVB

REG9

C9 1µF R1

415

0Ω

R9 8.2Ω

C20

220p

F

D3

12

6 5

41

2378 N2

R17

0.027Ω 1%

C21

4.7µF 80

V

R18

4.7Ω

PVIN

+VIN

R22

15kΩ

12

1 6D5

4T

R13

47Ω

C34

330p

F

2 58T

D71 2

3 21

4

56

6

78N3D4

1 23 2

14

578

N4R1

020Ω C23

1000

pF

8 102T

T1

L1 2.4µH

5V 5V5V

C29

0.1µF

3 2 1

1 2 3

4 5 6

6 5 4

N_OU

T

P_OU

T

V+

GND IN-

IN+

U4

U5

V+ P_OU

T

M_OU

T

IN+ IN-

GND

U7

C30

0.1µF

5VC3

10.1

µF5 4 3

1 2

VCC

OUT

GND

U1: M

AX50

51U2

: PS2

913-1

-MU3

: MAX

8515

U4, U

7: MA

X504

8AU5

: MAX

5023

MU6

: PS9

715

N1, N

2: SI

4486

N3, N

4: SI

4864

N5: B

SS12

3

AN CA

U6

LXH

R26

560Ω

R28

2kΩ

C13

270µ

F4V

C14

270µ

F4V

C15

270µ

F4V

C33

1µF

10V

V OUT

VOUT

SGND

5V

+VIN

C16

3.3µF

21

D6

C35

1µF

C32

1µF

1 2 3 4

8 7 6 5

INOU

T

WDI

N.C.

EN GND

RESE

THO

LD

21

D2N1

32 1

87 6

54

XFRM

RH

XFRM

RH

C10

0.47µ

F10

0V

C11

0.47µ

F10

0V

C12

1µF

100V

C25

0.07µ

F10

0V

-VIN

+VIN

N53 2

1

R29

1Ω

XFRM

RH

DRVB

MAX

5051

U1

REG5

V OUT

V OUT



Figure 9. Efficiency at Nominal Output Voltage vs. Load Current 48V Nominal Input Voltage

Figure 11. Turn-On Transient at Full Load (Resistive Load)

Figure 10. Power Dissipation at Nominal Output Voltage vs. Load Current for 48V Input Voltage.

Figure 12. Output Voltage Response to Step-Change in Load Current

60

65

75

70

85

90

80

95

0 4 62 8 10 12 14LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

RL = 0.22Ω

4ms/div

IOUT5A/div

VOUT1V/div

1

0

2

4

3

6

7

5

8

0 4 62 8 10 12 14LOAD CURRENT (A)

POW

ER D

ISSI

PATI

ON (W

)

VOUT100mV/div

50% > 75% > 50% OF IOUT(MAX), dl/dt = 5A/µs

IOUT5A/div

1ms/div



Figure 13. Output Voltage Ripple At Nominal Input Voltage and Full Load Current (Scope Bandwidth = 20MHz)

Figure 14. Load Current (10A/div) as a Function of Time When the Converter Attempts to Turn On into a 50mΩ Short Circuit

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTERN NO.

28 TSSOP U28E-4 21-0108 90-0146

VOUT50mV/div

2s/div

IOUT10A/div

IOUT10A/div

A: 1ms/divB: 20ms/div

A

B

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SYNCIN

FLTINT

STARTUP

UVLO

GND

AVIN

CS

BST

DRVH

XFRMRH

DRVB

DRVDD

PGND

DRVL

LXL

LXH

LXVDD

STT

PVIN

REG9

REG5

FB

COMP

CSS

CON

RCFF

SYNCOUT

RCOSC

TSSOP

TOP VIEW

EXPOSED PADDLE IS INTERNALLY CONNECTED TO GND.

MAX5051



Chip InformationTRANSISTOR COUNT: 2049PROCESS: BiCMOS/DMOSExposed Paddle Connected to GND

Pin Configuration

Package InformationFor the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

http://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF

http://pdfserv.maximintegrated.com/land_patterns/90-0146.PDF

http://www.maximintegrated.com/packages

REVISIONNUMBER

REVISION DATE DESCRIPTION PAGES

CHANGED

2 5/14 No /V OPNs; removed automotive reference from Applications section 1

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


© 2014 Maxim Integrated Products, Inc. 22

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

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