march new sumit tt

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March Test

Under Guidance of . . .

Presented B -Sumit Patel2011VLSI-14

31-March-2012


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1.Introduction 2. Formal Models

Memory Model Fault Model

3. Automatic Test Generation Methodology. Fault List Representation Test Pattern Generation


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1.Introduction

March Test : A march test consists of a finite sequence of march elements.

A march

element

is

a

finite

sequence

of

operations

applied

to

every

memory cell before proceeding to the next cell. It can be done in one of two address orders: an increasing address

order (e.g. from address 0 to address n l), or a decreasing address order ( ). When the address order is irrelevant the symbol m will be used.

An operation can consist of writing a 0 into a cell ( w ) , writing a 1 into

a cell (w1), reading a cell with expected value 0 (r0), and reading a cell with expected value 1 (r1).

For example march test, written as {m (w0); (r0,w1); (r1,w0)} It has the three march elements M0: m (w0), M1: (r0,w1) and M2: (r1,w0).

All operations of a march element are done before proceeding to the next address.


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March Test

Notation

Some basic march notations are r Memory action: A read operation w Memory action: A write operation r0 Memory action: Read a 0 from the memory location r1 Memory action: Read a 1 from the memory location w0 Memory action: Write a 0 to the memory location w1 Memory action: Write a 1 to the memory location Write a 1 to a cell containing 0 or the cell has a rising transition Write a 0 to a cell containing 1 or the cell has a falling transition Complement the cell contents Increasing memory addressing order

Decreasing memory addressing order mAddressing order can be either increasing or decreasing


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2 Formal Models 2.1 Memory Model

oriented memories only. Definition . An Ncell 1bit memory can be formally defined as

4upla:h A, N, M, X0 i

Where A={0, 1} is the set of possible states of a memory cell, N is the number of cells, = = , , , . . . ,

n , ,

X0 = { ri , wid | 0 i N1,d = A} is the set of possible memory operations. where ri means a read operation on the cell i, whereas wid

= th , .


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Memor model contd. The behavior of an Ncell 1bit memory can be formally represented by an Edge

Labeled Directed Graph (ELDG) G defined as

, , e ,

Where V is the set of 2N vertices representing the possible states of the memory, , , ,

possible memory operations that cause the transition from a vertex u to a vertex v, and

Le : E {labels} is is a label function that maps edges to labels, where given the edge (u,v), the corresponding label is defined as follows:Label = x/k,Where

x = X0 is memory operation able to fire the transition from u to v, and k={0,1, U} is the corresponding memory output, where the symbol U

denotes the unknown value at the memory data output signals when a write operation is per orme .


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Memor model contd.


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2.2 Fault Model

This model is used to represent the target memory functional faults. Faults are modeled starting from Faulty Behaviors (FBs), i.e., deviations of the memory behavior from the expected one. An FB is expressed using the following notation:

Di represents a faulty value D = {0,1} stored in the cell i. Rid represents an erroneous output D = {0,1} obtained while

reading the content of the cell i. This formalism is needed to represent classes of faults where a read operation returns an erroneous value, while the content of the memory cell is correct.

For example, 0 means that the it cell assumes an erroneous value 0, while Ri1 means that a read operation on cell i returns the value 1 even if the content of the cell is 0.


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Fault Model contd. Definition : A Functional Fault Primitive (FFP) represents the difference

between an expected (fault free) and the observed (faulty) memory behavior under a set of performed operations, denoted by

= ,

Where S

and

FB

represent

a

stimulus

and

a

faulty

behavior,

respectively.

. , the Inversion Coupling Fault (a transition performed on an aggressor cell a causes the inversion of the logic value stored in a victim cell v ) can be described b the followin two FFPs:


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Fault Model contd. Where a stimulus S is composed of an initial condition C of the f cells

(faulty cells), followed by an optional sequence of memory operations {op 1 , op 2 , . . . , op m}


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The march test generation methodology is based on the functional memory model and on the definition of functional faults in terms of FFPs. The main steps of the generation process are summarized as follows:

1. Fault list representation. Translate each FFP in the fault list into an operational representation of the faulty behavior, referred to as Addressed FFP, or AFFP .

2. Test pattern (TP) generation. Generate the set of TPs able to cover each AFFP. Each TP is represented by an additional edge on the ELDG modeling of the memory.

3. March test generation. Traverse the ELDG to generate the march test.


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3.1 Fault List Re resentation

The FFP formalism describes the conditions to sensitize and detect FBs by considering the f cells only. It does not consider the actual position of these cells in a generic Ncell memory.

To map an FFP into a generic Ncell memory model, we therefore introduce the concept of AFFP. formalized as

AFFP=h I, Es, Fv, Gv i , Where

I=(i0,i1,i2,.iN1)|i k= {0,1,}, 0 k N1 is the initial state of the memory. = = s m

sequence of m operations, performed on the aggressor cell, needed to sensitize the fault.


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3.1 Fault List Re resentation contd. Fv=(f 0,f 1,f 2,.f N1)|f k={0,1,}, 0 k N1 are the logical values (faulty

Gv=(g0,g1,g2,.gN1)|g k={0,1,}, 0 k N1 are the logical values (expected state) A sin le FFP ma enerate several AFFPs. For example, considering the Inversion Coupling fault FFPs defined

earlier applied to the two cell memory represented in Fig. 1 (N = 2, i=

address of the first cell, j = address of the second cell ), we obtain the


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3.2 Test Pattern Generation

From an AFFP, it is easy to define the sequence of memory operations, TP, used to detect the corresponding faulty behavior as

TP= h AFFP, O s i , where AFFP is the target AFFP, and Os ={rid} is the read and verify

operation performed on the victim cell, needed to observe the fault effect.


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3.2 Test Pattern Generation contd.

For example, the four AFFPs are covered by the following TPs in a two cell memory:


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Pattern Gra h Each TP can be represented by an additional directed edge (faulty edge)

from the state I to the state Gv on the memory model introduced. The faulty edge label is defined as Es , Os , where Es is the sequence of

sensitizing operations, and Os is the read and verify operation required to detect the fault.

The ELDG including the faulty edges is named Pattern Graph (PG) and is defined as

PG=hV,E F, Le Lf i ,


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Pattern Graph(contd.)


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3.3 March Test Generation Al orithm The PG(Pattern Graph) is used to generate a march test detecting the set

of faults described in the graph. Some additional definitions are required to understand test generation.

Definition : FEv is the set of faulty edges incident from the state v. FEv = .

to the state v.

Referring to the example in fig.3, we have four sets of faulty edges:FE00 = {w j1 r j, ri0 , ri, r j0 , w i1 , r j0 },FE01={},FE10={w j1 , ri1},

an

11= .


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March Test Generation Al orithm Contd.

Definition : FEiv is the set of faulty edges incident from state v, with an aggressor cell equal to i, 0 i N1 , FEiv = {TP|I=v, acell=i}. It represents the subset of TPs having the initialization state equal to state v and the aggressor cell address equal to i.FEi00 = { ri, r j0 , w i1 , r j0 },FE j00 = {w j1 r j, ri0 },FEi01={},FE j10={w j1 , ri1}, FE11={}.

Transition TP(test pattern): FEiv1 v2 is the set of faulty edges incident from the state v 1 and incident to the state v 2 , with an aggressor cell

, .


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Loop: if v1=v2 then FEiv1

v2

is called a loop TP(test pattern)

v . v i.e. for FE00 = {w j1 r j, ri0 , ri, r j0 , wi1 , r j0 },

$ FE00 = 3,an or FE00 = r , r 0 , w 1 , r 0 ,$ FEi00 =2 .


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FE i00 = { r i, r j0 , w i1 , r j 0 },

j = j j i

FE i10={},

10= w 1 , r 1 ,

FE i01=FE i01={},

FE 11={}.


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March Test Generation Al orithm Ste s Select initial state to start.

, .

In our example state 00 having high cost(3) than state 11 (1) choose a faulty edge with max cost.

for FEi00 = { ri, r j0 , w i1 , r j0 }, FEi00 =2 for FE j00 = {w j1 r j, ri0 }, $ FE j00 =1

Every time a faulty edge is traversed, the operations in its label are added to the ME.

also the read and verify operation needed to observe the fault is added if it is not already present .

Three rules can be derived for generating read operations:Rule 1. If read cell=sensitize cell: place read immediately after the write

o eration or when o eration is the last o eration of ME lace the read operation at the beginning of next ME.


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March Test Generation Algorithm Steps(Contd.)

Rule 2. if read cell < sensitize cell and AO is down( or read cell >

ME.Rule 3. in any other condition read is added as first operation of next ME.

e genera on en s no au y e ges can e se ec e rom e current state V, and ME closed.

Then each operation of ME is applied on the each cell of the memory s ar ng rom e n a s a e . If during this operation additional faulty edges are traversed, they are

marked as detected and removed from the graph.

At this point, we have reached the final state of the ME. The ME is completely defined, and if there are still faulty edges to traverse

the next ME is initialized, and the process is repeated .


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Exam le To better understand the generation algorithm, we will show its

application on the PG in Fig. 3. The initial selected state is V = 00, since #(FE 00)= 3 (00 is the state with

the highest number of faulty edges incident from it). We have to choose one faulty edge, so we calculate the cost of the different sets of faulty e ges:

FEi00 = { ri, r j0 , w i1 , r j0 }, $ FEi00 =2

for FE j00 = {w j1 r j, ri0 }, $ FE j00 =1. The algorithm chooses FEi00 and ri, r j0 is selected and added to the ME,

which becomes (ri0) with the current memory state still equal to 00. At this point, the algorithm chooses the only remaining choice in FEi

represented by w i1 , r j0 . wi1 (sensitizing sequence) is added to the ME, which becomes (ri0 wi1 ), while the observation is not required since it is already present.


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Exam le contd.

FE i00 = { r i, r j0 , w i1 , r j 0 },

j = j j i

FE i10={},

10= w 1 , r 1 ,

FE i01=FE i01={},

FE 11={}.


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Exam le contd. The new state is now v = 10. FE i10={ }, so the algorithm closes the ME

and generates the corresponding ME : (r0 w 1 ). It then simulates the operations of the ME on cell j. The simulation shows

that also w j 1 , r i1 (from state 10) is traversed. The read and verify operation performed on cell i is added to the next ME,

which becomes (r i1 ) again with up AO . The current state is now v =11. Since FE is em t the ME is closed and

the corresponding ME is generated: (r1 ). We now must change state to 00, which is the only state still having

fault ed es. The operation to move to 00 is w j 0 , it is added to the new ME, which

becomes (w j 0 ) with up AO. The ME is closed and the corres ondin enerated ME is w .


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Exam le contd. Now, the algorithm traverses the last faulty edge, and it adds the

operations on its label into a new ME, obtaining an ME equal to (w j1 r j1 ), with down AO.

It also inserts the read and verify operation, obtaining an ME equal to(r j0 w j1 r j1 ) .

, , , generated ME is (r j0 w j1 r j1 ) .

The algorithm ends, and the final generated march test is j j j 0 0 1 1 0 .


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O timizations March tests are critical components in any ATEbased or BIST Memory test

architecture. It has been shown that the BIST hardware overhead can be reduced if the

march test shows some particular characteristics such as uniformity (a constant number of operations in each ME), symmetry (particularly important on transparent march tests), or single AO.

Additional constraints can be very easily added in the generation phase performed by traversing the ELDG.

The only drawback is that adding too many constraints may lead to situations where no solutions can be generated.


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We have seen all the basics of March Test. Models used for March Test Generation.

The flexibility of the fault model formalism allows describing not only traditional static and dynamic faults but also linked and user defined faults.

Working of March Test generation algorithm. With respect to previously presented approaches, proposed

computation time, without exhaustive searches.


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Reference A. Benso A. Bosio S. Di Carlo G. Di Natale and P. Prinetto

March Test Generation Revealed , IEEE Transactions On Computers, VOL. 57, NO. 12,pp. 1704 1713 Dec2008.


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Thank you

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