mapld 2005/254c. papachristou 1 reconfigurable and evolvable hardware fabric chris papachristou,...

MAPLD 2005/254C. Papachristou 1

Reconfigurable and Evolvable Hardware Fabric

Chris Papachristou, Frank Wolff Robert Ewing

Electrical Engineering & Computer Science AFRL/AFTA, Bldg 620

Case Western Reserve University Wright Patterson

Cleveland, Ohio 44106 WPAFB, OH 45433

September 7, 2005


A novel reconfigurable processor for high data rate agile communications

Features- Reconfigurability & adaptability,

- Low power, system-on-chip technology,- Real time, robust performance,

- Fault tolerance, - Self-healing.

Platform: autonomous sensor or unit being a typical node in space

Project Overview


Concept: The Big Picture


Background

Ability of a device to change its internal structure, functionality, and behavior, either on command, or autonomously.

Reconfigurability Classes

Static Configuration: performed while device is off line.

Dynamic Configuration: device is on-line, "on the fly".

Self Reconfiguration: performed autonomously by device.

Evolution type: Self Reconfiguration with adaptation such as replication and growth, "bio-inspired". ...

Reconfigurability


Technology Assessment

Advantages over competing FPGA and DSP processors:

Flexibility: ability for self-reconfiguration

Granularity: ability to scale for variable bit-length operations

Cost: simpler upgrading of protocols, algorithms, code schemes

Fault Tolerance: ability for self repair and self healing from SEUs

Low Power: efficient energy consumption through configuration


Enhancements to Space Technology

Communication Requirements in Missions

• Rapid adaptation of onboard systems to changing environments

• Dynamic communications links: - self adaptable bandwidth to meet changing throughput requirements - self managing channel capacity

• Passive communication to reduce power

• Communication Protocol adaptation: - adapt to changing communication protocols for each situation

Reconfigurable Hardware: enabling technology to meet these requirements.


Sensor Web Scenario

Comm Tradeoffs Bandwidth = Buffer/Latency

Data Rate, Protocol, ErrorBit Rate.


Approach

Architecture: reconfigurable at four Layers:

Layer 4: the Adaptation Manager.

Layer 3: the Real-Time Operating System RTOS.

Layer 2: the Embedded Processors and Memory.

Layer 1: the Reconfigurable Hardware Fabric.


Architecture: Non Traditional Reconfigurable


Occurs at several levels:

(a) Selection of application modules by the Adaptation Manager.

(b) Mapping of modules into the hardware fabric or the embedded processors, depending on performance requirements.

(c) Configuration of the hardware fabric and the embedded processor to meet performance and data delivery requirements.

The reconfigurable hardware is essential for mapping of wireless communications algorithms such as : IR filtering, multichannel CDMA, complex encoding, advanced imaging.

Reconfiguration Strategy


Self Adaptation - Dynamic Configuration


Reconfigurable Fabric


Reconfigurable Tile


Core Switch Matrix


Double Buffer Configuration Switch Cell


is capable of on-line adaptation by autonomously reconfiguring its architecture either through software or by directly morphing the hardware.

The key idea is to achieve evolution in the hardware by evolving configuration candidates via a neural network and testing them for fitness.

A best fit configuration will morph the hardware to best responding to a particular input stimulus.

Evolvable Hardware


Evolvable Platform


Operation mode: NN generates configuration code

Training mode: NN incrementally evolves configurations by training itself on input stimuli as well as configuration data that are recurrently applied after being improved by genetic operations.

Other evolution modes e.g. self-diagnosis and self repair are also feasible.

Evolution modes:


During training, candidate configurations are selected from a population via genetic operations.

Training continues until a candidate passes a fitness test depending on responses from the hardware fabric.

Training may start on command or autonomously, in new environment, new functions or upgrading for better performance.

A major aspect of this scheme is to design a robust training mechanism for configuration evolution of the dynamic hardware fabric.

Training


Evolvable Hardware Training


Configuration Tools

Binding Configurator

Algorithm Data Flow

Arch Resource Netlist

Connectivity Bindings

Architecture Mapper Synthesis tools


Configuration Tools (Cont.)

Synthesis: Data Flow transormation of the application into a resource graph.

Binding: allocation of resources into configurable modules, This involves functional, local memories and interconnect modules.

Configuration Core: compact description of the mapping -- in space and time

Loading the configuration matrix into Buffere FIFOs to employ the mapping.


Results on Some Benches

Application AllocatedMemories

OperatorUnits

Size of 2 CoreMatrices

Deq 5 5 (10X10) and (5X5)

Bandpass Filter 9 9 (18X18) and (9X9)

Cosine Filter 11 11 (22X22) and (11X11)

Elliptical Filter 8 8 (16X16) and (8X8)

Arfilter 9 9 (18X18) and (9X9)

Wave Filter 6 6 (12X12) and (6X6)

DCT 12 12 (24X24) and (12X12)


Proof of Concept

For proof of concept, we will employ advanced FPGA boards from Xilinx and Altera, as well as CAD tools that we have obtained from commercial vendors.

We will develop an advanced prototyping environment based on these tools and software.

We will implement by emulation our proposed reconfigurable hardware on these boards, without actual chip design. Emulation and prototyping is quite feasible.

mapld 2005/254c. papachristou 1 reconfigurable and evolvable hardware fabric chris papachristou,...

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