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Silicon ImagingSI-3300 MegaCamera

3.2 Million Pixel Progressive Scan Digital Camera

Revision 1.0July 8, 2004

3.2 Million Pixels 2048 x 1536 Image Sensor3.2 um Square Pixel½ Optical formatRolling ShutterSubsampling & Binning20~80Mhz Clock rates (-H version)10 Bit Digital SamplingAuto Black Level Correction62.9dB Dynamic RangeCL High-Speed Interface

Silicon Imaging , Inc. 2004 of 40 Company Confidential

**** Company Confidential ****MegaCamera™ SI-3300M & RGB3.2 Megapixel, 10-Bit, 40/80MHz Progressive Scan Digital Camera

Silicon Imaging Inc.

INTRODUCTION

Silicon Imaging is proud to continue its innovation in high-resolution color vision camera. Driven by the growing demand for consumer Digital Still Cameras, CMOS sensors are continuing to break technical barriers and surpass the performance characteristics of CCD’s in many photonic, imaging and consumer applications. By utilizing a single highly integrated CMOS device, which incorporates Megapixel sensing areas, timing generation, Analog-to-digital Conversion and signal processing, Silicon Imaging has developed a very compact, low-power, ultra high speed Megapixel digital camera system.

2048 x 1536 Megapixel - Ultra Resolution The SI-3300 is an all-digital ½” format CMOS camera that delivers 3.2 Million pixels of resolution and is capable of running at over 12 frames/second at its full 2048 x 1536 resolution. The entire package is only 45 x 52 x 50mm (33 x 40mm x 22mm in PCB) and is small enough to placed on a robot for semiconductor machine vision inspection or placed in an outdoor housing for remote surveillance. It is ideal for live visualization and handheld instrumentation.

10-Bits Sampling – Sub-Pixel AccuracyThe SI-3300 MegaCamera uses 10-Bit digitizers to sample the pixel data. Converting the pixel data directly to digital at the sensor head eliminates pixel-sampling jitter and enables accurate sub-pixel metrology, image analysis and improved live video reconstruction. A programmable clock which ranges from 20~40Mhz or up to 80MHz with -H version, allows for trade-offs in speed versus exposure time and lower noise. Subsampling with Binning – Video PreviewIdeal for high speed preview and focusing, the SI-3300 is capable of generating imagery at over 30 frames per second by reducing the size of the readout image in color subsampling mode, This entire imager is readout by binning 4x4 groups of pixels into 2x2 bayer super pixels with increased sensitivity, less aliasing and faster readout rates. The camera also supports up to 3x binning and 8x subsampling.

1000FPS Windowing and 720/1080P HD ModesA small region of the imager can be readout at frame rates in excess of 1000fps, with speed increasing with reduced vertical and horizontal settings. At 1920 x 1080 and a 75MHz clock the output rate would be 30fps or 1280x720 at 73MHz will be 60fps. The window size and position can be adaptively changed on frame-by-frame basis.

Automatic Black Level Correction The SI-3300 has automatic black level calibration, which measures the average value pixels from two dark rows of the imager for each of the four colors. The pixels are averaged as if they were light sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames and compared to minimum and maximum acceptable thresholds for automatic correction.

CameraLink Digital Interfaces (12-Bit 1-Tap)An industry standard forum has adopted Camera Link, for low cost connectivity and cabling of cameras and frame grabbers at very high speeds. The SI-3300-CL utilizes the high speed CameraLink interface to output data continuously to a frame grabber and directly into PC memory for further processing. The single cable includes image data, synch,

FEATURES

· 2048 x 1536 Resolution (3.2 Million Pixels)

· 1/2” Imaging Format , 5.2um Square Pixel

· Rolling Shutter, Progressive scan

· 640 x 480 VGA Windowing at 120fps

· 10 Bits per Pixel, 48MHz Sampling (Nominal)

· 20 ~ 80MHz Programmable Clock (– H Version)

· Programmable Gain, Exposure & Clocks

· Auto Black Level Calibration

· Monochrome & Color Bayer RGB Model

· Custom PCB Version

· Cameralink Interface


Triggering and 9600 baud Serial communication. As this camera complies with the standard, it is compatible with many popular frame grabber and image processing hardware devices and GigaBit Ethernet or fiber-optic repeaters for extended distance transmission.

· C-Mount Precision Machined Housing

SI-3300 MegaCamera CameraLink Specifications

Sensor: Optical Imaging Format 1/2” (6.55mm x 4.91mm, 8.19mm diagonal)Active Pixels 2,048H x 1,536VPixel Size (pitch) 3.2 µm x 3.2 µm Pixel Type CMOS Aspect Ratio 1 : 1Spectral Response 350 ~ 1000 nm (Bayer Color Filtered)Responsivity > 1.0 V/lux-sec (550nm)Temporal Noise TBDSaturation Charge TBDDynamic range 61dBSNR max 43dBWindowing (ROI) Horizontal & Vertical speed increaseSub-sampling Full, 1/2, 1/3, 1/4, 1/8Binning 2x (4x4 to 2x2 / 4:1) & 3x (6x6 to 2x2 / 9:1)Gain MAX 8x Analog, 18x with DigitalReadout Method Progressive ScanBlack Level Auto Black Level CalibrationShutter Rolling Shutter with Global Reset optionShutter Speed / Integration Variable, approx. 50usec ~ 50sec Horizontal Blanking 390 Clocks/line Minimum Row Time 647 clocks (257 + 390 blanking)Vertical Blanking 4 RowsRow/Frame Time (default) 2438 clocks/row x 1540/rows @ 40MHz

A/D Conversion & Sampling Clock SynthesizerA/D Conversion Nominal 40Mhz (12fps @ 3.2MP)Readout Rate 20 ~ 80Mhz x 12bit formatA/D Resolution 10 Bit (CL Format = 12bit Single-Tap)Pixel Clock Frequency 20 ~ 40 Mhz Programmable

20 ~ 80Mhz (-H option)

Digital Video Output Interface Cameralink Base, Single-tap, 12bitReadout Format CL - 12 Bit Base

Duplicated data on Ports A, BEffective Data Rate 20~ 80MB/sec (8-bit, using MSB)

40~160MB/sec (12-bit Unpacked)Frame Rate

2048 x 15361600 x 12001920 x 1080

1280 x 720640 x 480320 x 240128 x 128

40MHz1117163380

243296

75MHz20313062150456555

Row/Frame Time (default) 1524 clocks/row x 1050/rows = 30fps

CameraLink Frame Grabber Control: Serial Communication RS-232 Protocol 9600bps (57.6k)Serial Signaling TX & RX (LVDS)Triggers LVDS – CC1 (-CL)

TTL Trigger-In / Strobe-Out (option)Region-of–Interest Programmable Horiz & VerticalProgrammable Modes Exposure, Gain, Windowing, Clock

Rates, Auto black, trigger.Gains (R,G,B,G & Global) Individual RGBG Gains

Range: 18X, Min step size 0.125Setting Timing Next top of FrameExt Clock Sync Clock in or Clock Out (-X Option)

PowerInput Voltage +5 VDC +/- 10%Power 2.5 WattsPower/Trigger Connection Tajimi RO3-PB3M 3Pin (-CL)

Tajimi RO3-PB5M 5Pin (-X)

MechanicalLens Mount C-Mount, 7mm Back focus Adj.Enclosure Size 45mm W x 52mm H x 50mm LWeight 12 oz.Camera Mount ¼” x 20 standard tripod mount Cable Connector Cameralink MDR-26

Mechanical Dimensions

ORDERING INFORMATION

SI-3300-[RGB or M]-S 3.2 MP Digital Camera, 2M Cable, PCI Frame Grabber & Win NT/2K/XP Imaging Software SystemSI-3300-[RGB or M]-CL 3.2 MP Digital Camera (RGB for Color, M for Monochrome) Cameralink (-CL) -X - H High-Speed CL 80MHz (–H), Add external clock sync (-X)FG-1300-xx Frame Grabber PCI (32 = 32Bit PCI -64 = 64bit PCI)CL-2M, 3M, 5M, 10M 2 / 3 / 5 / 10 Meter Digital Cameralink CablePC-3 Power Cable (3M)PCT-3 Power supply & External TTL trigger (3MPS-5 5VDC Power supply


SI-3300 Camera Architecture OverviewThe MegaCamera SI-3300 consists of 6 major component sections, which are built on two circuit boards.

Camera Block Diagram

1.) 3.2 Megapixel Sensor2.) Digital Clock Synthesizer3.) Digital Control Logic4.) Microprocessor5.) CL Interface6.) Power Regulation 7.) Trigger & Strobe Controls

1.) 3.2 Megapixel CMOS Image Sensor (2048 x 1536)The MegaCamera SI-3300 utilizes a proprietary 3.2 Million pixel high-speed CMOS image sensor. Each pixel is 5.2um Square, ideal for image processing, and the entire array fits the 1/2” format for flexible optic choices. This reduction in process geometry allows for both an increase in transistors and fill factor without compromising performance, plus offers more advanced readout controls, greater speeds and lower power dissipation.

This new sensor technology offers a more responsive pixel design with added circuitry for increased dynamic range, greater sensitivity, decreased fixed pattern noise and low dark current for long exposure applications. Unlike CCD, which leak charge to adjacent pixels when the registers overflows (blooms), the SI-3300 provides inherent anti-blooming protection in each pixel, so that there is no blooming.


The array has 2048 pixels on a line and 1536 rows, which result in a 4:3 aspect ratio. The sensor array design is based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme (aka. Rolling Shutter Method)

Analog Gain Amplifier & OffsetThe imager signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. The gain settings can be independently adjusted for the colors Green1, Blue, Red, and Green2 and are programmed through registers. A total programmable gain of 18x is available. The programmable analog offset stage corrects for analog offset that might be present in the analog signal. The analog offset settings can be independently adjusted for each color (R/G1/G2/B).

Automatic Black Level CompensationThe automatic black level calibration measures the average value of 256 pixels from two dark rows of the imager for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered average is compared to minimum and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased. If it is above the maximum level, the level is decreased. The upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting (out of all four colors), according to Register settings. This prevents clipping of the black level. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers.

2.) 10-Bit Digital Sampling System A 10-Bit Analog-to-digital (A/D) converter samples each pixel value and quantizes it into 1024 levels inside the sensor. Pixel clock sampling ensures precise measurement of the photonic charge without the jitter and sampling uncertainty associated with traditional analog video systems, such as RS-170 and CCIR. This produces images which can deliver improved photometry accuracy and sub-pixel metrology. The use of 10-bit converters versus traditional 8-bit systems further enhances the image dynamic range. The combination of 10-bit vertical resolution and pixel clock sampling provide precise sub-pixel measurement accuracy (ex. 1/10 pixel).


3.) Digital Clock Synthesizer A wide range a master clock frequencies (eg. 20 to 80MHz) can by precisely generated using the Digital Clock Synthesizer. The Frame Grabber, which is used with the camera, must be capable of receiving 12bit at 40Mhz for standard cameras or up to 80Mhz for the High-Speed (-H) model to achieve the highest data rates. Without any byte packing of the 12-bit word the data rate would be 160MHz (2pixel x 2bytes/pixel x 80MHz). In standard 32Bit/33MHz PCI computers the maximum data rate directly to host memory is usually below 120Mbytes/sec (from 132MB/sec bus) without system interrupts. However, 100MB/sec is more reasonable rate to achieve with other system devices operating (eg. display, clock, mouse etc.). Under these condition the 12-bit data can be mapped to 8-bits/pixel to reduce the bus traffic or the clock rate can be reduced to and still maintain 12bits/pixel. The frequency of the clock synthesizer can be set by serial command. A table with associated clock frequency is found in the serial programming section of the manual. Due to minimum frequency restriction on the digital transmission link, the pixel clock frequency cannot be lower than 20Mhz.

4.) Embedded MicroprocessorA microprocessor in the camera provides the control interface between the PC and the functional block in the camera (Sensor, Clock Synthesizer, Register Memory, Channel Link Interface & Serial port (CameraLink). The Microprocessor receives commands thru the LVDS level serial port and issues commands to the other devices. It also can store preset values for camera setting, which can be recalled with single ASCII character commands. Several digital I/O or analog sampling signals are available on the processor from PCB header points for custom OEM applications.

5.) 12-Bit CameraLink Interface (Base Configuration)

Camera Link is a new digital transmission method designed by imaging component manufacturers as an easy and standard way to connect digital cameras to frame grabbers. The Camera Link specification includes greater than 1.2Gb/sec data transmission as well as camera control and asynchronous serial communications all on a single cable with high-density 26pin connector. Only two connections are required to quickly interface your digital camera to a multitude of frame grabbers. This standardization will ultimately reduce cost of high performance digital cameras through open market competition and a simple migration path to faster and higher resolution systems.

As a standard that has been defined by industry members, Camera Link provides the following benefits:

Standard Interface: Every Camera Link product will use the same cable and signaling. Cameras and frame grabbers can easily be interchanged using the same cable.

Simple Connection: Only two connections will be required to interface a camera and frame grabber: Power and Camera Link.

Lower Cost: Because Camera Link is an industry-wide standard, consumers will be able to take advantage of lower cable prices.

Smaller connectors & cables: The technology used in Camera Link reduces the number of wires required to transmit data over traditional LVDS or RS-422 parallel interfaces, allowing for smaller cables. Smaller cables are more robust and less prone to breakage.

Higher data rates: The technology used in Camera Link has a maximum data rate of 2.3GB/s, for use in the most demanding high definition, high frame rate and line scan.

CameraLink Camera Signal


This section provides definitions for the signals used in the Camera Link interface. The standard Camera Link cable uses a MDR 26-pin connector (3M Part# 10226-6212VC)provides the following signaling:

Video Data (4 Pairs using 28:4 Mux, 24 Video, 4 Control)

Camera control signals (1 Pair)

Serial communication (2 Pairs)

Video DataThe 24 bit image data (2 words x 12 bit) and 4 control bits are transmitted over only 4 differential pairs using a 28:4 multiplexer (National Semiconductor DS90CR285 Channel Link device). The Four enable signals are defined as:

• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.

• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.

• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.

• Spare— A spare has been defined for future use.

All four enables are provided on the camera, via the Channel Link chip. The unused data bits are tied to a known value by the camera. For more information on image data bit allocations, see page 11, CameraLink Base Configuration Bit Assignment Configuration.

Communication

Two LVDS pairs have been allocated for asynchronous serial communication to and from the camera and frame grabber. Cameras and frame grabbers should support at least 9600 baud. These signals are

• SerTFG—Differential pair with serial communications to the frame grabber.• SerTC—Differential pair with serial communications to the camera.

The serial interface operates at 9600 baud, one start bit, one stop bit, no parity, and no handshaking. For applications requiring high serial throughput, such as real time windowing update at over 200FPS, the camera can support a serial link mode at 57kbs (not specified in CameraLink spec). The frame grabber serial communication must be set to match this speed.


Camera Control Signals & Power

Four LVDS pairs are reserved for general-purpose camera control. They are defined as camera inputs and frame grabber outputs. Camera manufacturers can define these signals to meet their needs for a particular product. The signals are:

• Camera Control 1 (CC1) - Used to do triggered image capture

• Camera Control 2 (CC2) for external master clock (optional)

Tajimi RO3-PB3M – POWER CABLE

5VDC Power Supplies


3-PIN POWER & TRIGGER INPUT WIRING

PhotoEye Trigger and Power Connection


Power-On Communication & PresetsInitial State When the power is first applied to the camera the camera will load its default (Preset #0) settings and will be generating live video and a serial status message. Preset #1 can be overwritten thru programming commands. Once Preset#1 is overwritten it will be the new power-on default setting.

If the Frame Grabber supports a serial terminal mode the following menu will appear:

100: Booted 108: CameraLink SI3300 3.12.08 120:C2010610 Sensor tag 190:66633035 Configuration code

's' - statusReturns the firmware version, clock configuration word, Sensor Tag, and FPGA Configuration code. Camera output example:

108: CameraLink SI3300 3.06.08 110:306882 Clock 120:C2010610 Sensor tag 190:66633035 Configuration code

Default SettingsWhen first turned on, the SI-3300 will be in the default mode, which will be 10 fps Full Frame Readout at 40MHz master clock. See serial programming section for details on changing formats.

Full Resolution, Rolling Shutter, Single-slope, 40MHz

Resolution = 2048 x 1536Clock = 40MHzIntegration = 1561 RowsGlobal Gain = 2.0Frame Rate = 11 FPS


Serial Communication & Protocol

The SI-3300 is capable of mode programming through its serial interface. Commands are sent from the CameraLink frame grabber to the camera. The commands are processed by the micro controller and communicated to various devices in the camera including the sensor, digital clock synthesizer and the Flash memory inside the microprocessor itself.

The communication uses an asynchronous serial format, similar to RS232, but is transferred to the camera using LVDS as part of the CameraLink interface specification.

Format: Asynchronous, ASCII Rate: 9600Data Bits: 8 + 2 Stop bitsParity: No ParityInterface: Serial LVDS (thru CameraLink)

The baud rate is set to 9600 and 8 data bits with no parity. This is the format set by the CameraLink standard. However, faster rates can be set by the factory and coordination with the Frame Grabber supplier.

Serial CommandsThere are two types of commands Single character and Register String (multiple characters followed by Carriage Return). Once the camera receives the string ending with a <CR> it will respond. For each command, there is a corresponding action and response from the camera.

Single Character commands

“s” Camera status including firmware version, clock configuration word, sensor tag and CPLD configuration codes.

“f” Arm single frame capture. Trigger frame capture & readout if already armed.

“c” Continuous Live Rolling Shutter Operation. Return tpo ERS after arming with an ‘f’

“g” Enter Genlock Mode. Use “c” to return to continuous (supported by -H model)

“h” Change to high-speed serial mode for operation at 57.6kbaud

*** Note: All commands must terminate with a <cr> (carriage return).

Register String commands

Each command may be entered through the Terminal communication mode from the frame grabber software. All ASCII characters sent should be lower case and no spaces between characters. The string is terminated with a carriage return <cr>. Hex numbers are sent as ASCII characters: 0Fh is sent as “0F” character. There are no spaces

between characters being sent in strings. These are multiple character string commands with a common format.


Register String Commands

Command Description Parameters Responselc xxxxxx <cr> Load Clock Register

(See clock table)xxxxxx = 6 hex values from table 114: Clock updated

ly rr xxx <cr> Load Sensor Registers Loads registers 00 to ff with 16bit values, which are sent as 4 ascii characters representing hex.

rr = register number 00~ff xxx = x0000~xFFFF

104: Sensor updated

le x <cr> Load EEPROM preset value ***overwrites factory values

x = 1 le1 = stores preset #1

106: Preset updated

ld x <cr> Load Bootup Default x = 0 or 1 ld1 = boots camera with preset #1

'luAA[YYXXx16]' Load upper/user memory7k-Bytes. Configured in 256 slots. Each slot has 16 memory locations of14bits for

AA = slot (00 ~FFYY = Memory (00-10)XX = 14 bit value (00~ FThe first two bits (MSBs) of the first byte and of every odd byte are not stored.

lr xxxx Read back user/upper memory

ln xxxx Load new firmware xxxx = password to enable firmware upgrade (contact factory)

*** Note: All commands must terminate with a <cr> (carriage return). Hex characters are lower case, no spaces.

Load Sensor Command Format

The following registers for SI-3300 control the sensor readout, timing and signal output levels. These are programmed thorough ‘ly’ register commands. The register number is represented by 2 characters. All sensor registers are 16 bits in length and are represented by 4 characters. The ASCII command format is:

ly rr xxxx <cr> rr = register number xxxx = values 0000 to ffff

The ly stands for load sensor array and must be sent as lower case. The “rr” is the register to be changed. The “xxxx”, “represents four HEX values that are to be loaded into each register. The sequence must end with a carriage return <cr>.

The following is an example of a 10-character command string

l y 0 1 0 0 6 4 <cr>

This command will load the WIDTH register “01” with hex “0064”. The resulting value loaded into the Width register is “0064” or 101 in decimal. The actual resulting width in the image is width-, which equals 100.


SI-3300 Sensor Register ProgrammingRegister Name Default Description

0x00 Chip Version 0x1601 or 11 Chip ID Response

0x01 Row Start 0x0014(20)

First row to be read out + 20. (Bits 10~0)Note: Register value must be an even number.

0x02 Column Start 0x0020(32)

First column to be read out + 32. (Bits 11~0)Note: Register value must be an even number. If column bin is enabled, the value must be a multiple of Reg0x23 [5-4] + 1.

0x03 Height 0x05FF(1535)

Number of rows – 1. Min = 0x0001. (Bits 10~0)Note: Register value must be an odd number.

0x04 Width 0x07FF(2047)

Number of columns – 1. Min = 0x0001. (Bits 10~0)Note: Register value must be an odd number.

0x05 Horizontal Blanking 0x0015(21)

Number of extra blanking clocks in row. Min = x0015 (21). (Bits 10~0)Horizontal Blanking = 390 clocks + (Regx05 - 21)

0x06 Vertical Blanking 0x0003 (3)

Number of rows + 1 in vertical blanking. Min = x0003 (3). (Bits 10~0)Typically used to slow down frame rate and allow time for register updates between images.

0x08 Long Exposure 0x000(0)

The MSB of Exposure Reg0x09. (Bits 15~0)Long Exposure = (Reg8 x 65536) + Reg9

0x09 Exposure Time 0x0619 (1561)

Number of rows of integration (exposure time). Min = x0001 (Bits 15~0)Exposure = Row_Time x Reg0x09. Row_Time = Width + 390 + Reg0x05Min_Row_Time = 647 clocks (even if width Reg05 is set smaller)

0x0C Shutter Delay(Short Exposure)

0x0000 (0)

Number of master clocks times four that the sensor waits before asserting the reset for a given row. Used for Sub-row exposure times

0x1E SnapshotMode

0x80408 Snapshot Mode—default is 0 (continuous mode).1 = enable snaphsot.

This register bit is automatically controlled by ‘f’ command.9 Strobe Enable = 110 Strobe Width: 0 = one row, 1 = all rows of integration11 1=Strobe Override, set high, 0 for low

0x21 Global Reset or ERS Readout Mode

0x0000(0)

Set to x0003 for Global Reset Snaphsot mode - Release all pixels from reset simultaneously (use with flash & mechanical shutter. x000: for ERS.Note: global reset requires model SI3300–T with external trigger cable.

0x22 Row Subsampling Skip & Bin

0x0000(0)

Subsampling Skip onlyReg 22 & 23

Skip + BinReg 22 & 23

None x0000 x00002x x0001 x00113x x0002 x00224x x0003 x00238x x0007 x0027

Load register x22 and x23 to get subsampling in both rows & columns.

0x23 Column Subsampling Skip & Bin

0x0000(0)

0x2B Green1 Gain 0x0008 (8)1x gain.

Gain Increments Settings1.000 to 4.000 0.125 0x0008 to 0x0020 4.25 to 8.00 0.25 0x0051 to 0x0060 9.0 to 18.0 1.0 0x0160 to 0x7860

Bits 6~0 : Analog Gain = (Bit[6] + 1) x Bit[5-0] x 0.125) Bits 14~8: Digital Gain = 1 + Bit[14-8] / 8 Total Gain = Analog x Digital Gain

0x2C Blue Gain 0x0008 (8)1x gain.

0x2D Red Gain 0x0008 (8) 1x gain.

0x2E Green2 Gain 0x0008 (8) 1x gain.

0x35 Global Gain 0x0008 (8)1x gain.

This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B.

0x49 Black Level Target 0x00A8Target Black Level (Bits 15~0). Digital offset will be applied such that the average black level of a frame in a resulting image equals the value of this register. This adjustment happens after black level calibration.

0x62 Auto Black Level Control X0000 0 0= Auto Black Calc, 1= Use Manual Black Levels (x60, x61, x63, x64)1 0 = Enable Correction, 1 = Disable Correction Voltage

0x60, 0x610x63, 0x64

Manual Black OffsetsGreen1, Green2, Red, Blue 0x0020

Two's compliment representation of analog offset correction value.Bit[8] =1 causes the analog offset correction to be negative. Bit[7-0] = valueGreen1 (x60), Green2 (x61), Red (x63), Blue (x64)

0x5D Auto Black Coarse Thresholds

0x2D13

6-0 Low Coarse Threshold. Max =less than High Target Threshold.14-8 High Coarse Threshold. Min = greater than Low Target Threshold.If the average black value for a color is higher than this value or lower than Low Coarse Threshold, the coarse mode will be activated (if enabled).Once the black level is in range the fine method will be used.

0x5F Auto Black Fine Thresholds

0x231D6-0 Thresh_lo: default = 29 Lower threshold for black level in ADC LSBs14-8 Thresh_hi: default = 35. Upper threshold for black level in ADC LSB. When the black value is within these thresholds, it is considered on target.


Digital Clock Synthesizer ProgrammingThe SI-3300 has a Digital Clock Synthesizer capable of generating a range of frequencies from 20MHz to 40 or up 80Mhz with –H version. The pixel data output rate is the same as the sampling clock rate. The clock frequency is set by the “lc” Register String command. A range of sample frequencies are listed below:

Command Clock RateMHz SI-3300 Frame Rate

MHz 2048 x 1536 1600 x1200 1920x1080 1280x720 640 x480 320 x240 128 x128lc306886 20 5 8 8 17 40 122 148lc30b689 25 7 10 10 21 50 152 185lc37cb8f 30 8 13 12 25 60 182 222lc35d40b 35 9 15 14 29 70 213 259lc306882 40 11 17 16 33 80 243 296lc35e709 45 12 19 18 37 90 274 333lc36a20f 48 13 20 19 40 96 292 355lc34b689 50 13 21 20 41 100 304 370lc34b688 55 15 23 22 45 110 334 407lc36cb8f 60 16 25 24 50 120 365 444lc367307 65 17 27 26 54 130 395 481lc36ee0f 70 19 29 28 58 140 426 518lc36f88f 73 19 30 29 60 147 446 542lc34ae05 75 20 31 30 62 150 456 555

Note: The factory can generate the command to achieve a targeted clock rate.

Sample Command:

The clock frequency is programmed by the “lc” command with by 6 HEX characters. An example is:

“lc36cb8f <cr>” This will request a clock value of 60MHz.

The response to a command will be:

114: Clock updated

Frame Rate Calculation

There is a minimum of 390 clocks of Horizontal Blanking (Reg x05 = 21) and of 4 rows of Vertical Blanking (Reg x06 = 3). To calculate the frame rate for any clock rate the equation is estimated by:

( clock rate(Hz) ) = # Frames Per Second (fps)

( # of columns + 390) * ( # of rows +4)

Example: What is the frame rate, at 45MHz clock rate for an image size of 2048 x 1536?

40 x 10 6 = 11 Frames Per Second (fps) ( 2048 + 390) * (1536 +4)

** Subsampling frame rates are based on the resulting size of the sub-sampled image or window.


*** Minimum # of columns that are internally clocked is 257, even if the image window is smaller. Therefore the minimum row time = 257 + 390 blanking = 647 clocks.Frame Timing RegistersRegister Name Default Description



0x04 Width 0x07FF(2047)


0x05 Horizontal Blanking 0x008E(142)

Number of extra blanking clocks in row. Min = x0015(21). (Bits 10~0)Horizontal Blanking = 390 clocks + (Regx05 - 21)

0x06 Vertical Blanking 0x0019 (25)

Number of rows + 1 in vertical blanking. Min = x0003 (3). (Bits 10~0)Typically used to slow down frame rate and allow time for register updates between images.

Frame Timing

Note: Typically, the value of Expsoure (Reg0x09) is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the


total number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as needed, and thereby reduce the effective frame rates.Exposure Time (Regx08, x09, x0c)

The exposure time is set by adjusting the number of row times in the exposure register (Reg09) and up to the number of rows in the frame. For long exposures, Reg08 will count in increments of 65536 rows. The user can also program sub-row integration time for fine exposure control using Regx0C.

Register Name Default Description

0x09 Exposure Rows 0x0619 (1561)

Number of rows of integration (exposure time). Min = x0001 (Bits 15~0)Exposure = Row_Time x Reg0x09. Row_Time = Width + 390 + Reg0x05Min_Row_Time = 647 clocks

0x08 Long Exposure 0x000(0)

The MSB of Exposure Reg0x09. (Bits 15~0)Long Exposure = (Reg8 x 65536) + Reg9

0x0C Shutter Delay(Short Exposure)

0x0000 (0)

Number of master clocks times four that the sensor waits before asserting the reset for a given row. Used for Sub-row exposure times

The exposure is estimated by:

Row_Time = [Width + 390 ] * Clock_RateExposure_Time = Exposure_Rows (Reg09) * Row_Time

Reg04 sets the image width. The minimum blanking period is 390 clocks and can be extended by setting Reg05. The exposure is set in number of row times. The minimum # of columns that are internally clocked is 257, even if the image width is smaller. Therefore, the minimum row time = 257 + 390 = 647 clocks.

Typically, the value of Reg0x09 (Exposure Rows) is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as needed, and thereby reduce the effective frame rates.

Example: What is the row_time and exposure time at 48MHz clock rate for an image size of 2048 width and no additional horizontal blanking?

Row_Time = 2048 + 390 / 48MHz Exposure_Time = 2438 * 20.8 nsec = 59.4 usec/row

1/ 60 sec = 280 rows * 59.4 usec/row = 16.7 msec (Reg09 = x0118) 1/ 120 sec = 140 rows * 59.4 usec/row = 8.3 msec (Reg09 = x008c) 1/ 240 sec = 70 rows * 59.4 usec/row = 4.1 msec (Reg09 = x0046)

The following table shows a sample set of values for Reg9 and the exposure time at clock rates 20MHz and 40MHz:

Width Row_count(Width+390)

Row_Time@ 20MHz(50ns)

Row_Time@40MHz(25ns)

Reg09(Exposure Rows)

Exposure Time20MHz

Exposure Time40MHz

2048 2438 122 us 61 usec x0089 (137) 16.7ms 1/60 8.3ms 1/1202048 2438 122 us 61 usec x00a4 (164) 20 ms 1/50 10.0ms 1/1002048 2438 122 us 61 usec x0112 (274) 33 ms 1/30 16.7ms 1/602048 2438 122 us 61 usec x0224 (548) 66 ms 1/15 33.0ms 1/302048 2438 122 us 61 usec x066c (1644)* 200ms 1/5 100 ms 1/102048 2438 122 us 61 usec X2004 (8196)* 1 sec 0.5 sec


* Note: These high row exposure counts will extend the frame time, slowing down the effective max frame rate. At a 1 second exposure, the maximum frame rate is 1 frame/sec. For even longer exposure, use Reg08.

The full formula for calculating the pixel integration time is:

T_INT = ((65536 x Reg0x08 + Reg0x09) * Row_Clocks - P1 + 132 - Reg0x0C) * Clock_rate

Row_Clocks = Width + P1 +P2 +P3 P1 = Frame Start Blanking #1 (Row Binning)

331 if Reg0x22[5-4] = 0, normal 673 if Reg0x22[5-4] = 1, Bin 2x

999 if Reg0x22[5-4] = 2, Bin 3x P2 = Frame Start Blanking #2 (Column Binning)

38 if Reg0x23[5-4] = 0, normal 22 if Reg0x23[5-4] = 1, Bin 2x 14 if Reg0x23[5-4] = 2, Bin 3x

P3 = Horizontal_Blanking set by Reg0x05 (min value = 21)Note: P1 + P2 + P3 = 331 + 38 + 21 = 390 for min values and no binning

Flickerless Operation

While the user can adjust the integration time to the desired value according to the aforementioned formula, not all integration times may be desired under certain lighting conditions. If the light source has a flicker component, then the integration time needs to be set properly to avoid banding in the image. Under 60Hz flicker, the integration time must be a multiple of 1/120 of a second to avoid flicker. Under 50Hz flicker, the integration time must be a multiple of 1/100 of a second to avoid flicker.

Short Exposure ( Less than 1 Row Time)

To set the SI-3300 to an integration time less than 1 row, the shutter width register 0x09 must first be set to 1. Shorter integration times are controlled by the Shutter Delay register 0x0C.

T_INT = (Reg0x09 * Row_Clocks) - P1 + 132 - Reg0x0C * Clock_rate

For an image width of 2048, no binning, Reg9 set to 1, the sub-row short exposure time is calculated as follows:

T_INT = (1 * Row_Clocks) – P1 + 132 - Reg0C Row_Clocks = width + P1 +P2 +P3

= Width + 390 P1 = 331 (673 = Bin2x, 999, Bin 3x) Reg0C = 21 (minimum value)

T_INT = Row_Clocks – 331 + 132 – Reg0x0C * clock_rate= (Width + 390) – 199 – Reg0x0C * clock_rate= Width + 191 – Reg0x0C * clock_rate

Width(Reg4 + 1)

Row_cntr(Width + 191)

Reg09(1 Row)

Reg0C(short exposure)

Exposure ClocksRow_Cntr - Reg0c

Exposure_Time20MHz (50ns)

Exposure_Time40MHz (25ns)

2048 2239 x0001 x085b (2139) 100 5.0 usec 2.5 usec2048 2239 x0001 x07f7 (2039) 200 10 usec 5.0 usec


2048 2239 x0001 x06cb (1739) 500 25 usec 12.5 usec2048 2239 x0001 x04d7 (1239) 1000 50 usec 25 usec

Window Programming – Image Size & PositionRegister Name Default Description

0x01 Row Start 0x0014(20)

First row to be read out + 20. (Bits 10~0)Note: Register value must be an even number.

0x02 Column Start 0x0020(32)

First column to be read out + 32. (Bits 11~0)Note: Register value must be an even number. If column bin is enabled, the value must be a multiple of Reg0x23 [5-4] + 1.



0x04 Width 0x07FF(2047)


The minimum value for Reg0x03 is 0x0001; for Reg0x04, 0x0001. Thus, the smallest window size is two columns by two rows (2H x 2V). The value of Reg0x03 and Reg0x04 must be an odd number (there can only be even number of columns).

The user can program the window size to be any format desired. To place a 1280 x 1024 window at a start position of 640, 480, use the following commands:

ly 04 xxxx Set WIDTH to (1280 - 1) = 1279 (0x04ff) ly 03 xxxx Set HEIGHT to (1024 -1) = 1023 (0x03ff) ly 02 xxxx Set COLUMN_START to 640+32=672(0x02a0) ly 01 xxxx Set ROW_START to 480+20=500 (0x01f4)

As shown in the adjacent picture, Registers 4 and 3 set the size of the display window. Register 2 sets the column start location and registers 1 set the row start location.

Note: Other custom commands can be used to move the window at high speeds – please consult the factory.

The following table shows examples of register settings to achieve various resolutions and frame rates based on a nominal 48MHz clock rate.

For tables above, the settings for Reg0x05 (horizontal blanking) and Reg0x06 (vertical blanking) are 21 and


15 respectively, while all of the registers are set to default.

Subsampling Skip & Bin ModesRow and column skip modes use subsampling to reduce the output resolution without reducing field-of- view. The SI-3300 also has row and column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes. This is achieved by the averaging of two or three adjacent rows and columns (adjacent same-color pixels). Both 2x and 3x binning modes are supported. Rows and columns can be binned independently.

Skip/Bin ResolutionRow Skiply22 00xx

Column Skiply23 00xx

Row Skip + Bin ly22 00xx

Column Skip + Binly23 00xx

None 2048 x 1536 00 00 00 002x 1024 x 768 01 01 11 113x 682 x 512 02 02 22 224x 512 x 384 03 03 23 238x 256 x 192 07 07 27 27

The following table shows examples of register settings to achieve various resolutions and frame rates based on a nominal 48MHz clock rate, such as 1920x1440 with a 3x bin & skip to achieve a 640x480 output at 48fps:

Bin 2-to-1: 2,048H x 1,536V (QXGA) to 1,024H x 768V (XGA)

NOTE:Grs = binning of 4 Gr[s] in a 4 x 4 window; Gbs = binning of 4 Gb[s] in a 4 x 4 window.Rs = binning of 4 R[s] in a 4 x 4 window; Bs = binning of 4 B[s] in a 4 x 4 window.


Bin 3-to-1: 2,048H x 1,536V (QXGA) to 640H x 480V (VGA)

NOTE:Grs = binning of 9 Gr[s] in a 6 x 6 window; Gbs = binning of 9 Gb[s] in a 6 x 6 window.Rs = binning of 9 R[s] in a 6 x 6 window; Bs = binning of 9 B[s] in a 6 x 6 window.

Column Skip 2x; Row Skip 2x Enabled



GAIN CONTROL (Registers: 2B, 2C, 2D, 2E, 35)The SI-3300 contains manual Analog and Digital gain controls for each color channel (G1, G2, R, B). Analog Gain values may be set using the following registers: G1 = 0x2B [6..0], G2 = 0x2E [6..0], R = 0x2D [6..0], and B = 0x2C [6..0]. In addition, the SI3300 contains a global gain register, 0x35 [6..0], that applies the gain value to all gain channels (G1, G2, R ,B ). Digital Gains are set using Bits{14~8] of each of the registers. The total gain = analog gain x digital gain. When the global gain register (Reg35) is read, it returns only the gain setting from the Green 1 channel register 0x2B.

0x2B Green1 Gain 0x0008 (8)1x gain.

Gain Increments Settings : 1.000 to 4.000 0.125 0x0008 to 0x0020 4.25 to 8.00 0.25 0x0051 to 0x0060 9.0 to 18.0 1.0 0x0160 to 0x7860

Bits 6~0 : Analog Gain = (Bit[6] + 1) x Bit[5-0] x 0.125) Bits 14~8: Digital Gain = 1 + Bit[14-8] / 8 Total Gain = Analog x Digital Gain

0x2C Blue Gain 0x0008 (8)1x gain.

0x2D Red Gain 0x0008 (8) 1x gain.

0x2E Green2 Gain 0x0008 (8) 1x gain.

0x35 Global Gain 0x0008 (8)1x gain.

This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B.


The table below shows recommended gain register settings and corresponding gain values:

Register Setting (0x2B, 0x2C, 0x2D, 0x2E, 0x35) Gain

Register Setting (0x2B, 0x2C, 0x2D, 0x2E, 0x35) Gain

Decimal Hex Gain Gain [dB] Decimal Hex Gain Gain [dB]8 0x08 1 0 32 0x20 4 12.09 0x09 1.125 1.0 81 0x51 4.25 12.610 0x0A 1.25 1.9 82 0x52 4.5 13.111 0x0B 1.375 2.8 83 0x53 4.75 13.512 0x0C 1.5 3.5 84 0x54 5 14.013 0X0D 1.625 4.2 85 0x55 5.25 14.414 0x0E 1.75 4.9 86 0x56 5.5 14.815 0x0F 1.875 5.5 87 0x57 5.75 15.216 0x10 2 6.0 88 0x58 6 15.617 0x11 2.125 6.5 89 0x59 6.25 15.918 0x12 2.25 7.0 90 0x5A 6.5 16.319 0x13 2.375 7.5 91 0x5B 6.75 16.620 0x14 2.5 8.0 92 0x5C 7 16.921 0x15 2.625 8.4 93 0x5D 7.25 17.222 0x16 2.75 8.8 94 0x5E 7.5 17.523 0x17 2.875 9.2 95 0x5F 7.75 17.824 0x18 3 9.5 96 0x60 8 18.125 0x19 3.125 9.9 352 0x160 9 19.126 0x1A 3.25 10.2 353 0x161 10 20.027 0x1B 3.375 10.6 354 0x162 11 20.828 0x1C 3.5 10.9 355 0x163 12 21.629 0x1D 3.625 11.2 356 0x164 13 22.330 0x1E 3.75 11.5 357 0x165 14 22.931 0x1F 3.875 11.8 358 0x166 15 23.5


Signal Path & Black Level Controls

The SI-3300 analog signal path consists of the pixel array, the column sample and hold (S/H) circuitry, the programmable gain stage, the analog offset correction and the analog-to-digital converter (ADC). The reset and signal voltages from the pixel are sampled onto the column sample and hold circuitry on a row-wise basis. After signal sampling is complete, the differential signal (reset-signal) is transferred to the programmable gain stage.

After the gain stage, the differential signal goes through the analog offset correction circuitry. The user can decide if a positive or negative offset or no offset needs to be added to the differential signal. The signal is then sampled onto the sample and hold circuitry of the ADC before being digitized.

Register Name Default Description

0x62 Auto Black Level Control X0000 0 0= Auto Black Calc, 1= Use Manual Black Levels (x60, x61, x63, x64)1 0 = Enable Correction, 1 = Disable Correction Voltage

0x60, 0x610x63, 0x64

Manual Black OffsetsGreen1, Green2, Red, Blue 0x0020

Two's compliment representation of analog offset correction value.Bit[8] =1 causes the analog offset correction to be negative. Bit[7-0] = valueGreen1 (x60), Green2 (x61), Red (x63), Blue (x64)

0x5D Auto Black Coarse Thresholds 0x2D13

6-0 Low Coarse Threshold. Max =less than High Target Threshold.

14-8 High Coarse Threshold. Min = greater than Low Target Threshold.If the average black value for a color is higher than this value or lower than Low Coarse Threshold, the coarse mode will be activated (if enabled).Once the black level is in range the fine method will be used.

0x5F Auto Black Fine Thresholds

0x231D

6-0 Thresh_lo: default = 29 Lower threshold for black level in ADC LSBs

14-8 Thresh_hi: default = 35. Upper threshold for black level in ADC LSB. When the black value is within these thresholds, it is considered on target.

0x49 Black Level Target 0x00A8Target Black Level (Bits 15~0). Digital offset will be applied such that the average black level of a frame in a resulting image equals the value of this register. This adjustment happens after black level calibration.

Auto Black Level Thresholds (Registers: 0x5D & 0x5F)

The digitized black level of the camera will potentially vary with temperature or gain setting changes. The SI-3300 allows the user the flexibility of automatic black level calibration or manual black level control. In automatic mode, the black level will be adjusted to be within the high and low thresholds set in Reg5D and 5F. The final black level digital output can be further adjusted by Reg49.


Auto Black Level Calibration (Registers: 0x62)

The automatic black level calibration measures the average value of 256 pixels from two dark rows of the imager for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered average is compared to minimum and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased. If it is above the maximum level, the level is decreased. The upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting (out of all four colors), according to Register settings. This prevents clipping of the black level. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers.

Manual Black Level (Registers: 0x60, 0x61,0x63 & 0x64)

The programmable analog offset stage corrects for analog offset that might be present in the analog signal. The user would need to program Reg0x62 to enable the manual analog offset correction. The analog offset settings can be independently adjusted for the colors of Green1, Green2, Red and Blue and are programmed through Reg0x60, Reg0x61, Reg0x63 and Reg0x64 respectively.

Bit[8] of Reg0x60, Reg0x61, Reg0x63 and Reg0x64 determines the sign of the analog offset(these registers have two’s complement representation). Bit[8] = 1 makes the analog correction negative instead of positive.

The lower 8 bits (Bit[7–0]) determine the absolute value of the analog offset to be corrected and Bit[8] determines the sign of the correction. When Bit[8] is “1”, the sign of the correction is negative and vice versa. The analog value of the correction relative to the analog gain stage can be determined from the following formula:

Analog offset = Bit[8–0] x 1 LSB

Note that the 1 LSB value in the formula is an estimate amount. It will deviate from 1 LSB with process variation.

Black Level Digital Control (Register: 0x49)

Digital offset will be applied such that the average black level of a frame in a resulting image equals the value of this register. This adjustment happens after black level calibration.


READOUT MODES

There are three operating modes for the SI-3300 cameras: Continuous, Frame Snapshot and Genlock modes. Each has its own characteristics shown below

“c” Continuous Electronic Rolling Shutter Operation. Return to ERS after an “f” or “g”

“f” Arm single frame capture. Trigger frame capture & readout if already armed.In Frame snapshop there are 2 methods of Readout Rolling Shutter Readout - Reg21 = x0000 Global Reset Readout - Reg21 = x0003 (-T Model)

“g” Enter Genlock Mode. Use “c” to return to continuous (supported by -H model)

Continuous, Electronic Rolling Shutter (ERS) – “c” ModeContinuous, rolling shutter mode is the default mode of operation of the camera. The exposure is determined by the delay between two scans of the pixel array and controlled with the shutter width registers, Reg0x08 and Reg0x09. The shutter width is measured in row times. The first scan (shutter) resets each row of pixels in turn, starting the exposure. The second scan (read) stops the exposure by transferring the accumulated charge from each row of pixels to sample/hold capacitors at the foot of the columns and reads the (digitized) values out. When each scan reaches the bottom of the array there follows a blanking period (controlled by the user) after which the scan automatically restarts at the top of the array. Read out is therefore continuous.

Frame Snapshot Mode, with ERS – “f” Mode with ERSThe snapshot mode allows capture of a single frame initiated by an external trigger using CC-1, TTL-Trigger (-T option) or software command (‘f <cr>)’, with the capability of controlling a flash using the Strobe_Out signal. Each of the rows in the shutter will be reset, as shown in Figure. Just as for continuous mode the exposure is determined by the delay between the scans. However, before the start of the frame, the sensor waits for a trigger before starting the scan. The first (shutter) scan does not start until a rising edge on the TRIGGER signal is seen. The second scan then follows after the shutter width delay. After the end of the frame, the sensor waits for another trigger before restarting the scan. The maximum snapshot rate is limited to half the continuous readout rate. Note that the exposure (shutter width) is still determined electronically.

To return to Continuous ERS Readout mode, send a ‘c’ command.


Frame Snapshot Mode with Global Reset - “f” mode (with Reg21 = x0003) - T Model

0x21 Global Reset or ERS Readout Mode

0x0000 (ERS)or

0x0003 (GR)

Set to x0003 for Global Reset Snaphsot mode - Release all pixels from reset simultaneously (use with flash & mechanical shutter. x0000: for ERS.Default Mode is conitunous ERSNote: Global reset requires model SI3300–T with external trigger cable.

A further enhancement to the snapshot capability is a global reset mode that enables all pixels to start exposure to the scene simultaneously. Global reset mode is selected by Reg0x21 to x0003 (x0000 is Rolling Shutter).

Global reset mode has to operate with a mechanical shutter to terminate the exposure time or with a strobe with minimum ambient light. Using the global reset feature changes the behavior of the row reset controls. Instead of pulsing, the resets are held on. As the shutter pointer moves through the rows the resets are turned on one by one. When all of the rows have been reset, the exposure is started by releasing them all together. Exposure is terminated when an external mechanical shutter cuts off the light. Row read out is performed after the exposure is terminated. The strobe can be used to control flash and/or a mechanical shutter to end the exposure of the array prior to readout.

To enter Snaphshot mode with global Reset:

ly210003 <cr> Global Reset Mode f <cr> Frame Snapshot Mode

The snapshot is initiated with the CC-1 Trigger, TTL-Trigger (-T option) signal or “f’ frame request command, as in ERS snapshot mode. The array is reset row by row before the sensor waits for the trigger. All of the rows are held in reset until a rising edge is detected on the TRIGGER input, whereupon they are all released at once. At this point every row in the array starts to integrate at the same time. Integration is terminated and the readout started when the internal shutter counter is equal to the shutter width register ([Reg0x08, Reg0x09]). The first active row is read out after the preamble (5 rows), the calibration rows (18 rows) and the dark rows (24 rows), allowing 47 row times for the mechanical shutter to be closed. (Default values).

To return to Continuous ERS, set Reg21 to ERS Readout (x0000) and a “c’

ly210000 <cr> Rolling Shutter Mode c <cr> Continuous Readout


Genlock Mode for Stereo Capture – ‘g’ command (-H Model)

For stereo and synchronized multi-camera applications the SI-3300-H models supports a Genlock feature.

In normal Frame Snapshot mode, an image can be captured for two cameras simultaneously by triggering the cameras at the same time. However, this method limits the maximum frame rate to half speed as the exposure and readout do not overlap and require two frame times per image captured. The first frame time is for Reset and begin exposure. The second frame time for Readout and completion of exposure. The Genlock mode provides the highest frame rate synchronization possible by allowing overlapping exposure and readout, just like continuous ERS, while being synchronized to a triggering timebase.

Sending a ‘g’ command arms the camera for Genlock Mode. Each CC-1 trigger causes the camera to initiate a frame readout. The camera is left in an armed state, continuing exposure and can be re-triggered at anytime. New CC-1 triggers can occur immediately after the completion of the current frame readout cycle. Note: The first frame is improperly exposed and should not be used.

The exposure time should be set to the full frame time for consistent exposures throughout the image. However, variable exposure times can be used if the Genlock trigger rate matches the normal Frame_Time set by image height and Vertical Blanking.

The mode is exited by sending a ‘c’ command.


Response Codes

000:XXXX Sensor Chip ID. This is sent at boot time, and also when the status command is issued.

0XX:XXXXXX... Sensor registers. This message gives the address and contents of a chip register. 16 bytes of register data will be sent on each line.

100: Booted This is the first string sent when the Camera boots. It will later be augmented with a firmware version number.

102: Default loaded A message sent a boot time after the sensor and clock have been programmed.

104: Sensor updated A response that follows the "ly..." command.

106: Preset updated A response that follows the "le..." command.

108: CameraLink SI-3300 2.12.30

Output by the ‘s’ status command. Identifies the camera model, interface and firmware version

110: XXXXXX Clock Output by the ‘s’ status command. It gives the current clock setting.

114: Clock updated A response that follows the "lc..." command.

120: XXXX Sensor Tag Output by the ‘s’ status command. It provides the factory serial number.

152: serial to 57.6kbaud Response to an ‘h’ command

159: serial rate fault A serial framing error occurred in high-speed serial mode. Camera will return to default 9600 baud.

190: XXXX Configuration Code

Output by the ‘s’ status command. It gives the current configuration.

501: Unrecognized Command

The first character of the command line input is unrecognized.

503: Invalid Input There are multiple forms of the 503 message code. They represent invalid input other then the command specifier, such as "ly..." commands which include to many characters of input, or not enough to fill the specified data byte count.

505: busy Further input was given while the camera was still processing the previous input

601: Loaded preset #1 A response to “1” command. Preset #1 was loaded.


605: help menu All of the lines of the help menu begin with code 605.

702: Single frame This message is sent after the camera enters single frame mode, and again after each frame is sent.

703: Leave single frame This message is sent after the camera exits single frame mode and enters continuous frame mode.

Binary to Hex (ASCII) TableBinary Hex in ASCII0000 00001 10010 20011 30100 40101 50110 60111 71000 81001 91010 a1011 b1100 c1101 d1110 e1111 f


SI-3300CameraLink Frame Grabber

Hardware Interface Notes

1. Data Configuration – 12bits x Single-TapThe 12bit data is duplicated on both A & B outputs, to simplify Frame Grabber testing and integration.

2. LVDS Serial InterfaceThe standard data rate is 9600 baud. (Faster rates, up to 57kbps can be programmed).

3. CC-1 Trigger InterfaceThe camera is armed for capture modes via serial command. The CC-1 trigger is used to start the snap exposure or live video output.

4. PCI BandwidthThe camera can operate at 80 Million Pixels per second. In 8-bit mode, this equates to 80MB/sec a sustained data rate. In 12-bit mode, where 2 bytes per pixel are typically used, the maximum rate is 160MB/sec and may require the use of a 66MHz PCI system. The data rate can be adjusted thru the on-board clock synthesizer.


CameraLink ConnectionMegaCamera to Frame Grabber Interface

SIGNAL NAME PAIR26-PIN

CONNECTORFROM

CAMERA

26-PIN CONNECTOR

FRAME GRABBER

X0- 1- 2 25X0+ 1+ 15 12X1- 2- 3 24X1+ 2+ 16 11X2- 3- 4 23X2+ 3+ 17 10X3- 5- 6 21X3+ 5+ 19 8

Xclk- 4- 5 22Xclk+ 4+ 18 9

SerTC- 6- 20 7SertTC+ 6+ 7 20SerTFG- 7- 8 19SerTFG+ 7+ 21 6

CC1- 8- 9 18CC1+ 8+ 22 5CC2- 9- 23 4CC2+ 9+ 10 17CC3- 10- 11 16CC3+ 10+ 24 3CC4- 11- 25 2CC4+ 11+ 12 15Gnd Gnd 1 1Gnd Gnd 13 13Gnd Gnd 14 14Gnd Gnd 26 26

MDR-26 ConnectorThe camera uses the standard 3M MDR-26 connector specified in CameraLink specifications.


12-Bit CameraLinkBase Configuration Bit Assignment

CameraLinkPort Assignements

PORT/BIT 12-bit x 2ChBit

NameA0 A0 DO-0A1 A1 DO-1A2 A2 DO-2A3 A3 DO-3A4 A4 DO-4A5 A5 DO-5A6 A6 DO-6A7 A7 DO-7B0 A8 DO-8B1 A9 DO-9B2 A10 DO-10B3 A11 DO-11B4 B8 DE-8B5 B9 DE-9B6 B10 DE-10B7 B11 DE-11C0 B0 DE-0C1 B1 DE-1C2 B2 DE-2C3 B3 DE-3C4 B4 DE-4C5 B5 DE-5C6 B6 DE-6C7 B7 DE-7

DE = Even Pixels DO = Odd PixelsThe ODD and EVEN Outputs are identical on the SI-3300.

NationalDS90CR285MTD

SignalName

Camera Data Bit

Channel LinkPin

RX-00 DO-00 27RX-01 DO-01 29RX-02 DO-02 30RX-03 DO-03 32RX-04 DO-04 33RX-05 DO-07 34RX-06 DO-05 35RX-07 DO-08 37RX-08 DO-09 38RX-09 DO-10 39RX-10 DE-10 41RX-11 DE-11 42RX-12 D-11 43RX-13 DE-08 45RX-14 DE-09 46RX-15 DE-00 47RX-16 DE-06 49RX-17 DE-07 50RX-18 DE-01 51RX-19 DE-02 53RX-20 DE-03 54RX-21 DE-04 55RX-22 DE-05 1RX-23 SPARE 2RX-24 LVAL 3RX-25 FVAL 5RX-26 DVAL 6RX-27 DO-06 7

RX-CLK RX-CLK 26

The following are the pin numbers for the 28 signals output from the National Semiconductor Channel Link chip on the Frame Grabber:


Channel Link Interface

CameraLink Cable

CameraLink Cable Ordering


FRONT VIEW REAR VIEW

SENSOR PACKAGING


SI-3300-CL ENCLOSURE DIMENSIONS


SI-3300 Spectral Response Curve

SI-3300-RGB Cover Glass Filter Response (IRC-30)


SI-3300 SENSOR PCB DIMENSIONS


Revision UpdatesRev 1.17/31/04

Added “g” mode descriptions for Genlock operation (-H models)Added -T camera option for External TTL trigger and Global Reset operation


Contact Information

Silicon Imaging, Inc.www.siliconimaging.com

[email protected]

Ordering Information

SI-3300M-CL 3.2 Megapixel MegaCamera, Monochrome, 20~40MHz Cameralink CameraSI-3300RGB-CL 3.2 Megapixel MegaCamera, Color, Cameralink Camera SI-3300M-S 3.2 Megapixel, Monochrome, Cameralink Frame Grabber, Power Supply & CablesSI-3300RGB-S 3.2 Megapixel, Color Cameralink Frame Grabber, Power Supply & Cables-T External TTL-Trigger trigger input, Power/Trigger Cable & Global Reset Mode-H High Speed version, 20~80MHz operationPS-5 5VDC Power Supply PC-2 Power Cable, 2-MeterCBL-3PT Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug

Legal DisclaimerSilicon Imaging reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. No license, express or implied to any intellectual property rights is granted by this document.

Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SILICON IMAGING PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SILICON IMAGING PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

The Product described in this datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request.

Copyright: Silicon Imaging, Inc., 2004

070804-Rev 1.0


mailto:[email protected]

http://www.siliconimaging.com/

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