ESO RO shifted to new premises

Intel Core i7

processor 2

Solutions

Corner 13

Tips of the month 18

Feedbacks @

HCL Cochin 19

Technology

@HCL 21

Major Tech

Events 21

RRC COC H I N

Magnum Opus J U N E 2 0 0 9 V O L U M E 1 I S S U E 2

Inside this Issue:

OUR NEW ADDRESS HCL INFOSYSTEMS LIMITED, ( E S O ) “ Midland Arena “ 4/84 Marottichuvadu Junction, Edapally,COCHIN 682 024 Callboard Number – 0484— 4016500

A new dawn, new hopes and new heights to climb. This may describe our shifting to new spanking office @Edappally. With this shifting all HCL divi-sions offices in Kerala will join to make the concept of HCL ONE true. Other divisions are Office Automation Division (OA), Front Line Division (FSL) ,DMS along with the repair centres including HO3. With this effort we hope to reduce the cost of opera-tion and effectively address the require-ments of our customers. One major change in our opera-tion is ,all over Kerala except Calicut and Trivandrum( Area Offices) one unified number is in place to register customer complaints ie 0484-4016500.

All departments in ESO will have separate lines and will connect together using Centrix facility. So your call to RO will never make you hold for a long time. You can make calls to callboard and they will transfer your calls to respective depart-ments. We are going to install new UPSs to counter power problems effectively and will have generator backup. So your con-nectivity to RO will never get disturbed.

In inter department connectivity matters we will be using common Mail ,Proxy, Firewall and InfoSecuAccess servers with separate VLAN configuration. So our inner department data will never get compromised. Seven manageable L2 switches along with one L3 switch will en-sure the connectivity.

In this issue we have given a detailed de-scription about Intel core i7 architecture and given maximum importance to cus-tomer satisfaction letters. .Actually cus-tomer referral letters are pouring from all over Kerala.

That’s for the moment. Note our new office address and contact numbers. As always

our motto should be Citius, Altius, For-tius. Editorial Team RRC COCHIN

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Intel Core i7 processor

Intel Core i7 is a family of three Intel desktop x86-64 processors, the first processors released using the Intel Nehalem microarchitecture and the successor to the Intel Core 2 family. All three current models and two up-coming models are quad-core processors.

The Core i7 identifier applies to the initial family of processors codenamed Bloomfield. The name continues the use of the Core brand Core i7, first assembled in Costa Rica, as officially launched on November 17, 2008 and is manufactured in Arizona.

:

When you look at the Nehalem CPUs by themselves you have to wonder what makes them so much different than the pre-vious generation. On the left is the I7 965 Extreme Edition that features a non turbo multiplier of 24 and is unlocked both up and down. Couple the 24 mul-tiplier with the 133MHz base clock frequency and you end up at 3.20GHz. The I7 920 is at the other end of the spec-trum and has a maximum non turbo clock multiplier of 20 for a base clock speed of 2.66GHz, in turbo mode this will jump as high as 22 for a turbo speed of 2.93GHz, the same base frequency of the I7 940. To accommodate this massive chip the socket pin count is up to 1366 from the Core 2 processors 775 pin count.

Closer Look

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Specifications Features The Nehalem microarchitecture has many new features, some of which are present in the Core i7. Nehalem is the codename of the new Intel CPU with integrated memory controller that will be called Core i7; this archi-tecture will also be used on CPUs targeted to servers (Xeon) . CPUs based on this architecture will have an embedded memory controller supporting three DDR3 channels, three cache levels, the return of Hyper-Threading technology, a new external bus called QuickPath and more. It is important to remember that Core 2 CPUs manufactured under 45-nm technology have extra features compared to the Core 2 CPUs manufactured under 65-nm technology. ♦ The new LGA 1366 socket is incompatible with earlier processors. ♦ On-die memory controller: the memory is directly connected to the processor. It is called the uncore part

and runs at a different clock (uncore clock) of execution cores. ♦ Three channel memory: each channel can support one or two DDR3 DIMMs. Motherboards for Core i7

generally have three, four (3+1) or six DIMM slots. ♦ Support for DDR3 only. ♦ No ECC support. ♦ The front side bus has been replaced by the Intel QuickPath Interconnect interface. Motherboards must

use a chipset that supports QuickPath. ♦ The following caches: o 32 KB L1 instruction and 32 KB L1 data cache per core o 256 KB L2 cache (combined instruction and data) per core o 8 MB L3 (combined instruction and data) "inclusive", shared by all cores ♦ Single-die device: all four cores, the memory controller, and all cache are on a single die. ♦ "Turbo Boost" technology allows all active cores to intelligently clock themselves up in steps of 133 MHz

over the design clock rate as long as the CPU's predetermined thermal and electrical requirements are still met.

Re-implemented Hyper-threading. Each of the four cores can process up to two threads simultaneously, so the processor appears to the OS as eight CPUs. This feature was present in the older NetBurst microarchi-tecture but was dropped in Core.

Processor I7 Extreme 965 I7 940 I7 920

CPU Clock speed 3.20GHz 2.93GHz 2.66GHz

Transistor count 731 Million

Base Clock Frequency 133MHz

Die Size 263mm2

L3 Cache size 8MB

Package type 1366 LGA

Manufacturing technology 45nm

Code Name Bloomfield

Maximum Non Turbo Multiplier 24 22 20

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♦ Only one QuickPath interface: not intended for multi-processor motherboards.

♦ 45nm process technology.

♦ 731M transistors.

♦ 263 mm2 Die size.

♦ Sophisticated power management can place an unused core in a zero-power mode.

♦ Support for SSE4.2 & SSE4.1 instruction sets.

Let’s now discuss in details the most significant differences introduced by this new architecture.

Integrated Memory Controller Since the beginning of times Intel CPUs use an external bus called Front Side Bus or simply FSB that is shared between memory and I/O requests. Nehalem-based CPUs have an embedded memory controller and thus will provide two external busses: a memory bus for connecting the CPU to the memory and an I/O bus to connect the CPU to the external world. This change improves a lot the system performance for two main reasons. First, now we have separated datapaths for I/O and memory accesses. Second, memory access is faster as the CPU doesn’t need to com-municate first with an external controller anymore. On Figures 1 and 2 we are comparing the traditional architecture used by Intel CPUs and the new architec-ture that will be used by Intel CPUs with an integrated memory controller. Figure 1: Architecture used by current Intel CPUs.

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Figure 2: Architecture used by Intel CPUs with embedded memory controller.

This new external bus is called QuickPath Interconnect (QPI) and it provides two separated datapaths (one for transmitting data and another for receiving data) for the CPU to communicate with the chipset or with other CPUs, in the case of servers with more than one CPU. As you can see, this bus is the equivalent of the Hy-perTransport bus used on AMD CPUs. The first generation of QuickPath Interconnect will run at 3.2 GHz transferring two 16-bit data per clock tick, which equals to a maximum theoretical transfer rate of 12.6 GB/s on each direction. Desktop CPUs will have only one QuickPath Interconnect, while server CPUs will have two independent bus-ses to allow them to be connected together on SMP (Symmetric Multiprocessing) environments. The memory controller integrated on Nehalem-based processors provides three memory channels, i.e. it is capable of accessing three memory modules at the same time, in parallel, in order to improve performance – in theory triple-channel architecture provides a 50% increase of available bandwidth compared to a dual-channel architecture running at the same clock rate. The memory controller embedded on Nehalem-based CPUs accepts only DDR3 memories – no support for DDR2 is given. Due to the integration of the memory controller, Intel has to change the CPU socket to a new socket using 1,366 pins.

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Memory Cache On the cache memory side Intel will use the same cache arrangement AMD is using on their Phenom CPUs, i.e. individual L2 caches for each core and a shared L3 memory cache. Each L2 memory cache will be of 256 KB and the L3 cache will be of 8 MB, at the least for the first models to be launched (Intel may launch Neha-lem-based Xeon CPUs with more cache). L1 cache remains the same as Core 2 Duo (64 KB, 32 KB for in-structions and 32 KB for data). Core 2 Duo processors have only one L2 memory cache, which is shared among all CPU cores, but quad-core CPUs from Intel like Core 2 Quad and Core 2 Extreme have two L2 caches, each one shared by each group of two cores. For a better understanding we summarize the available cache architectures on Figures 3 and 4. Figure 3: A comparison between cache architectures. Figure 4: A comparison between cache architectures.

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Enhancements to the CPU Pipeline As mentioned, Nehalem (Core i7) is based on the architecture used by Core 2 Duo, bringing some enhance-ments on the way instructions flow inside the CPU. Core 2 Duo is, by the way, based on Pentium M, which in turn is based on Pentium III. All these CPUs are 6th generation Intel CPUs Pentium 4 was a 7th generation Intel CPU, using a complete different microarchitecture – Core 2 and Core i7 CPUs have absolutely nothing to do with Pentium 4. Refer to Figure 5 to understand the genealogy of the new Nehalem microarchitecture. Figure 5: Nehalem microarchitecture genealogy tree. In order to understand the improvements brought by this new microarchitecture you need to remember that programs are written using x86 instructions (also called “macro-op” or simply “instructions”), which aren’t un-derstandable by the CPU execution units. They must be first decoded into microinstructions (also called “micro-op” or “µop”). This architecture is a CISC/RISC hybrid and was introduced by the Pentium Pro: CPU receives x86 (CISC) instructions, but execute proprietary microinstructions (RISC). Core microarchitecture, used on Core 2 CPUs, introduced macro-fusion, which is the ability of translating two x86 instructions in just one microinstruction (also known as “micro-ops”) to be executed inside the CPU, im-proving performance and lowering the CPU power consumption, since it will execute only one microinstruc-tion instead of two. This scheme, however, only works for comparing and conditional branching instructions (i.e. CMP or TEST plus a Jcc instruction). Core microarchitecture also add a Loop Stream Detector, basically a small 18-instruction cache between the fetch and the decode units from the CPU. When the CPU is running a loop (a part of a program that is re-peated several times) the CPU doesn’t need to fetch the required instructions again from the L1 instruction cache: they are already close to the decode unit. In addition the CPU actually turns off the fetch and branch prediction units while running a detected loop, making the CPU to save some power.

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Nehalem microarchitecture improves macro-fusion in two ways. First it adds the support for several branching instructions that couldn’t be fused on Core 2 CPUs. And second, on Nehalem-based CPUs macro-fusion is used on both 32- and 64-bit modes, while on Core 2 CPUs macro-fusion only works when the CPU is working under 32-bit mode. Core microarchitecture also add a Loop Stream Detector, basically a small 18-instruction cache between the fetch and the decode units from the CPU. When the CPU is running a loop (a part of a program that is re-peated several times) the CPU doesn’t need to fetch the required instructions again from the L1 instruction cache: they are already close to the decode unit. In addition the CPU actually turns off the fetch and branch prediction units while running a detected loop, making the CPU to save some power. On Nehalem-based CPUs this small cache has been moved to after the decode unit. So instead of holding x86 instructions like on Core 2 CPUs, it holds micro-ops (up to 28). This improves performance, because when the CPU is running a loop, it now doesn’t need to decode the instructions present in the loop: they will be already decoded inside this small cache. Also, the CPU can now turn off the decode unit in addition to the fetch and branch prediction units when running a detected loop, saving even more power. Figure 6: Location of the Loop Stream Detector on Core and Nehalem CPUs. Nehalem architecture adds one extra dispatch port and has now 12 execution units, see below. With that CPUs based on this architecture can have more microinstructions being executed at the same time than pre-vious CPUs.

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Figure 7: Dispatch ports and execution units. Nehalem microarchitecture also adds two extra buffers: a second 512-entry Translation Look-aside Buffer (TLB) and a second Branch Target Buffer (BTB). The addition of these buffers increases the CPU perform-ance. TLB is a table used for the conversion between physical addresses and virtual addresses by the virtual mem-ory circuit. Virtual memory is a technique where the CPU simulates more RAM memory on a file on the hard drive (called swap file) to allow the computer to continue operating even when there is not enough RAM avail-able (the CPU gets what is on the RAM memory, stores inside this swap file and then frees memory for us-ing). Branch prediction is a circuit that tries to guess the next steps of a program in advance, loading to inside the CPU the instructions it thinks the CPU will try to load next. If it hits it right, the CPU won’t waste time loading these instructions from memory, as they will be already inside the CPU. Increasing the size (or adding a sec-ond one, in the case of Nehalem-based CPUs) of the BTB allows this circuit to load even more instructions in advance, improving the CPU performance.

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Power Management Enhancements Transistors inside the CPU work as a switch, with two possible states: conductive (a.k.a. “saturation mode”), working as a closed switch, and non-conductive (a.k.a. “cut-off” mode), working as an open switch. The prob-lem is when they are on their non-conductive state in theory they shouldn’t allow any current to flow, but a small amount of current still flows. This current is called leakage and if you add up all leakage currents you have a significant amount of current (and thus power) being wasted and unnecessary heat being generated. One of the challenges in designing CPUs in recent years has been trying to eliminate leakage current. Nehalem brings a power control unit inside the CPU in order to better manage power (see Figure 8). Figure 8: Power control unit. This unit reduces leakage current and also allows the new “Turbo Mode”, which we will discuss on next page. Basically, the CPU can now have different voltages and frequencies for each core, for the units outside the cores, for the memory controller, for the cache and for the I/O units. On previous CPUs, all cores had to run at the same clock rate but on Nehalem-based CPUs each core can be programmed to run at different clock rates to save power. The embedded power control unit can now switch off any of the CPU cores, feature not available on mobile Core 2 CPUs. In fact now the CPU can put any core into the C6 (“deep power down”) power state independ-ently of the state under the remaining cores are running. This allows energy savings when you are running your PC normally but one or more cores are idle and thus can be shut down.

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Other Features HyperThreading technology allows each CPU core to be recognized as two CPUs. Thus if you have a Core i7 with four cores, the operating system will recognize it as having eight cores. This technology is based on the fact that when the CPU core is running there are certain circuits inside that are idle and thus can be used. Originally released for the Pentium 4 CPU this is the first time this technology is available on a 6th generation Intel CPU. This technology is also called SMT or Simultaneous Multi-Threading (SMT). This technology does not provide the same performance gain as if “real” CPU cores were used instead (i.e. a CPU with 8 cores is faster than a CPU with 4 cores and HT technology, provided that they both work under the same clock rate and are based on the same architecture), however you are gaining these extra “CPU cores” for free.

There are two kinds of SSE instructions that access memory, aligned and unaligned (also called misaligned). Aligned instructions required the requested data to be inside 16-byte (128-bits) address boundaries, while unaligned instructions don’t. See Figure 9 for an illustration.

Aligned vs unaligned (misaligned) instructions Figure 9: Aligned vs. unaligned instructions. Imagine a system with dual-channel memory. The memory controller will access the memory 128 bits at a time. So the memory will be divided into 128-bit (16 bytes) blocks. So in theory the address that you request must start at the beginning of each block, so you can make a 128-bit read (or write) and get what you want at just one request. This is the aligned request shown on top of Figure 9. But suppose that you issue a command to read a data from the memory but instead of using the first address inside the block you ask for the address in the middle of the block.

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Since you are requesting a 128-bit data, what will happen is that half of the data will be on the first block and the other half of the data will be on the next block – this is shown on the bottom of Figure 9. Since the data you requested will be split into two different blocks the memory controller will have to read two memory blocks, not just one as it happened on the previous example. On the first read you will get back half of the data you want and on the second read you will get the remaining of the data. Although aligned requests are more efficient they are more difficult for programmers because they need to know the memory organization. Because of that most programmers end up using only unaligned instructions. Previous Intel CPUs were optimized for aligned instructions and unaligned ones were slower and were trans-lated into multiple micro-ops – in other words, unaligned instructions were easier for the programmer but ran slower. Nehalem-based CPUs are optimized for unaligned instructions, achieving the same speed as aligned instructions. The slide on Figure 10 summarizes this.

Figure 10: Nehalem is optimized for unaligned SSE instructions.

Prepared by:Jinish.K.G,

Regional response Centre,Cochin,

Source:www.intel.com

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Customer: Thalikulam SCB Head Office,Thrissur

Engineer: Ouseph.N.A

Solution provided by: Jinish.K.G

Problem Reported CD drive or DVD drive is missing or is not recognized by Windows.

Resolution

FOR Microsoft Windows XP Click Start, and then click Run. In the Open box, type regedit, and then click OK. In the navigation pane, locate and then click the following registry subkey: HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Class\{4D36E965-E325-11CE-BFC1-08002BE10318} In the right pane, click UpperFilters.On the Edit menu, click Delete. When you are prompted to confirm the deletion, click Yes.In the right pane, click LowerFilters.On the Edit menu, click Delete. When you are prompted to confirm the deletion, click Yes.Exit Registry Editor. Restart the computer.

FOR Microsoft Windows VISTA Click Start then click All Programs. Click Accessories, and then click Run.Type regedit, and then click OK. If you are prompted for an administrator password or for a confirmation, type the password, or click Allow. In the navigation pane, locate and then click the following registry subkey: HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Class\{4D36E965-E325-11CE-BFC1-08002BE10318} In the right pane, click UpperFilters. On the Edit menu, click Delete.When you are prompted to confirm the deletion, click Yes.In the right pane, click LowerFilters. On the Edit menu, click Delete. When you are prompted to confirm the deletion, click Yes. Exit Registry Editor. Restart the computer.

Solutions Corner

Send your tips to: rrccn@hcl.in

14

Customer: Sarathy Autocars Kollam

Engineer: Vinod.M.V

Solution provided by: Baluraj

Problem Reported Microsoft Excel files opening in grey blank pages and no sheets are displayed

Resolution

This can happen for several reasons: Least likely is that your workbook has hidden sheets, such as with a personal.xls file. So, just go to Format->Sheet->Unhide. Excel isn't really opening your workbook at all. Go to Tools->Options, General tab. Uncheck Ignore Other Ap-plications. The worksheet has gotten hidden within the application window. Go to Window->Arrange, and hit OK. Check also these settings First, open any folder in Windows . Click on the Tools menu, and choose Folder Options. From the dialog that pops up, click the File Types tab. You will now be presented with a list of all document types recognized by your computer. Scroll down to XLS, select it, and click the Advanced button. Now you'll see several "Actions" registered for Excel worksheets. Usually, Open is the default (indicated by being in bold). Select "Open" and click the Edit button. The main piece of data in here is the field labeled "Application used to perform action". This should point to your Excel executable, followed by some command-line arguments. Here's how it appears on my PC: "C:\Program Files\Microsoft Office\Office\EXCEL.EXE" /e "%1" It is very important to make sure that the %1 is surrounded by quotes. %1 is the variable representing the full path and file name of the document you are opening. If it contains any spaces, and this is not surrounded by quotes you will get a flurry of weird errors. "Use DDE" is normally checked. Now, make sure that "DDE Message" is empty. Click OK. Click OK back at the Edit File Type dialog. Click Close on the Folder Options dialog.

Solutions Corner

Send your tips to: rrccn@hcl.in

15

Customer: SBI Attingal

Engineer: GopiRaj

Solution provided by: Devasia.C.M

Problem Reported Not able to open any file with extention .exe

Resolution

Open the ‘Run’ command in the start menu,enter ‘regedit’ and click ‘OK’ In the registry editor navigate your way to the

HKEY_CLASSES_ROOT\exefile\shell\open\command.It should have a default value of: "%1" %* exactly as typed here.

Solutions Corner

Send your tips to: rrccn@hcl.in

16

Solutions Corner

Customer: Various Schools

Solution provided by: Asif.P,Kasaragod

Problem Reported ‘No signal’ problem in LCD monitor due to improper resolution settings in IT@Linux OS.

Resolution

Method 1

1. Press CTRL+ALT+F1

2. Login as root pwd:hcl123

3. Enter command as dpkg-reconfigure xserver-xorg

4. Give OK to all output.

5. Restart.

Method 2

1. At welcome screen click actions->configure the login manager->security->allow localsystems

select that option and close the window then login as root ;pwd: hcl123

2. Edit file /etc/x11/xorg.conf

3. Remove all entries except ‘800x600’ in screen resolution field.

4. Save and restart.

Method 3

1. Login as single user mode and follow step 2 to 5 from solution 1.

Send your tips to: rrccn@hcl.in

17

Problem Reported Customer: AGs Office Trivandrum

Engineer:Sreenivasan,Trivandrum

Solution provided by: Sudheesh Kumar.T.S Disk full message in SCO-Unix Resolution

To check disk space

1. du –a -> in blocks where a blocksize is 512 bytes

2. df –f -> will show a larger block size compared to previous command

because it will show full inode size

3. dfspace for showing disk space in MB

These are the log files in SCO UNiX

Administrative log files

Solutions Corner

Send your tips to: rrccn@hcl.in

Log File Purpose Checking frequency

/etc/wtmp historical login record automatic

/usr/adm/pacct process accounting log file weekly

/usr/adm/messages system messages log file weekly

/usr/adm/sulog su(C) log file automatic

/tcb/audittmp/ audit system temporary files weekly

/usr/spool/uucp/LOGFILE records of UUCP job requests,

file transfers, system status

monthly

/usr/spool/uucp/.Log/.Old/ old UUCP log files stored by uudemon.clean

monthly

/usr/spool/lp/logs/requests record of print requests automatic

find / -size +3 -print to search for files greater than (3512 bytes)

so for searching for files greater than 100 MB size we need to give find / -size +200000 –print.

We should not delete log files, we rather trim it.For ex to trim the /etc/wtmp file cat /dev/null >/etc/wtmp.

Or #> /etc/wtmp

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Reducing the Wait Time

When you start to shut down Windows XP, it has to quit, or "kill," any live applications or processes that are

currently running. So close all applications first. However, some applications and processes are always run-

ning in the background. You can reduce the amount of time that Windows XP waits for those applications and

processes to close before Windows XP kills them.

Open registry editor

Navigate to HKEY_USERS\.DEFAULT\Control Panel\Desktop. Set the WaitToKillAppTimeout and set the

value to 1000. Select the HungAppTimeout value and set it to 1000 as well.

Navigate to HKEY_LOCAL_MACHINE\System\CurrentControlSet\Control. Select the WaitToKillServiceTime-

out value and set it to 10000.Close the Registry Editor.

Automatically Killing Tasks on Shutdown

You start to shut down the computer, you wait a few moments, and then you see a dialog box asking if you

want to kill an application or service that is running. Instead of prompting you, you can make Windows XP

take care of the kill task automatically. Here's how:

Open the Registry Editor.

Navigate to HKEY_CURRENT_USER\Control Panel\Desktop.Highlight the value AutoEndTasks and change

the value to 1.Close the Registry Editor.Restart the machine.

Alter Prefetch Parameters

Pre-fetching (the reading of system boot files into a cache for faster loading) is a commonly overlooked com-

ponent that can have a significant impact on system boot time. To see which files are gathered using each

setting, clear the prefetch cache located at C:\Windows\Prefetch and then enable one of the settings listed in

this hack. Clear the cache and repeat for each setting. Set the Registry key

HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Session Manager\ Memory Manage-

ment\PrefetchParameters\EnablePrefetcher to 0 to disable prefetching, 1 to prefetch application launch files,

2 to prefetch boot files, or 3 to prefetch as many files as possible.

A Flying Start for the Start Menu

A simple Registry tweak can give speed up your start menu and sub-menus. Open the Registry Editor, and

navigate to and select:HKEY CURRENT USER\Control PanelXDesktop.Double-click the MenuShowDelay

icon on the right, and change 'Value data' from its default of 400 (milliseconds) to something speedier, like 0.

When you have finished, press Enter.

Tips of the month

19

Feedbacks @ cochin

Please sent your customer satisfaction letters to rrcccn@hcl.in

Engineer:Devasia.C.M,Cochin Sales tax Office Mattanchery Cochin,Officer says

“I am very grateful to you and your firm which gives a good technical support to to solve our internet problem. We expect such cooperation from your side in the future also.”

Engineer:Jinish.K.G,Cochin Mr.Shaji, Regional Cancer Centre,Trivandrum

“Very Quick and Good Support from HCL RRC Team”

Engineer:Devasia.C.M,Cochin Mr.BHUVANADAS,Senior Manager Canara bank Pallur Mahe

“Thanks a lot for the timely help”

Engineer:Devasia.C.M,Cochin Mr.Lal,Manger from Hotel Thampuru International, Trivandrum

“I am really satisfied with your remote support services. I am also recommended your latest mode of services to my friend who has got computer technical support with other organizations in Trivandrum”

20

Feedbacks @ cochin

Please sent your customer satisfaction letters to rrcccn@hcl.in

Engineer:BaluRaj,Cochin

Mr Santhosh,EDP Manger,Sarathy Auto Cars,Kollam

“We would like to place on record the excellent professional support received from Mr. BALURAJ. T. R. His behavior and attitude was found to be very excellent. He has got required skills and perseverance to attend the computer and network related problems remotely. We appreciate his high level of commitment to complete the work assigned to him”.

Engineer:Mr.Ranjith.M.L,Trivandrum System Administrator from Hotel Thamburu international trivandrum, “The service provided by your office,especially ypur engineer Sri.Ranjith M.L is very good.We are getting very good response from your engineer.we are satis-fied and happy with the service and support.Your Engineer provided to be very hardworking efficient,skill full and soft spoken.We hope with this support will continue without interrupt in future also”.

Engineer:Devasia.C.M,Cochin BSNL,Kottayam, OCB Exchange

“Very good response at any time “

21

Feedbacks @ cochin

Please sent your customer satisfaction letters to rrcccn@hcl.in

Engineer:Rajesh.A

Chief Manger,State Bank of India,Trivandrum “we express our extreme satisfaction about the IT support service delivered to us by

your engineer Mr.Rajesh.A.He carried out his duties to our best satisfaction.He is al-

ways quick in attending and solving our complaints effectively.We appreciate him for

his co-operation.professionalism,sincerity and technical abilities and we wish him suc-

cess in his future carrier”.

Engineer:Mr.Rajesh.A

Manger,Federal bank ,Trivandrum

“We appreciate him for his co-operation.professionalism,sincerity and technical abilities

and we wish him success in his future carrier”.

Engineer:Ranjith.M.L,Trivandrum

Inspector of Police,Immigration Wing Trivandrum airport

“I would like to extend my happiest gratitude towards Mr.Ranjith M.L Customer En-

gineer HCL Infosystems Ltd for his tremendous effort for solving computer and net-

work related problems of thyis Immigartion check post.We are sure with his good be-

haviour,positive attitude and good technical skill,he will be an asset to the organiza-

tion which he serves.”

22

May 2

Mandriva Linux 2009 Spring Released..Windows 7 RC Released to TechNet, MSDN Subscribers.

May 4

HCL Infosystems Ltd launches HCL Leaptop Z39 series.

May 9

OpenOffice.org 3.1 Released.KDE 4.2.3 Released. Intel Stops Core i7 940, 965 processors

May 11

Epson Launches Wireless All-in-One Printer in India.

May 12

HCL Infosystems announced a new partnership with Microsoft whereby HCL will be Microsoft's voice solutions partner

for OCS R2.

May 18

Microsoft released Internet Explorer 8 Multilingual User Interface (MUI) packs for Windows XP SP2/SP3 and Windows

Server 2003 SP2

May 21

The NEC Electronics device Introduces World's First USB 3.0 Controller.

May 22

The Google Chrome 2.0 Web Browser released.

May 27

Service pack 2 released for Windows vista and windows 2008 server.

May 28

HCL wins Rs 240 crore ERP-based System Integration deal from BSNL.

MAJOR TECH EVENTS

RRC COCHIN The Technology Meets The Passion

News letter design:RRC COCHIN Editorial Team, E-mail:rrcccn@hcl.in, Phone-04844016507,6508,6509.6510 Address: HCL INFOSYSTEMS LTD,Midland Arena,4/84 Marottichuvadu junction Edappally,COCHIN-682024

TECHNOLOGY @HCL

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24*7*365 days customer support for HCL Leaptops • Universal Number: 1860 1800 425 • SMS: +919911115555 • Email for call registration: hcltouch.reg@hcl.in