m31 usb 3.1/ usb 3.0/ usb 2.0 phy ip for host and ...flyer version no. m31708 m31 usb 3.1/ usb 3.0/...

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Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications TX Eye Diagram USB 3.1 PHY IP with Type-C connector support Overview M31 USB 3.1 transceiver IP provides a complete range of USB 3.1 host and peripheral applications up to 10Gbps. It is compliant with the PIPE4.3 and UTMI+ specification. The USB 3.1 IP integrates high-speed mixed signal circuits to support super-speed Gen2 and Gen1 traffic and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at 12Mbps and low-speed data rate at 1.5Mbps. To support the USB Type-C connector, the USB 3.1 IP also integrates the active switch to support the bi-directional plug-in and the specific functions (USB attachment cable orientation detection and VBUS configuration) through the CC1/CC2 pins defined in Type-C connector. Highlights Worldwide smallest USB 3.1 PHY IP in 28nm process (IP size is smaller than 0.6mm²) Fully compliant with Universal Serial Bus (USB) 3.1 and 2.0 electrical specifications Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core (25MHz, 50MHz and 100MHz) Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX Integrates an active switch to support the orientation-less connection with USB Type-C connector Provides an auxiliary CC module IP to support USB Type-C related functions Supports both Wire-bond and flip-chip package type USB 3.1 Gen2 PHY IP is available in 28nm process and USB3.1 Gen1 PHY IP is available in 28nm, 40nm, 55nm and 110nm process Block Diagram The USB3.1 PHY supports full USB 3.1 Gen2/ USB 2.0 functions and Type-C features within 1 compact IP hard macro RX Jitter Tolerance For USB 3.1 Device with Type-C Connector Sinusoidal Jitter [ps] Sinusoidal Jitter Frequency [MHz] 1 10 1000 100 10000 0.1 1 10 100 RX2_10G_JToL RX1_10G_JToL USB3.1 TX1 USB3.1 TX2 Sinusoidal Jitter [ps] Sinusoidal Jitter Frequency [MHz] 1 10 1000 100 10000 0.1 1 10 100 Min Failed Jitter Max Passed Jitter Jitter Capability Test Setup Min Spec Min Failed Jitter Max Passed Jitter Jitter Capability Test Setup Min Spec Deserilizer SSCG-PLL Crystal / Coreclkin Elastic Buffer TX Logic CC Module DP DP HS CDR FS CDR Elastic Buffer PLL and Clock Generator NRZI Decoder and Bit-stuffer NRZI Decoder and Bit-stuffer RX State Machine TX State Machine Control Logic UTMI+ PIPE M U X M U X M U X M U X Serializer RX Logic SSRXM0 SSRXP0 SSRXM1 SSRXP1 Pattern Generator Shift/Hold Register Shift/Hold Register 8b/10b Encoder 8b/10b Decoder Pattern Checker DM DM D E M U X SSTXM0 SSTXP0 CC1 CC2 SSTXM1 SSTXP1 EQ/CDR TX Driver Crystal / Coreclkin TX TX RX RX HS TX/RX FS TX/RX Real-Time Eye 1.98875 MUI 1 Wfms 727mV 545mV 364mV 182mV -181mV -363mV -726mV 100 ps -100 ps 80.2 ps -80.2 ps 60.1 ps -60.1 ps 40.1 ps -40.1 ps 20.0 ps -20.0 ps 0.0 ps 100 ps -100 ps f1 f1 80.2 ps -80.2 ps 60.1 ps -60.1 ps 40.1 ps -40.1 ps 20.0 ps -20.0 ps 0.0 ps -545mV 0.0 V 726mV 544mV 363mV 181mV -182mV -364mV -727mV -546mV -1 V Real-Time Eye 1.98892 MUI 1 Wfms

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Page 1: M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and ...Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications £ ¤ ,"µ ÷ 70O î TX Eye

Flyer Version no. M31708

M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IPfor Host and Peripheral Applications

TX Eye Diagram

USB 3.1 PHY IP with Type-C connector support

Overview

M31 USB 3.1 transceiver IP provides a complete range of USB 3.1 host and peripheral applications up to 10Gbps. It is

compliant with the PIPE4.3 and UTMI+ specification. The USB 3.1 IP integrates high-speed mixed signal circuits to support

super-speed Gen2 and Gen1 traffic and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at

12Mbps and low-speed data rate at 1.5Mbps. To support the USB Type-C connector, the

USB 3.1 IP also integrates the active switch to support the bi-directional plug-in and the

specific functions (USB attachment cable orientation detection and VBUS configuration)

through the CC1/CC2 pins defined in Type-C connector.

Highlights

Worldwide smallest USB 3.1 PHY IP in 28nm process (IP size is smaller than 0.6mm²)

Fully compliant with Universal Serial Bus (USB) 3.1 and 2.0 electrical specifications

Supports clock inputs from 25MHz crystal oscillator and external clock

sources from the core (25MHz, 50MHz and 100MHz)

Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX

Integrates an active switch to support the orientation-less connection with

USB Type-C connector

Provides an auxiliary CC module IP to support USB Type-C related functions

Supports both Wire-bond and flip-chip package type

USB 3.1 Gen2 PHY IP is available in 28nm process and USB3.1 Gen1 PHY

IP is available in 28nm, 40nm, 55nm and 110nm process

Block Diagram

The USB3.1 PHY supports full USB 3.1 Gen2/

USB 2.0 functions and Type-C features

within 1 compact IP hard macro

RX Jitter ToleranceFor USB 3.1 Device with Type-C Connector

Sin

uso

ida

l Jitte

r [p

s]

Sinusoidal Jitter Frequency [MHz]

1

10

1000

100

10000

0.1 1 10 100

RX2_10G_JToL

RX1_10G_JToL

USB3.1 TX1 USB3.1 TX2

Sin

uso

ida

l Jitte

r [p

s]

Sinusoidal Jitter Frequency [MHz]

1

10

1000

100

10000

0.1 1 10 100

Min Failed Jitter

Max Passed Jitter

Jitter Capability Test Setup

Min Spec

Min Failed Jitter

Max Passed Jitter

Jitter Capability Test Setup

Min Spec

Deserilizer

SSCG-PLLCrystal /

Coreclkin

ElasticBuffer

TX Logic

CC Module

DPDP

HS CDR

FS CDR

Elastic

Buffer

PLL

and

Clock Generator

NRZI Decoderand

Bit-stuffer

NRZI Decoderand

Bit-stuffer

RX State Machine

TX State Machine

Control Logic

UT

MI+

PIP

E

MUX

MUX

MUX

MUX

Serializer

RX LogicSSRXM0

SSRXP0

SSRXM1

SSRXP1

PatternGenerator

Shift/HoldRegister

Shift/HoldRegister

8b/10bEncoder

8b/10bDecoder

PatternChecker

DMDM

DEMUX

SSTXM0

SSTXP0

CC1

CC2

SSTXM1

SSTXP1

EQ/CDR

TX Driver

Crystal /

Coreclkin

TX

TX

RX

RX

HS TX/RX

FS TX/RX

Real-Time Eye

1.98875 MUI

1 Wfms

727mV

545mV

364mV

182mV

-181mV

-363mV

-726mV

100 ps-100 ps 80.2 ps-80.2 ps 60.1 ps-60.1 ps 40.1 ps-40.1 ps 20.0 ps-20.0 ps 0.0 ps 100 ps-100 ps f1f1 80.2 ps-80.2 ps 60.1 ps-60.1 ps 40.1 ps-40.1 ps 20.0 ps-20.0 ps 0.0 ps

-545mV

0.0 V

726mV

544mV

363mV

181mV

-182mV

-364mV

-727mV

-546mV

-1 V

Real-Time Eye

1.98892 MUI

1 Wfms

Page 2: M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and ...Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications £ ¤ ,"µ ÷ 70O î TX Eye

USB 3.0 PHY IP

Overview

M31 USB 3.0 transceiver IP provides a complete range of USB 3.0 host and

peripheral applications. It is compliant with the PIPE 3.0 and UTMI+

specification. The USB 3.0 IP integrates high-speed mixed signal circuits to

support super-speed traffic at 5Gbps and is backward compatible to

high-speed data rate at 480Mbps, full-speed data rate at 12Mbps and

low-speed data rate at 1.5Mbps.

Highlights

Worldwide smallest USB 3.0 PHY IP in 28nm process (IP size is smaller than 0.5mm²)

Fully compliant with Universal Serial Bus (USB) 3.0 and 2.0 electrical specifications

Compliant with PIPE3.0 and UTMI+ specification (Super-Speed, High-Speed, Full-Speed and Low-Speed functions)

Supports clock inputs from 25MHz crystal oscillator or external 25MHz clock source

Provides plenty of register controls for TX, RX, SSCG-PLL and CDR electrical parameters

Silicon proven and mass production IP records

USB-IF certified PHY IP are available in 28nm, 40nm, 55nm, 65nm and 110nm process

RX Jitter ToleranceRx_5G_JTol

for USB 3.0 Device with Standard-B Connector

Sin

uso

ida

l Jitte

r [U

I]

Sinusoidal Jitter Frequency [MHz]

0.1

1

10

0.1 1 10 100

TX Eye Diagram

-0.6

0.6

-0.2 0.1 0.2 0.3 0.4

Unit Intervals [UI]

Diffe

ren

tia

l S

ign

al [V

]

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2-0.1 -0.0

-0.5

0.5

-0.4

0.4

-0.0

-0.3

0.3

-0.2

0.2

-0.1

0.1

The USB 3.0 PHY supports full USB 3.0/

USB 2.0 functions within 0.5mm²

M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IPfor Host and Peripheral Applications

Min Failed Jitter

Max Passed Jitter

Jitter Capability Test Setup

Min Spec

Page 3: M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and ...Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications £ ¤ ,"µ ÷ 70O î TX Eye

like the M31 galaxy, inspiring unlimited imagination and bringing us a brighter future

USB 2.0 PHY IP

Overview

M31 provides customers a next generation USB 2.0 IP which delivers an

extremely smaller die area and lower active and suspend power consumption.

M31 uses a whole new design architecture to implement the USB 2.0 IP

without sacrificing USB 2.0 related performances. The USB 2.0 IP is not only

suitable for USB peripherals but also an optimized solution for SOC which is

eager for multiple USB ports.

Highlights

Worldwide smallest USB 2.0 PHY IP (IP size of 55nm, 40nm, 28nm, and 16/12nm are smaller than 0.2mm²)

Fully compliant with Universal Serial Bus (USB) 2.0 electrical specifications

Compliant with UTMI+ specification (High-Speed, Full-Speed and Low-Speed functions)

Supports clock inputs from 10/12/25/30MHz crystal oscillator or external 10/12/25/30MHz clock source

Integrated PLL to provide a variety of stand-alone clock outputs for USB related applications

Available in 12nm, 16nm, 28nm, 40nm, 55nm and 110nm process

*GDS size evolution of USB2.0 Tiny PHY under different Process

Diffe

ren

tia

l sig

ma

l [V

]

Time [ns]

-0.4

-0.2

0.0

0.2

0.4

0.0 0.5 1.0 1.5 2.0

GDS Size: 110nm 16/12nm

IP Size (After Shrink): 0.348mm² 0.14mm²

Page 4: M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and ...Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications £ ¤ ,"µ ÷ 70O î TX Eye

like the M31 galaxy, inspiring unlimited imagination and bringing us a brighter future

Flyer Version no. M31708

Copyright© 2017 M31 Technology Corporation. All rights reserved. The information and material included in this flyer are

provided by M31 Technology Corporation as a service to its customer. The material is to be used for information purposes only.M31 Technology Corporation www.m31tech.com

M31 Headquarters | M31 Technology USA Inc. | M31 Technology (Shanghai), Inc.

[email protected] | [email protected]

USB 1.1 PHY IP for IOT and Low Power application

Overview

M31 provides customers a unique USB 1.1 PHY IP for IOT application. The USB 1.1 PHY

IP incorporates a semi-digital PLL which can supports clock inputs as low as 32.768KHz.

The USB 1.1 PHY IP not only supports the standard USB 1.1 functions but also provides

multiple clock outs ranged from 48MHz to 240MHz. It’s extremely suitable for IOT devices

or wearable devices which may need the basic USB functions.

Highlights

Worldwide smallest USB 1.1 PHY IP with PLL inside (<0.1mm²)

Fully compliant with Universal Serial Bus (USB) 1.1 electrical specifications

Integrated PLL to provide a variety of stand-alone clock outputs

Available in 40nm and 55nm ULP process

BCK Technology Specialized for Peripheral Applications

M31 provides customers with not only a standard USB PHY solution, but also

a unique BCK (Built-in-Clock) function to eliminate the need of external crystal

oscillator. The IP processes background calibration during USB data transfer to

ensure frequency accuracy. The USB IP with BCK can meet the USB-IFcompliance

spec and exhibit the same electrical performances as the standard USB IP.

Highlights

Fully compliant with Universal Serial Bus (USB) 3.0, 2.0 and 1.1 electrical specifications

Supports clock inputs from internal BCK module

Real-time calibrations to assure the frequency accuracy

Data UI (unit interval) is well-controlled within ±500ppm during data transfer

Concise and explicit design structure to ease the IP integration

Available in 40nm, 55nm and 110nm logic process

The unique USB1.1 PHY IP with a semi-digital

PLL inside only consumes area < 0.1mm²

Diffe

ren

tia

l sig

ma

l [ V

]

Time [ns]

-0.4

-0.2

0.0

0.2

0.4

0.0 0.5 1.0 1.5 2.0

The BCK Series USB PHY still exhibit very good jitter control

even if it’s without the external clock sources

0.7

-0.7

-200m 220m 360m 500m 640m

Unit Intervals [UI]Legend: Waveform

Vo

lta

ge

[V

]

780m 920m 1.06 1.2-60m 80m

0.525

-0.525

0.35

-0.35

0.175

-0.175

0

D+

an

d D

- [ V

]

Time [ns]

0

1

2

3

4

0 10 20 30 40 50 60 70 80