Low Volt age Analog Cir cuitDesign Techniques:A Tut or ialEdgar Snchez-Sinencio http://amsc.tamu.edu/Texas A&M UniversityAnalog and Mixed-Signal CenterIEEE Dallas CAS Workshop 2000 March 27, 2000Low volt age (LV) powersupply cir cuitdesign t echniques ar e addr essed in t his t ut or ial. I n par t icular :(i) I nt r oduct ion; (ii)Tr ansist or modelscapablet opr ovideper f or mance and powerconsumpt ion t r adeof f s; (iii)Lowvolt ageimplement at iont echniques,suchas f loat ing gat es andbulk dr iven;(iv) Basic building blocks notinvolving cascode st r uct ur es, and(v) LV cir cuitimplement at ions examples.Low Volt age Analog Cir cuitDesign Techniques: RoadmapAnalog and Mixed-Signal Center, TAMUMot ivat ion What are the challenges in designing low voltage circuits ?- To operate with power supplies smaller than 3.3 volts- To design circuits with the same performance or better than circuits designed for larger power supplies- To perform with technologies smaller than 0.5 micron-To come with new design alternatives, The need for analog circuits in modern mixed-signal VLSI chips for multimedia, perception, control, instrumentationmedical electronics and telecommunication is very high.Analog and Mixed-Signal Center, TAMU- Designers can not use conventional cascode structures, and other conventional design methodologies.- Circuits should have the same performance or better than circuits designed for larger power supplies- Circuit performance with technologies smaller than 0.5um must be better than circuits for larger technologies. -Third-generation communication applications require circuits ( and systems)with improved dynamic range over a much wider bandwidth.- New building blocks and system must be designed to satisfy the needs of portable, lighter and faster equipment( continues)Analog and Mixed-Signal Center, TAMU Why are we concerned in designing low voltage circuits ?I ssues aboutlow powersupply volt ageMister 5 voltsICMister 0.8 volts ICVTHVTHScaling down size technology andsupply voltage does not scale linearly the VTH hat Threshold and VDSAT do not scale down linearly with power supply nor with smaller size technologies. Let us consider an illustrative example of a cascode and a simple inverting amplifiers, assume transistors MC and MS carry the same current IL, VT= 0.75V and VDS(SAT)=0.2V Keeping the same output voltage swing for both circuits involve the tradeoffs shown in the plot of transistor sizes and GBW vs. Power Supply Voltage How t o det er mine how much bias cur r entis needed f orcer t ain applicat ion ? When a designer operates transistors in saturation, what does it mean VDS > VDS(SAT)? Can a circuit have their transistors operating in the transitionregion ?What transistor model equation can be employed ?One Equation-All RegionsTransistor Model Features of ACM model: physics-based model, universal and continuous expression for any inversion, independent of technology, temperature, geometry and gate voltage, same model for analysis, characterization and design. Main design equations: (design parameters: I, gm, if)21 1fm tin gI+ +f( ) 1 1 222 + ftTiLfpmf1 11 +f t oxmi CgLWf m( ) 4 1 1 + + ftDSATiVf

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1 2n gICgLWm tt oxmff mI drain current in transistorgm transconductance in saturationn slope factorft thermal voltageif inversion level of the transistor defined as,where is the normalization current.if> 1 strong inversion.s fI I i LWnC Itox s22fm LWC n IIIitox SSDf22fm ID: saturation current IS: normalization current n: slope factor t mD dngI i+ +21 1 10-210-110010110210310-210-10410() theory (n=1.35)( )simulation(o o o o o o) experimentt mDgIi10 WIMISI Nor malizedCur r ent Tr ansconduct ance- t o- Cur r ent Rat ioAnalog and Mixed-Signal Center, TAMUThe intrinsic cutoff frequency ( )221 1 2Lfi f ftof o Tpmf + 10-210-110010110210310410-210-1100101102103idffTo Drain-to-source saturation voltage ( ) 4 1 1 + + ftDSsatiVf 10-210-1100101102103104100101102103id WIMISI WI MISI VDSsattAnalog and Mixed-Signal Center, TAMUCorrelation Between Junction Capacitance (CJ) and Frequency ResponseParasitic capacitance GBW/fT

CJ CJ W LDIF TDIFoxfGBWLLCJ C2CLCJLDIFWCJWLCLCGBWfox T2Correlation Between Area and Frequency Response Analog and Mixed-Signal Center, TAMU+VO-CLIBIAS=IC+VI-CL+VO-IBIAS=ID+VI-t Cm1Ig( )

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+ + d t Dmi 1 1 n2 1IgtvoVAA ( )

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+ + d tvoi 1 1 n2 VAAtCICL 21GBW ( )

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+ + d tDi 1 1 n2 ICL 21GBW21fT( ) 1 i 1 221fd T +tCEsatV6 to 8( ) 4 1 i 1VdtDSsat+ + BIPOLAR MOSTr ansconduct ance- t o- cur r ent - r at io(gm/ ID)DCGain(Avo)Gain- Bandwidt hPr oduct (GBW)I nt r insicCut of fFr equency(fT)MinimumOut putVolt age(VO)DCCir cuitLow volt age (LV) powersupply cir cuitdesign t echniques ar e addr essed in t hist ut or ial.I n par t icular :(i) I nt r oduct ion; (ii) Tr ansist ormodels capable t o pr ovide per f or mance and powerconsumpt ion t r adeof f s; (iii)Lowvolt ageimplement at iont echniques,suchas f loat ing gat es, self -cascode, low volt age cur r ent -mir r or s and bulk dr iven;(iv) Basic building blocks notinvolving cascode st r uct ur es, and(v) LV cir cuitimplement at ions examples.Low Volt age Analog Cir cuitDesign Techniques: RoadmapAnalog and Mixed-Signal Center, TAMU(a) Layout (b) Schematic Symbol(c) Equivalent CircuitPoly IPoly IIN DiffusionMetalVG1VG2VG3SDVG1VG2VGnCG1CG2CGnCFGBCFGSCFGDVG1VG2VGnFloat ing Gat e Tr ansist or sThe floating gate voltage VF ,assuming that the initial charge QFin the floating gate is zero,,is described by:VF= w0V0+ w1V1+ w2V2+ .. + wnVnWhere wi = Ci/CTOTCTOT = C0 + C1+ C2+.+CnFloating Gate MOS Tr ansistor sCG (control Gate)Poly - IPoly - IIDSCO = Cgs + Cgb + CgdAssuming Cg >> Cgd,Cgb,an approximate IDS can be obtained:IDS=Koeff [( VCGS-VT,eff)VDS-CT VDS2/2Cg] ohmicIDS =Kseff ( VCGS-VT,eff)2saturationCgWhere:VT,eff =VTCO - QFG/CgKoeff = Kp(Cg/CT)(W/L), Kseff =Kp(Cg/CT)2(W/L),CT= CO + CgWhat is the effect of the FG on the tr ansconductance and the output conductance, in the satur ation r egion ?gm = ( 2K2eff IDS)2=Cg gcm/CTgo = gco + Cgd gm/CgWher e gcm and gco are the conventional transconductance and the output conductance of the conventional MOS tr ansistor .Thus, the FGT has a smallertr ansconductance and a lar geroutput conductance than conventionalMOS tr ansistorAnalog and Mixed-Signal Center, TAMUWhatis a Self -Cascode Composit e Tr ansist or ?M2M1W/Lm W/LGDSX(a) Self-Cascode Composite NMOS Transistor(b) Equivalent Simple TransistorIn practical cases, for optimal operation the W/L ratio of M2 should be larger than that of M1, i.e. m>1. The 2-transistor structure can be treated as a composite transistor, which hasa much larger effective channel length (thus lower output conductance). DGSThe lower transistor M1 is equivalent to a resistor, but this resistor is input dependent..The effective transconductance of the composite transistor is approximatelyequal to the transconctance of M1: gm-eff =gm2/m=gm1EquivalentTr ansist orPar amet er( )2212T X GSV V V i bX X T GSV V V V i

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211 1bFor the composite transistor work in saturation region, we know M2 shouldin saturation and M1 is in linear region. Thus, we can write equations for these two transistors as:Solvingwe can obtain:1i( )21 21 2221T GSV V i +b bb bFrom (3), we have1 21 2b bb bb+eqIf1 2b b m2 1111b b b++m mmeq1b b > meqComment s on VDSATBecause transistor M1 always operates in linear region while the toptransistor operates in saturation or linear region. Voltage between the sourceanddrainterminalof M1 issosmall thatthereisnodiscernable VDSATdifference in both the composite and simple transistors. Thus,self-cascodestructure can be used in low voltage applications.The operating voltage of a regular cascode circuit is much higher than that of a single transistor. This characteristic makes regular cascode circuit not suitablefor low voltage applications. 1 2 2 1 2 M D M DSAT M DS M DSAT eq DSATR I V V V V + + ( )LWV V CRT GS OXMm11whereReferences1. C. Galup-Montoro, etc., Series-Parallel Association of FETs for High Gain and High Frequency Applications, IEEE JSSC, Sept. 19942. D. Ceuster, etc., Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors, Electronics Letters, Feb. 19963. P. Furth, H. Ommani, A 500-nW Floating-Gate Amplifier with Programmable Gain, IEEE 19994. I. Fujimori, T. Sugimoto, A 1.5V, 4.1mW Dual-Channel Audio Delta-Sigma D/A Converter, IEEE JSSC, Dec. 19985. Personal note from Dr. Ugur Cilingiroglu6. Yunchu Li, examples and SPICE tables7. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, An MOS transistor model for analog circuit design, IEEE J. Solid-State Circuits, vol. 33, No. 10, pp 1510-1519, Oct. 1998IinMm M1McIoutVcasM2Iout VrefAactIinM1 M2IoutIin VrefM1MmMcPotential LV Current-MirrorsGoals: To reduce the input impedance and to increase the outputGoals: To reduce the input impedance and to increase the output impedance, impedance,while keeping the voltage operation while keeping the voltage operationIoutVrefIinMcMmM1M2VmirrorIoutIinM1 M3M2M4XIoutM1 M3IBIBM2VcasIinIoutIinM1M3IBIBM2M4M5VshiftIoutIinM1M2IoutIinM1 M2VddIB1M3 M4IB2IoutM1 M2IinROBAFBLV CURRENT-SOURCEA conceptual Schematic of the low voltage current source.(a) Current source representation(b) ArchitectureddVXYZA +1M2MIBIS 0RB 0R(a)IS 0RxV(b)Analog and Mixed-Signal Center (AMSC) TAMUHow can we obtain a large impedance and low head room for the tail current used in a differential pair ?) g / g A ) g g /( g A 1 ( 2 o) oB 1 o o 1 mos2 o 2 m ooB1 o 1 m ogg g /( A g 1R + ++ +where ( )2 mg1 mg( )2 o 1 og g ,are the transconductance and output conductance of( )2 1M M ,respectively.oA is the DC gain of the error amplifierAand ( )oB oBR g is the outputconductance (resistance) of the reference current sourceBI .Assuming that1 mg2 mg and1 og2 og , equation (1) can be simplified as:oB osR R Note that the resistance is negative and is equal to the resistance of the reference source .BI4 o 3 o4 mosg ggR (1)(2)(3)Analog and Mixed-Signal Center (AMSC) TAMUddVXYZ1M2MoIS 0R4M3MbVBIDIVCurrent Ref. Error Amplifier AssVFull implementation of the LV current source.Analog and Mixed-Signal Center (AMSC) TAMUddVXYZA +1M2MIBIS 0RB 0R(a)Measured output current of the simple (curve A) and LV (Curve B) current source.Analog and Mixed-Signal Center (AMSC) TAMUBulk-Driven MOS Transistor Characteristics IDvs. VBSor VGSof bulk-driven and conventional gate-driven MOS transistorsDrain CurrentGate-Source or Bulk-Source Voltage-3V -1.5V 0V 1.5V 3V0mA2mA4mA6mA8mABulk-Source DrivenGate-Source DrivenID1.5VVGSVBSOverhead of Bulk-Driven MOS TransistorsThe bulk-driven amplifier is more suitable for low voltage operation. Please notice that the maximum allowable voltage at Vx is VDIODE. M1Ib1VinVoutM1Ib1VinM2Ib2M2Ib2VinVoutVb VbVxVyVdd Vdd-Vss -VssSRVX, Swing range of VxSwing range of VyVdsat,M1Vdsat,Ib1Vdsat,Ib1VGS,M2SRVX=Vsup-Vdsat,Ib1-Vdsat,M1SRVY=Vsup-Vdsat,Ib1-VGS,M2= Vsup-Vdsat,Ib1-Vdsat,M2-VT(a)(b)Advantages of Bulk-Driven MOS Transistors Thedepletioncharacteristicallowszero,negative,andevensmall positive values of bias voltage to achieve the desired dc current. This canleadtolargerinputcommonmodevoltagerangeandvoltage swingthatcouldnototherwisebeachievedatlowpowersupply voltages. ( Please refer the following example in this section and bulk-driven differential pair discussed in following sections ) Wecanusetheconventionalgatetomodulatethebulk-driven MOS transistor. ExampleAssume for the low voltage amplifiers, power supply voltage isVsup= Vdd+|Vss|