logical minimization of multilevel coded functions

Logical minimization of multilevel coded functions

Mir M. Mirsalehi and Thomas K. Gaylord

Discrete numerical values in digital processing systems may be encoded in two-level (binary) or higher-level(multilevel) representations. Multilevel coding can produce smaller and more efficient processors. In truth-table lookup processing, the number of entries (reference patterns) can be reduced using multilevel coding.Since parallel-input/parallel-output optical truth-table lookup processors can be constructed based onholographic content-addressable memories, it is essential to know the minimum storage required to imple-ment various functions. A new simple method for reducing multivalued functions is presented. Thismethod is based on an extension of the Quine-McCluskey minimization method used for binary logicfunctions. This minimization method is then applied to the truth tables representing (1) modified signed-digit addition, (2) residue addition, and (3) residue multiplication. A programmable logic array gateconfiguration for the modified signed-digit adder is presented.

1. Introduction

Many useful digital operations are implemented incomputers by converting them into a series of simpleroperations and then mapping these into hardware.For example, the addition of two n-bit numbers can beimplemented by one half-adder and n - 1 full-addercircuits. The serial nature of this type of implementa-tion results in decreased speed of computation, espe-cially as the number of bits is increased. Carry-saveand pipelining techniques",2can be used to increase thespeed and throughput of digital computers. Anotherapproach is to list all possible inputs together withtheir corresponding outputs. Such a list is called atruth table. The numbers in this list are usually repre-sented in binary form. Direct implementation oftruth tables provides faster computation, since theentire operation is performed in a single step and not asa series of sequential steps. However, the amount ofhardware required to implement a truth table can beconsiderable, and thus this technique is not a commoncomputer architecture. Recent advances in varioustechnologies and the growing need for faster computa-tion have stimulated new interest in this type of imple-mentation. A truth table can be realized with a memo-ry or with logic gates as a programmable logic array(PLA). The most straightforward memory imple-

When this work was done, both authors were with Georgia Insti-tute of Technology, School of Electrical Engineering, Atlanta, Geor-gia 30332. Mir M. Marsalehi is now with the University of Alabamain Huntsville, Department of Electrical and Computer Engineering,Huntsville, Alabama 35899.

Received 30 March 1986.0003-6935/86/183078-00$02.00/0.© 1986 Optical Society of America.

mentation of a truth table may be achieved by storageof the entire table in a direct or location-addressablememory (LAM) such as an electronic read-only memo-ry (ROM). In this type of system, the inputs representthe address of the answer. Less storage is generallyrequired when a truth table is implemented using acontent-addressable memory (CAM). In a CAM, theinput represents the data, and the output is all theaddresses where those data occur. These addressesare provided simultaneously in parallel. The content-addressable memories are of great interest because oftheir storage efficiency and capability of parallel pro-cessing. Content-addressable memories can be imple-mented by optical or electronic systems. An exampleof an optical holographic CAM is described in Ref. 3.In this system, after the search data are loaded into thespatial light modulator, the entire holographic memo-ry can be searched in an amount of time (possibly 10ns) equal to the sum of the propagation time throughthe system and detection time. An example of anelectronic CAM is described in Ref. 4. This system is a4-kbit CAM fabricated with CMOS technology. It hasa 140-ns minimum cycle time and 250-mW power dis-sipation at 5-MHz operation.

A major issue in all methods of direct implementa-tion of truth tables is the reduction of the size of thetables without discarding essential information. Thisreduction is needed to make direct implementationpractical. Truth tables may be reduced by one or acombination of the following techniques: (1) using theresidue number system; (2) representing the data incoding levels higher than binary; and (3) applying logi-cal minimization techniques. These are described inprevious publications.35-7 The purpose of the presentpaper is (1) to describe a new extended version of the

3078 APPLIED-OPTICS / Vol. 25, No. 18 / 15 September 1986

Quine-McCluskey method for minimization of multi-level-coded truth tables, (2) to provide results ob-tained by applying this method to the truth tables forsome practical operations, and (3) to present equiva-lent logic gate diagrams for implementations of theseoperations.

II. Logical Minimization of Truth Tables

A. Introduction

Each entry in the truth table of a digital functionprovides the output of that function for one possiblecombination of the input bits. Equivalently, a func-tion can be defined by listing the input bit combina-tions that produce a 1 in each output bit. These inputsare called minterms in Boolean algebra terminology orreference patterns in pattern recognition terminology.In this method, a separate table is prepared for eachoutput bit. These tables are known as the unity-resulttruth tables. For data processing, the input pattern iscompared with all the reference patterns in each table.If a match with one of the reference patterns occurs,that output bit is designated as a 1; otherwise, it isdesignated as a 0. Since the present work deals withthis type of implementation, the minimization of uni-ty-result tables is explained here. The techniquesused, however, are general and can be used for othertypes of truth table representation.

As an illustrative example, the simple case of addi-tion of two 2-bit numbers is considered here. In thisoperation, there are eight input bit combinations thatproduce a 1 in the first (least significant) bit of theoutput: 0001 (corresponding to 00 + 01), 0011, 0100,0110, 1001, 1011, 1100, and 1110. Similarly, eightreference patterns produce a 1 in the second bit and sixreference patterns produce a 1 in the third (most sig-nificant) bit of the output. Therefore, this operationcan be represented by three unity-result tables havinga total of 8 + 8 + 6 = 22 reference patterns.

Two reference patterns in a unity-result table can becombined if they are identical in all their bits exceptone. For example, the patterns 1001 and 1011 can becombined as 1OX1, where X represents a don't-carebit, meaning that bit can be either 0 or 1. This resultsin a reduction of the number of reference patterns.For example, the eight reference patterns correspond-ing to the first output bit of the 2-bit addition can bereduced to two patterns: X1X0 and XOX1. Similar-ly, the number of reference patterns corresponding tothe second and third bits of the output can be de-creased from 8 to 6 and from 6 to 3, respectively.Therefore, the total number of reference patterns for2-bit addition can be reduced from 22 to 2 + 6 + 3 = 11.

B. Logical Minimization Methods

A number of methods exist for the reduction ofbinary truth tables. Two well-known methods are theKarnaugh map and the Quine-McCluskey method.8

The Karnaugh map is a graphical technique in whichthe possible combinations of the patterns can be easilyvisualized. However, it becomes impractical for func-

tions of more than 5 or 6 input bits. The Quine-McCluskey method is more powerful and can handlemuch larger size tables. It is a two-step procedure.First, using a tabular method, all prime implicants ofthe function are obtained. A prime implicant is areduced reference pattern that cannot be reduced fur-ther. For example, considering the eight referencepatterns mentioned in Sec. II.A, XOX1 is a prime im-plicant, while 1OX1 is an implicant but not a primeimplicant. After all the prime implicants of the func-tion are determined, a systematic method is used toselect a minimum set of prime implicants that coversall the minterms of the function. This set is known asthe minimal sum set. The Quine-McCluskey tech-nique is described in more detail in Ref. 6. Othertechniques have been developed to minimize very largetruth tables through the use of efficient computer pro-grams.8 The description of these techniques is beyondthe scope of the present paper.

Although data in most digital systems are in binaryform, this is not essential. The data can be coded inother forms. It has been shown that using higher-levelcoding may result in more reduction. 7 This is espe-cially significant for the cases where the residue num-ber system is used and the moduli are expressible as pn,wherep is a prime number and n is an integer (>1). Inthese cases, significant reduction can be achieved if p-level coding is used. This is a type of multilevel cod-ing. An example of multilevel coding is ternary cod-ing, where three values (e.g., 0, 1, 2 or -1, 0, 1) areallowed for each digit. The minimization of multileveltables requires a type of logic different from the com-monly used binary logic. The appropriate logic,known as multiple-valued logic, is based on Post alge-bra 9 and is currently an active area of research. 1 0 -'3

During the past two decades, a number of methodshave been developed for the minimization of multival-ued functions. Among these are the methods devel-oped by Allen and Givone,14"15 Su and Cheung,16"17 andSmith.18 In the next section, a new and simple methodfor reducing multivalued functions is presented. Thismethod is based on an extension of the Quine-McClus-key technique used for binary functions.

C. Extended Quine-McCluskey Technique

In multiple-valued logic, reference patterns can becombined in several ways. To introduce the notationused in the present work, an example of logical reduc-tion is presented. Consider the three reference pat-terns 120, 121, and 122 in ternary logic. These termscan be combined into a single term. The reduced termcan be written as 12X, where X (herein referred to as acomplete-don't-care digit) represents a digit that cantake any possible value (in this case 0, 1, and 2). If oneof the above terms is absent, the other two can still becombined. For example, the terms 120 and 121 can becombined into one term. The reduced term is writtenas 12X0 1, where Xoj (herein referred to as a partial-don't-care digit) represents a digit with possible valuesof 0 and 1, but not 2.

15 September 1986 / Vol. 25, No. 18 / APPLIED OPTICS 3079

Reference Paterns

0 1 0 1

0 1 0 1 1 /

0 1 0 1 2

Fig. 1. Flow chart of procedure for obtaining the prime implicantsof a multivalued function. The steps labeled on the chart refer to

the steps as listed in Sec. II.C.1.

The extended Quine-McCluskey method, like theoriginal method, consists of two procedures: (1) deriv-ing all prime implicants and (2) deriving a minimalsum. The first procedure is a modified version of theprocedure used for binary logic functions. This modi-fied procedure is described below.

First List

0 1 0 0 1 0 2 0 0 1

0 1 2 0 1 0 1 0 1 10 2 0 0 1 0 1 0 1 2/0 2 0 1 1 0 1 2 0 10 2 2 0 1 0 2 0 1 1/

0 2 20 2 / 0 2 2 0 1 I I 0 0 1 0 2 2 0 2 I 1 0 0 2 11 0 0 1/11 0 1 2/ 1 1 0 21I1 2 0 1

1 1 211 1 1 0 1 2/1 2 0 1 1 I 1 2 0 1/

1 2 0 1/ 11 2 0 1 1 /1 2 2 1 1 1 2 0 2 1 2 2 1 2

I 1 2 1 1

1 2 2 1 1

1 2 2 1 2

Second List

OX,0 0 1 1

a 1I0 X 1 0 1 X0 , 1 /0lXI 0 1

02I0XO 10 011/

01011

0 2 OX0, 1 1

0 2X02 0 1 0 1 0 1X,

OX,20 1 1 1OX0 2 0 1 10 2 2 0 X1 1 0 OX,2

X 1 0 1 2

02°1/

1 1 0 ,X 2X2 0 1 2

1 2 0 1 X 2 /

Third List

OX 2 0XI, 1

X 2X0 2 1

XO 1 X0 2 0 1

1 2 X02 1 X,2

1 1 2X, 1

1 2X02 1 1 11 2 X02 1 2 /

1X 2 2 1 112 2 1 X 2

Fig. 2. Example of determining all prime implicants in the extend-ed Quine-McCluskey method.

1. Derivation of All Prime ImplicantsThe procedure for finding all prime implicants of a

multivalued function is described in this section. Aflow chart of the procedure is shown in Fig. 1. Thesteps labeled on the flow chart refer to the steps of theprocedure as listed here.

Step 1: Make a list of all terms (reference patterns)divided into groups according to the number of non-zero digits present in the terms. Only uniquely de-fined digits with values different from zero (e.g., -1, 1,2, etc.) are treated as nonzero digits. Don't-care digitsare not counted as nonzero digits. The group at thetop of the list should include all the terms that have theleast number of nonzero digits. Each subsequentgroup proceeding down the list should include all theterms that have one more nonzero digit than the groupabove it. The groups are labeled by the group numbern, the number of nonzero digits in each of their pat-terns. For example, in the first list of Fig. 2, the groupnumbers are n = 2 (the group at the top), 3, 4, and 5(the group at the bottom). Using the systematic pro-cedure described in steps 2-10, all possible ways ofcombining the terms are checked, and a new list isproduced.

Step 2: Let i be one less than the group number forthe group at the top of the list. For example, for thefirst list of Fig. 2, i = 1.

Step 3: If both groups with group numbers i and i+ 1 exist, go to step 4; otherwise, go to step 5.

Step 4: Compare each term in group i with eachterm in group i + 1. If two terms differ by only onedigit, combine them into one term. This occurs whenthe digit that differs is a zero in the term from group iand is a nonzero digit in the term from group i + 1. For

3080 APPLIED OPTICS / Vol. 25, No. 18 / 15 September 1986

example, the terms 01201 and 01211 can be combinedinto 012X0 11.

Step 5: If group i exists, go to step 6; otherwise, goto Step 7.

Step 6: Compare all possible pairs of terms withingroup i. If two patterns differ in only one digit loca-tion by having different don't-care digits, combinethem into one term. For example, the terms 13X010and 13X120 can be combined into 13X0 120.

Step 7: If group i + 1 exists go to step 8; otherwise,go to step 9.

Step 8: Compare all possible pairs of terms withingroup i + 1. If two patterns differ in only one digitlocation by having different nonzero digits, combinethem into one term. For example, the terms 01001and 02001 can be combined into OX12001.

Step 9: Write the new terms (if any) obtained insteps 4, 6, and 8 as the elements of group i of the newlist and put a check mark beside the combined terms inthe old list. If the same new term appears as a result ofmore than one combination, do not repeat it in the newlist.

Step 10: If group i is not the last group of the oldlist, increment i by one and go back to step 3. If group iis the last group of the old list, go to step 11.

Step 11: If the new list is not empty, repeat steps2-10 on this new list (which would then become the oldlist). If the new list is empty, the procedure is fin-ished, and the terms in the created lists that do nothave check marks make a complete set of all primeimplicants.

As an example, all prime implicants of a particularset of ternary-coded reference patterns are found inFig. 2.

It should be mentioned that, in the above procedure,the patterns could have been categorized according tothe number of digits that are not k, where k can be anypossible value of a digit. Categorizing according tononzero digits has no inherent advantage over otherpossible categorizations. The comparison betweenthe elements of the groups are then made using similarsteps as described above, where zero is replaced by thatparticular digit value in all the statements. Regard-less of what digit value has been used in the procedure,the same list of prime implicants will be obtained.

2. Derivation of a Minimal SumThe prime implicants derived by the above proce-

dure usually cover the minterms in an overlappingmanner. That is, some of the minterms are covered bymore than one prime implicant. The next step is tochoose a set of prime implicants that covers all theminterms with the minimum cost. The cost parame-ter depends on the technology used for implementa-tion, and it is usually either the number of primeimplicants in the set or the total number of bits in theset. If the number of prime implicants is minimized,the result is called a sloppy minimal sum. If the mini-mization of the number of prime implicants is accom-panied by minimization of the total number of bits, theresult is called an absolute minimal sum. The proce-

dure for derivation of a minimal sum described here isexactly the same as that used for binary logic. In fact,this procedure, known as the set covering problem,'9 isnot limited to logic design and has other applications.

To derive a sloppy or absolute minimal sum, first, atable of choice is constructed. The rows of this tablecorrespond to the prime implicants (listed at the left),and the columns correspond to the minterms (listed atthe top) as shown in Fig. 3(a). Each prime implicantrow is marked in the minterm columns covered by thatprime implicant. This illustrates how the entries inthe initial truth table are covered by the prime impli-cants.

From the table of choice, a sloppy or absolute mini-mal sum may be obtained using the steps listed below.Note that the sloppy and absolute minimal sums maynot be unique.

Step 1: Select essential rows. These are the rowsthat uniquely cover some of the columns, and theymust be selected to cover those columns. The primeimplicants associated with these rows are called essen-tial prime implicants. The essential rows and all col-umns that contain marks in these rows should be elimi-nated from the table of choice.

Step 2: Eliminate dominated rows. One row dom-inates a second row if the first row has marks in allcolumns in which the second row has marks.

For an absolute minimal sum, the prime implicantassociated with the dominated row is eliminated fromthe table of choice only if the dominating row has thesame or fewer variables in its prime implicant.

For a sloppy minimal sum, a dominated row is al-ways eliminated regardless of the number of variablesin its prime implicant.

Step 3: Eliminate dominating columns. Similar-ly, one column dominates a second column if the firstcolumn has marks in all rows in which the secondcolumn has marks. The minterms associated with thedominating columns should be eliminated from thetable of choice.

Step 4: Repeat steps 1-3 until all columns areeliminated. The resulting sum of all essential rowprime implicants represents a sloppy or absolute mini-mal sum.

Figure 3 shows the results obtained by applying theabove procedure to the table of choice consisting of theminterms and the prime implicants for the examplecase.

There are cases when the above procedure is unableto eliminate all columns. The remaining table, whichcontains at least two marks in each column, is called acyclic table. In this case, the tabular method using arecursive branch-and-bound algorithm presented byMuroga8 may be used to obtain either a sloppy or anabsolute minimal sum.

III. Implementations

A. Hardware Logic Gates

A truth table may be directly implemented withlogic gates. Each reduced reference pattern (prime


0 0 0 N N N 0 0 0 N N 0 0 N NI

XX~~X

X X

X X

X X

X X

X X

X X

X X

X X X X

X X X X

X X X X

X X X X

* 0 0 0 0 0

(a)

0 0 0 N 0 0 0 0s 0 N N0 0 0 0 0 … OO_

0 1 0 1 X12

1 1 0 X12

X,, 1I0 1 2

1 1 XI, 2

* 1 1 2 X, 1

* OX12 0X0, 1°OX2X0 2 0°

X X0 0 10I'1 X02 1

(C)

0 1 0 1 X2

1 1 0 0 X12X, 1 0 1 2

XI,2 0 1 1

1 1 0 X 2

1X 2 0 1 2

1 1 2 XI, 1

1X 2 2 1 1

OX12 O X

0, 1

OX X2 0 1

X0 1 X02 1

N - _ - N N -0 N 0 0 0 0 N_ 0 .__

(d)

N- - N N0 N 0 0 00 0 - =

1 1 X 2* X 1 0 1 2

1 1 OX0, 2

* XOI 1 X02 0 1

(g)

12

I I 0 0 X12C1 1 X0 1 2 L]

(h)

) * 1 1 OX0,2

(i)

Absolute Minimal Sum = 0220X12, 12X021X12, 112X0 11, OX12OX0 11 X 11012, X 11Xo2 o1, 11OX0 ,21

()

Fig. 3. Example of deriving a minimal sum for the truth table provided in Fig. 2: (a) constructing the table of choice; (b) table reduced by re-moving essential rows; (c) table reduced by eliminating dominated rows; (d) table reduced by eliminating dominating columns; (e) tablereduced by removing essential rows; (f) table reduced by eliminating dominated rows; (g) table reduced by eliminating dominating columns;

(h) table reduced by removing essential rows; (i) table reduced by removing dominated row; (j) absolute minimal sum set obtained.

implicant) can be realized with an AND gate. If thepatterns are binary coded, the inputs to the AND gateare determined as follows. If a bit in the referencepattern is a 1, the corresponding input line is directlyconnected to the AND gate. If it is a 0, the input bit iscomplemented before connecting it to the gate. If it isa don't care bit, the input bit is not connected. Forexample, the realization of pattern OX1 is shown in

Fig. 4(a). The input bits are numbered starting withthe least significant bit a. If the input pattern(a3a2aiao) is identical to the reference pattern (lOX1),the output voltage would be high, representing a 1. Ifthe input pattern differs from 1OXi by one or morebits, the output voltage would be low, representing a 0.

If higher levels of coding are used, each digit wouldhave more than two possible values. One technique


o 1 0 1 X,2* 0 2 2 O X12

1 1 0 O X,2

X01 0 1 2

X,, 2 0 1 1

1 1 0XI,2

1XI, 0 1 2

1 1 2X0 , 1

1X12 2 1 1

O X,2 0 X0, 1

°X2X02 1X01I X02 1

* 1 2 X0 2 I XI,

0 0 0 N 0 0 0 N N

)

(b)

0 1 0 1 xI'

1 1 0 O X,2XI, 1 0 1 2

1 1 0X, 2

1 1 2XI, 1

OX O0Xo 1OX X 0X0 1° X12X 02 1

X0 1 X02 0 1

-

0 0 - - -

a 1 0 1 X12

1 1 0 X12X1 0 1 2

1 1 0 X 2

O XI2 X0 2 0 1

XI 1 X0 2 0 1

)

)

(e)

1 1 0O X 2

X0 1 0 1 2

1 1 XI1 2

X0 1 X02 0 1

Wif

V G. 11, 5_1

XX

XI I

a3

a1 -

a0

(a) (b)

for representing a p-level digit is to use p input lines.Each value of that digit is then realized by raising thevoltage of the corresponding line high. This allows asimple realization of the different types of don't-caredigits. A partial-don't-care can be realized by raisingthe voltage high of the lines corresponding to the al-lowed values of that digit. A reference pattern canthen be identified by the output of an AND gate. Foreach digit, the inputs to the AND gate are the input linesthat correspond to the values of that digit in the refer-ence pattern. If a digit has a complete-don't-carevalue, the corresponding input lines are not connected.For example, the realization of the ternary pattern2X1X02 is shown in Fig. 4(b). If the input pattern isidentical to the above reference pattern, the outputvoltage would be high, indicating the presence of thatpattern.

As described above, each reference pattern is identi-fied with an AND gate. To implement the entire func-tion, the outputs of these AND gates should be logicallysummed by an OR gate. This realization is known asthree-level logic, the levels corresponding to NOT, AND,and OR operations. Electronic integrated circuits forthis type of implementation are commercially avail-able as programmable logic arrays.

B. Optical Implementation

The information in a truth table can be stored asholograms in a recording medium such as a photore-fractive crystal. Each reference pattern is coded as anumber of transparent or opaque spots in a spatiallight modulator which is used as the object in a Fouriertransform hologram configuration. For recording, areference beam incident at a particular angle interfereswith the object beam. The recording process is re-peated for all the reference patterns using differentreference beam angles for each case. During the read-ing process, the input pattern is compared with all thereference patterns recorded for each output digit. If itmatches any of them, the corresponding value is as-signed to that output digit. This system is basically anoptical content-addressable memory, and it exhibits anumber of the advantages of optics. Among these isthe capability for parallel processing. The lack ofangular selectivity in the direction perpendicular tothe recording plane of incidence for volume holo-grams20 allows an entire array of parallel inputs to be

-' Fig. 4. Examples of realizing thereference patterns by logic gates:(a) binary coded pattern (lOX1);(b) ternary coded pattern(2X1X02). The digit numbersstart from the least significant

digit ao.

processed simultaneously by the same set of holo-graphic recordings. More detailed information aboutthis type of processing may be found in Ref. 7.

IV. Example Applications

A. Modified Signed-Digit (MSD) Numbers

One disadvantage of commonly used weighted num-ber systems, such as the decimal and binary systems, isthe strong interdigit dependence. This results in car-ry propagation in both addition and multiplication.Hence the calculations need to be performed serially,i.e., bit by bit. If a number system has no interdigitdependency or has a weak dependency, the calcula-tions may be performed in parallel, i.e., all digits calcu-lated simultaneously. The residue number system isan example of a system with no interdigit dependency,and the modified signed-digit number system is anexample of a system with weak interdigit dependency.The modified signed-digit number system is a radix 2system in which three values are allowed for each digit:1; 0; and-1 (or 1). For example, the decimal number 5can be represented as (1,-1,0,1) or (1101)MSD, since(1101)MSD = 1 X 20 + 0 X 21 - 1 X 22 + 1 X 23 = (5)10.The negative of a MSD positive number can be ob-tained by complementing each digit of that number.The complement of 1 is -1, of -1 is 1, and of 0 is 0.Thus 1 - 1, 1 - 1, and 0 - 0. For example, thedecimal number -5 can be represented by (110)MSD.A disadvantage of MSD representation is the redun-dancy. That is, there is more than one representationfor each number. For example, the decimal number 5can also be represented as (101)MSD, (1011)MSD,(llOll)MSD, etc. However, this redundancy can beused to limit the carry propagation only to the nextmore significant digit. This, in turn, makes it possibleto perform an operation in parallel. For example, theaddition and subtraction of two MSD numbers of anyword length can be done fully in parallel. The sche-matic diagram of a system that performs the additionof MSD numbers has been presented by Drake et al. 2 1

Their approach is shown in Fig. 5. In this figure, thetwo input numbers are X = (x4 x3 x2 xzxo) and Y =(y4y3y2ylyo), and the output is Z = (Z5Z4 z3 z2 z1zo). Theblocks labeled with W, Y, W', and T1 perform theweight and transfer operations. The truth tables ofthese operations are shown in Table I. In Fig. 5, the


a3 I 102-

a2 � a2 -

al Il1

0

12 -

Table I. Truth Tables Corresponding to the Transfer (Tand 1) andWeight (Wand W) Functions Used In the MSD Adder

X Y T W T1WI

1_ 1 1 0 1 0

1 0 1 0 1

1 0 0 0 0

o 0 * 1 0 1

o 0 0 0 0 0

o 1 1 1 0 1

1o o o1 0* 0 0 0

1 0 1 1 0 1

1 1 1 0 1 0

part of the diagram that affects one particular outputdigit z3 has been separated from the rest of the diagramby dashed lines. It can be seen that Z3 is only affectedby xi, y1, X2, Y2, x3, and y3. In general, the nth outputdigit is affected by six input digits: Xn-2Yn-2, Xn-i )Yn,xn, and Yn. A truth table can be made with the abovevariables as the inputs and Zn as the output. Sinceeach digit has three possible values (1, 0, and -1), thistable will have 36 = 729 entries. It turns out that thenumber of input patterns that produce a 1 in theoutput digit is 183. Similarly, 183 patterns produce anoutput of -1. The remaining 363 patterns produce a0. For the types of implementation described in Sec.III, it is only required to implement that part of thetruth table that produces a nonzero value at the outputdigit. A value of zero can then be assigned to theoutput if the output is found to be neither 1 nor -1.The size of the system can be reduced further by com-bining the reference patterns using the logical minimi-zation technique described in Sec. II. As a result, thenumber of patterns for each case is reduced from 183 toonly 28. Thus the output digit can be obtained bycomparing the input patterns with a total of 56 re-duced reference patterns. The list of the reducedreference patterns that produce a 1 in the output digitis provided in Table II, and the corresponding gate

Fig. 5. Modified signed-digit (MSD) adder array for two five-digitternary numbers (from Ref. 21).

implementation is shown in Fig. 6. The negation of 1,0, and 1 give X01, Xi,, and X1o, respectively. Allthirty-six signal lines are shown in the figure for com-pleteness. Notice, however, that eighteen lines (xnand yn 1, X 10, X 01; xn- 1 and Yn-i = X10, X1,; Xn-2 andYn-2 = 1, 0, X10, and Xi,) are not needed in this imple-mentation. The reference patterns that produce a-1in the output digit can be obtained from the list inTable II simply by converting the 1's to -1's and the-1's to 1's. As mentioned above, an output of zeromay be obtained by detecting the absence of a 1 and a-1 in the output. This can be realized by a NOR gatewhose two inputs are connected to the Zn = 1 and Zn =-1 lines. By repeating the above procedure for otherdigits, the addition of two modified signed-digit num-bers can be obtained fully in parallel. The time re-quired for the calculation will then be independent ofthe word length. From Fig. 5, it is clear that the firsttwo output digits (zo and z) and the last output digit(Z5 in the figure) depend on less than six input digits.Therefore, the corresponding truth tables have fewerentries, and the gate diagrams are simpler. Only tworeference patterns produce a 1 in the output digit zo.These are y0x0 = 10 and yoxo = 01. The referencepatterns that produce a 1 in the other two output digits(Z, and ZN) are listed in Tables III and IV. The gatediagrams corresponding to the above special cases are

Table II. Reduced Reference Patterns that Produce a 1 In the Output Digit z (n Pd 0, 1, N)of the MSD Addera

X11 1 X X 1 X 0 1 X 0 1 X Xi'X0 1 X 1 X XX01 O 1 Xo

1 X 0 1 X 0 X01 1 0 1 11 X X1X 1 X 0 1 0 0 1

10 X O X O 1 X X 1 0 1X01 XlX01 X-i 1 0x °01

1 1 X 0 1 X 0 1 1 0 X01 X OX0 11 1 1 1 X01 ° 1

0 1 X 11 X 0 X01 X 0 1 1 0 1 X X0 Xi, 0 1 0 1

0 X 1 X X1 1 1 Xi1XO X 0 0X01X1 11X001X011xi1 X01

OO X 0 X X 01 XXl, 1 1 0 0 1 0, 1 x 01 o1X1X01X01

a Each pattern consists of the effective digits of the two input numbers IX and Y and isexpressible as yy,.1Yn.2xnXn1xn.2. The digit number of the output starts with n = 0 for theleast significant digit and ends with n = N for the most significant digit


Fig. 6. Logical gate implementation of the truth table corresponding to the output digit zn (n = 0, 1, N) in the MSD adder.

Table IlIl. Reduced Reference Patterns that Produce a 1 in the OutputDigit z of the MSD Adder-

0 1 1 1 1 0 1

0 0 1 0 OX01 01

o i T 1 0 1 0 X0 1

1 0 0 0 X-,Xo X- 1

i Xi,~1 1 11X1 1 0 1 X,, 1 XX 0 1

a Each pattern consists of the effective

digits of the two input numbers X and

Y) and is expressible as y1y0x1x0.

shown in Figs. 7-9. Again the lists of the referencepatterns that produce a -1 in the output and thecorresponding gate diagrams can be obtained by con-verting the 1's to -1's and the -1's to 1's in the abovetables and figures.

B. Residue Number System

Another useful number system for parallel process-ing is the residue number system (RNS). This num-ber system has been extensively investigated during

Table IV. Reduced Reference Patterns that Produce a 1 in the LastOutput Digit ZN of the MSD Addera

1 X 1 X 1 1 X01 X

X01X 1 1 X01 01 X01

X0 1 1 X 1 X01 0X1 1

1 X X 0 1

a Each pattern consists of the

effective digits of the two input

numbers (X and Y) and is expressible

as YN-1YN-2XN-1XN-2

the last thirty years.22 23 The main advantage of theRNS is that the calculated output digits are indepen-dent of each other. As a result, the problem of carrypropagation does not occur, and an operation such asaddition or multiplication can be performed fully inparallel. This interdigit independence greatly simpli-fies the truth table representation of the operation.Choosing a set of moduli and performing an operationin the RNS result in numerous small truth tables rath-er than one very large truth table. The truth tables


-10

-1

0

I

x ~l. I-

I l 1t

Zo = 1

Fig. 7. Logical gate implementation of the truth table correspond-ing to the output digit z0 in the MSD adder.

-1

1

Fig. 8. Logical gate implementation of the truth table correspond-ing to the output digit z1 in the MSD adder.

corresponding to each modulus can be simplified indi-vidually by using logical minimization techniques. Ithas been shown7 that further reduction can beachieved if multilevel coding is used to represent thedigits of a residue number. The numbers of reducedreference patterns required to implement residue ad-dition and multiplication operations have been report-ed in Ref. 7 for moduli 2-32 and for two-level, three-level, and five-level coding. Operations of practicalinterest require large dynamic ranges. These may beachieved by choosing a number of moduli without com-mon factors. The dynamic range of the system is then

Fig. 9. Logical gate implementation of the truth table correspond-ing to the last digit of the output ZN in the MSD adder.

the product of the selected moduli. For direct imple-mentation of a function, it is often desired to select themoduli so that the total number of the reduced refer-ence patterns is minimized. The set of moduli that isoptimum in this sense can be obtained by an exhaus-tive search or by using the procedure described in Ref.5. Using this technique, a number of cases of additionand multiplication were analyzed. The results are inTable V. The numbers of required reference patternsfor these cases are significantly less than the corre-sponding numbers for the usual binary coded num-bers.

V. Summary and Discussion

Recent advances in various technologies and thegrowing need for faster computation have stimulatednew interest in direct implementation of truth tables.The major issue associated with this technique is thereduction of the sizes of the tables so that this ap-proach becomes practical. In this paper, the logicalreduction of truth tables has been explained, and a newtechnique, based on an extension of the Quine-McCluskey method, has been described for minimiz-ing multilevel coded truth tables. This method can beeasily applied to multivalued functions with smalltruth tables by hand calculation, or it can be pro-grammed on a digital computer to handle large truthtable cases.

An an example application of this technique, thetruth tables corresponding to the addition of modifiedsigned-digit numbers were minimized. As a result, thenumber of reference patterns for a general output digitwas reduced from 366 to only 56. This number ofreference patterns can be implemented optically (suchas with a holographic content-addressable memory) orelectronically (as with a programmable logic array).The gate diagrams for the latter implementation and


Table V. Optimum Sets of Moduli and Number of Required Reference Patterns N, for Implementing Some Practical Operations with a Content-Addressable Memory with Two-Level, Three-Level, and Five-Level Coding Alloweda

Operation Required Range Moduli Corresponding Coding Levels Covered Range Nr

16-bit fixed-point addition 0-65,535 3, 5, 7, 8, 11, 13 2 or 3 or 5, 3, 2, 2, 3, 5 0-120,119 286

32-bit fixed-point addition 0-4,294,967,295 5, 7, 9, 11, 13, 16, 17, 19, 23 3, 2, 3, 3, 5, 2, 3, 3, 2 0-5,354,228,879 1001

16-bit fixed-point multiplication 0-65,535 3, 5, 7, 8, 11, 13 2 or 3 or 5, 2 or 3, 2, 2, 5, 3 0-120,119 234

32-bit fixed-point multiplication 0-4,294,967,295 5, 7, 9, 11, 13, 16, 17, 19, 23 2 or 3, 2, 3, 5, 3, 2, 3, 5, 3 0-5,354,228,879 1067

a The corresponding coding level(s) shown for each modulus is (are) determined such that the number of referenceeach operation, the required range of numbers and the range of numbers covered by the selected moduli are given.

Table VI. Comparison of Number of Required Reference Patterns toPerform 16-Bit Full-Precision Addition Using Various Encoding Schemes

Without Logical Reduction:

Binary 3.65 x 1010

Binary-coded residue 694

Multilevel-coded residue 568

Modified-signed digit 5212

With Logical Reduction:

Binary 3.28 x 105

Binary-coded residue 327

Multilevel-coded residue 300

Modified-signed digit 822

the corresponding reduced reference patterns havebeen provided. Another number system suitable forparallel processing is the residue number system. Theresults of minimization of truth tables correspondingto residue addition and multiplication operations havebeen provided, and this information was used to ana-lyze some practical addition and multiplication cases.

The effect of coding schemes and logical reduction inreducing the number of reference patterns in content-addressable memories can be seen from Table VI. Inthis table, the number of reference patterns corre-sponding to 16-bit full-precision addition are providedfor different coding schemes without and with logicalreduction. The advantage of the modified signed-digit number and the residue number system over theusual binary number system is evident. The residuenumber system allows the greater reduction of a truthtable. However, it is an unweighted system, and thesize of the resulting answer is not immediately appar-ent. The modified signed-digit number system, on theother hand, is a weighted number system, and theanswer is readily convertible to binary notation. How-ever, modified signed-digit truth tables exhibit lesslogical reduction than do residue truth tables for thesame operation.

patterns is minimized. For

VI. Conclusion

It has been demonstrated that the truth tables canbe significantly reduced by using the appropriate num-ber system and coding scheme and applying logicalreduction techniques. Also, as shown in this paper,the reduced truth tables corresponding to some opera-tions of practical interest can be directly implementedwith present technologies.

This work was supported in part by a grant from theJoint Services Electronics Program and by a grantfrom the Strategic Defense Initiative Office adminis-tered through the Office of Naval Research.

References1. e.g., F. J. Hill and G. R. Peterson, Digital Systems: Hardware

Organization and Design (Wiley, New York, 1978).2. e.g., J. R. Jump and S. R. Ahuja, "Effective Pipelining of Digital

Systems," IEEE Trans. Comput. C-27, 855 (1978).3. C. C. Guest and T. K. Gaylord, "Truth-Table Look-Up Optical

Processing Utilizing Binary and Residue Arithmetic," Appl.Opt. 19, 1201 (1980).

4. T. Ogura, S-I. Yamada, and T. Nikaido, "A 4-kbit AssociativeMemory LSI," IEEE J. Solid-State Circuits SC-20,1277 (1985).

5. C. C. Guest, M. M. Mirsalehi, and T. K. Gaylord, "ResidueNumber System Truth-Table Look-Up Processing-ModuliSelection and Logical Minimization," IEEE Trans. Comput. C-33, 927 (1984).

6. T. K. Gaylord and M. M. Mirsalehi, "Truth-Table Look-UpProcessing: Number Representation, Multilevel Coding, andLogical Minimization," Opt. Eng. 25, 22 (1986).

7. M. M. Mirsalehi and T. K. Gaylord, "Truth-Table Look-UpParallel Data Processing Using an Optical Content-AddressableMemory," Appl. Opt. 25, 2277 (1986).

8. e.g., S. Muroga, Logical Design and Switching Theory (Wiley,New York, 1979).

9. E. I. Post, "Introduction to a General Theory of ElementaryPropositions," Am. J. Math. 43, 163 (1921).

10. D. C. Rine, Ed., Computer Science and Multiple- Valued Logic(North-Holland, Amsterdam, 1977).

11. See the annual issues of Proceedings, International Symposiumon Multiple- Valued Logic (IEEE, New York, 1971-1986).

12. S. L. Hurst, "Multiple-Valued Logic-Its Status and ItsFuture," IEEE Trans. Comput. C-33, 1160 (1984).

13. Special issue on Digital Optical Computing, Multiple-ValuedLogic/Digital Logic, Opt. Eng. 25, (1986).

14. C. M. Allen and D. D. Givone, "A Minimization Technique forMultiple-Valued Logic System," IEEE Trans. Comput. C-17,182 (1968).


15. C. M. Allen and D. D. Givone, "The Allen-Givone Implementa-tion Oriented Algebra," in Ref. 10, Chap. 9.

16. S. Y. H. Su and P. T. Cheung, "Computer Minimization ofMulti-Valued Switching Functions," IEEE Trans. Comput. C-21, 995 (1972).

17. S. Y. H. Su and P. T. Cheung, "Computer Simplification ofMulti-Valued Switching Functions," in Ref. 10, Chap. 7.

18. W. R. Smith III, "Minimization of Multivalued Functions," inRef. 10, Chap. 8.

19. e.g., C. E. Lemke, H. M. Salkin, and K. Spielberg, "Set Coveringby Single Branch Enumeration with Linear Programming Sub-problems," Oper. Res. 19, 988 (1971).

20. H. J. Gallagher, T. K. Gaylord, M. G. Moharam, and C. C. Guest,"Reconstruction of Binary-Data-Page Thick Holograms for anArbitrarily Oriented Reference Beam," Appl. Opt. 20, 300(1981).

21. B. L. Drake, R. P. Bocker, M. E. Lasher, R. H. Patterson, and W.J. Miceli, "Photonic Computing Using the Modified Signed-Digit Number Representation," Opt. Eng. 25, 38 (1986).

22. H. L. Garner, "The Residue Number System," IRE Trans. Elec-tron. Comput. EC-8, 140 (1959).

23. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and ItsApplications to Computer Technology (McGraw-Hill, NewYork, 1967).

Patter continued from page 3060The power-conversion efficiency of the low-resistivity silicon solar cell is

considerably less than the maximum theoretical value mainly because theopen-circuit voltage is smaller than simple p/n junction theory predicts.With this method, the air-mass-zero open-circuit voltage has been increasedfrom the 600-mV level to -650 mV. Figure 11 gives a cross-sectional schemat-ic view of the proposed cell. Shown is the p-type substrate and the n-typeemitter comprising a low region and a high-electron-accumulation region. Anoxide layer on the illuminated surface contains a high positive charge. Shal-low n+ contact diffusion regions underlie each of the one or more aluminumemitter contacts, and an ohmic contact underlies the p region.

Ap/n junction exists between the emitter region and the substrate. A high/low junction has been formed between the high-electron-accumulation regionand the low emitter region. An aluminum metal contact is in ohmic contactwith the emitter, and a shallow n diffusion contact is made under thismetallized portion of the top surface area. The aluminum emitter contactcovers no more than 5-10% of the surface area.

Provided in the proposed solar cell is a suppression of dark emitter currentand an increase of short-circuit current. The emitter is less heavily doped-preferably in the -1018 to 1019-cm-3 range-compared to emitters of conven-tional cells, which are typically doped to 102° cm 3. A heavily doped emitterregion has the disadvantage that the dark emitter recombination is so largethat it limits the maximum open-circuit voltage to -600 mV. The high/lowemitter suppresses the dark emitter recombination current, resulting in pow-er-conversion efficiencies significantly higher than were previously achieved.

This work was done by Arnost Neugroschel, Shing-Chong Pao, Fred A.Lindholm, and Jerry G. Fossum of the University of Florida for Lewis Re-search Center. Refer to LEW-13618.

Broadband ultrasonic transducersThe bandwidth of a piezoelectric transducer can be greatly increased by

fabricating the transducer with a nonuniform thickness. The greater band-width improves the accuracy of sonar and ultrasonic imaging equipment.

A conventional piezoelectric transducer consists of a crystal disk with metalfilms on its two flat parallel surfaces. Applying an alternating electricalpotential to the films expands and contracts the crystal rapidly so that itlaunches compressional elastic waves into the material around it. With itsparallel faces, the crystal resonates at a narrow range of frequencies, and theultrasonic waves it sets up in the surrounding medium have essentially thesame narrow range.

In the new transducer, the crystal surfaces are made nonparallel. Onesurface may be planar; and the other, concave, for example. The geometry canbe designed to produce a nearly uniform response over a predetermined bandof frequencies and to attenuate strongly the frequencies outside the band (seeFig. 12). The new transducer may make it unnecessary to use signal-process-ing circuits to compensate for the transducer frequency response or to useauxiliary circuits to modify the frequency spectrum of the voltage applied tothe crystal. Such circuits would add to the cost of the transducer system.

This work was done by Richard C. Heyser of Caltech for NASA's JetPropulsion Laboratory. Refer to NPO-16590.

a

a*8IcR

c

>

o

0 5 10

Relative Frequency

Fig.12. Frequency response of a plano-concave transducer covers abroad range. The steep sides of the response curve show that the

transducer cuts off extraneous frequencies cleanly.

Mapping the structure of heterogeneous materialsA nondestructive method for studying the structure of heterogeneous mate-

rials uses energy-dispersive x-ray analysis in a scanning electron microscope.A scanning microdensitometer/Fourier analyzer (SMFA) is applied to theSEM images to obtain statistics about the sample structure.

The method was originally developed for studying the effect on combustionof the fine structure of composite solid propellants. The propellant studiedincludes ammonium perchlorate as an oxidizer and hydroxyl-terminated poly-butadiene as a binder. Three samples were prepared for analysis; one withcoarse oxidizer particles (mass mean particle size approximately 200 ,um), onewith fine particles (10 pm), and one containing both size groups. The resultsfor a representative bimodal sample are shown in Fig. 13.

0.8

a

a ~-Z

1.0

' 0.80T

2

0.4(

'~ 060(1.00

0.80

-50,4

.

3:

0.2

00U- 0.40Z

0.20

0.00

D E

0 128 256 384 51:Scan Line

0 ono 0.10 0.20 0. 40 0.80

Normalized Spatial Frequency of Scan Shown Above

Fig. 13. Analyses of scanning-microdensitometer measurements ofa chlorine map yield data that help to characterize the oxidizer-

density distribution.continued on page 3121


10- 1 .\ j

20 i r

30

40 ' I l

12

.

logical minimization of multilevel coded functions

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