logic not gate

8/10/2019 logic NOT gate

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ACTIVITY 1: LOGIC GATE: INVERTER

NOGAS, LEONARDO G.

Submitted to: Prof. Jefrey C. Pasco

I.

OBJECTIVES:

To study the basic logic gate: inverter, as well as itsrepresentation by truth table,

logic diagram and Boolean algebra.

To familiarize Quartus II, computer-aided design tool via the inverter simulation.

To observe the pulse response of the inverter.

II. BASIC CONCEPT

The digital Logic NOT Gate is the most basic of all the logical gates and is

sometimes referred to as an Inverting Buffer or simply a Digital Inverter. It is a single

input device which has an output level that is normally at logic level 1 and goes LOW

to a logic level 0 when its single input is at logic level 1, in other words it inverts

(complements) its input signal.

Figure 1. Inverter or Not Gate

Logic NOT Gates are available using digital circuits to produce the desired logical

function. The standard NOT gate is given a symbol whose shape is of a triangle pointing

to the right with a circle at its end. This circle is known as an inversion bubble and is

used in NOT, NAND and NOR symbols at their output to represent the logical operation

of the NOT function. This bubble denotes a signal inversion (complement) of the signal

and can be present on either or both the output and/or the input terminals.


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Table 1 Truth table for Not Gate

Logic NOT gates provide the complement of their input signal and are so called

because when their input signal is HIGH their output state will NOT be HIGH.

Likewise, when their input signal is LOW their output state willNOT be LOW. As they

are single input devices, logic NOT gates are not normally classed as decision making

devices or even as a gate, such as the AND or OR gates which have two or more logic

inputs. Commercial available NOT gates ICs are available in either 4 or 6 individual gates

within a single IC package.

The bubble (o) present at the end of the NOT gate symbol above denotes a

signal inversion (complement) of the output signal. But this bubble can also be present

at the gates input to indicate an active-LOWinput. This inversion of the input signal is

not restricted to the NOT gate only but can be used on any digital circuit or gate as

shown with the operation of inversion being exactly the same whether on the input or

output terminal. The easiest way is to think of the bubble as simply an inverter. (

Wayne Storr, 2014)

III.

MATERIALS

Laptop Quartus II Web Edition

IV.

PROCEDURE:

1. Open Quartus II. Click New Project Wizard and then fill up the following requirements.

2. Go to file > new > schematic diagram. Add components double click the design space

and add a NOT gate.

3.

To add the input and output pins, double click the design space and add input ad output

pins.

4. In order to simulate, you need to compile first the schematic file (Ctrl + L).

5. To simulate, click file > new > universally program VWP

6. To specify the input; right click, choose clock and choose

a. Rising ( if you want your input be 1)

b. Falling ( if you want your input be 0)


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7. Observe wave output

Figure 2 Input waveform at pin_name 2 and output waveform at pin_name1

V. CONCLUSION:

A NOT gate is usually called an inverter because it gives the complement value of

the input. When the output signal is high the input signal is low, when the input signal is

low, the output signal is high. This can be observed in the simulation. The input is a

pulse wave with amplitude 1.When the input is 1, the output values is zero, when the

input is 0, the output is one. The truth table in table 1 was confirmed because if you give

an input value of 1 it gives an output value of 0 and vice versa. Thus, a not gate gives an

inverted version of the input signal.

VI.REFERENCES

Wayne Storr(December 2014).The Logic NOT gate. . Retrieved from

http://www.electronics-tutorials.ws/logic/logic_4.html

logic not gate

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