gate logic: two-level simplification
DESCRIPTION
Gate Logic: Two-Level Simplification. Design Example: Two Bit Comparator. Block Diagram and Truth Table A 4-Variable K-map for each of the 3 output functions. Gate Logic: Two-Level Simplification. Design Example: Two Bit Comparator. F1 = F2 = F3 =. Gate Logic:Two-Level Simplification. - PowerPoint PPT PresentationTRANSCRIPT
2-1
IntroductionGate Logic: Two-Level SimplificationDesign Example: Two Bit Comparator
Block Diagramand
Truth Table
A 4-Variable K-mapfor each of the 3output functions
F 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
F 2 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
F 3 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B 0 1 0 1
A 0 0 1 1
=, >, < F 1 A B = C D F 2 A B < C D F 3 A B > C D
A B
C D
N 1
N 2
2-2
IntroductionGate Logic: Two-Level SimplificationDesign Example: Two Bit Comparator
F1 =
F2 =
F3 =
AB 00 01 11 10
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
00
01
11
10 C
CD
A
D
B
K-map for F 1
AB 00 01 11 10
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
00
01
11
10 C
CD
A
D
B
K-map for F 2
AB 00 01 11 10
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
00
01
11
10 C
CD
A
D
B
K-map for F 3
2-3
IntroductionGate Logic:Two-Level SimplificationDesign Example: Two Bit Comparator
F1 = A' B' C' D' + A' B C' D + A B C D + A B' C D'
F2 = A' B' D + A' C + B' C D
F3 = B C' D' + A C' + A B D'
AB 00 01 11 10
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
00
01
11
10 C
CD
A
D
B
K-map for F 1
AB 00 01 11 10
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
00
01
11
10 C
CD
A
D
B
K-map for F 2
AB 00 01 11 10
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
00
01
11
10 C
CD
A
D
B
K-map for F 3
2-4
IntroductionGate Logic: Two-Level SimplificationDesign Example: Two Bit Adder
Block Diagramand
Truth Table
A 4-variable K-mapfor each of the 3output functions
+ N 3
X 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1
Y 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1
Z 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B 0 1 0 1
A 0 0 1 1
A B
C D
N 1
N 2
X Y Z
2-5
IntroductionGate Logic: Two-Level SimplificationDesign Example (Continued)
X =
Z =
Y =
AB 00 01 11 10
0 0 0 0
0 0 1 0
0 1 1 1
0 0 1 1
00
01
11
10 C
CD
A
D
B
K-map for X
AB 00 01 11 10
0 0 1 1
0 1 0 1
1 0 1 0
1 1 0 0
00
01
11
10 C
CD
A
D
B
K-map for Y
AB 00 01 11 10
0 1 1 0
1 0 0 1
1 0 0 1
0 1 1 0
00
01
11
10 C
CD
A
D
B
K-map for Z
2-6
IntroductionGate Logic: Two-Level SimplificationDesign Example (Continued)
X = A C + B C D + A B D
Z = B D' + B' D = B xor D
Y = A' B' C + A B' C' + A' B C' D + A' B C D' + A B C' D' + A B C D
= B' (A xor C) + A' B (C xor D) + A B (C xnor D)
= B' (A xor C) + B (A xor B xor C)gate countreduced if
XOR available
1's on diagonal suggest XOR!Y K-Map not minimal as drawn
AB 00 01 11 10
0 0 0 0
0 0 1 0
0 1 1 1
0 0 1 1
00
01
11
10 C
CD
A
D
B
K-map for X
AB 00 01 11 10
0 0 1 1
0 1 0 1
1 0 1 0
1 1 0 0
00
01
11
10 C
CD
A
D
B
K-map for Y
AB 00 01 11 10
0 1 1 0
1 0 0 1
1 0 0 1
0 1 1 0
00
01
11
10 C
CD
A
D
B
K-map for Z
2-7
IntroductionGate Logic: Two-Level SimplificationDesign Example (Continued)
Two alternativeimplementations of Ywith and without XOR
Note: XOR typicallyrequires 4 NAND gates
to implement!
X XOR Y
X
Y
\ D \ A \ C
Y 1
A
C
D
\ B
B
Y 2
2-8
IntroductionGate Logic: Two-Level SimplificationDesign Example: BCD Increment By 1
W =
X =
Y =
Z =
AB 00 01 11 10
0 0 X 1
0 0 X 0
0 1 X X
0 0 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
0 1 X 0
0 1 X 0
1 0 X X
0 1 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
0 0 X 0
1 1 X 0
0 0 X X
1 1 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
1 1 X 1
0 0 X 0
0 0 X X
1 1 X X
00
01
11
10 C
CD
A
D
B
Z Y
X W
2-9
IntroductionGate Logic: Two-Level Simplification
W = B C D + A D'
X = B C' + B D' + B' C D
Y = A' C' D + C D'
Z = D'
AB 00 01 11 10
0 0 X 1
0 0 X 0
0 1 X X
0 0 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
0 1 X 0
0 1 X 0
1 0 X X
0 1 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
0 0 X 0
1 1 X 0
0 0 X X
1 1 X X
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
1 1 X 1
0 0 X 0
0 0 X X
1 1 X X
00
01
11
10 C
CD
A
D
B
Z Y
X W
2-10
IntroductionGate Logic: Two Level SimplificationDefinition of Terms
implicant: single element of the ON-set or any group of elements that can be combined together in a K-map
prime implicant: implicant that cannot be combined with another implicant to eliminate a term
essential prime implicant: if an element of the ON-set is covered by a single prime implicant, it is an essential prime
Objective:
grow implicants into prime implicants
cover the ON-set with as few prime implicants as possible
essential primes participate in ALL possible covers
2-11
IntroductionGate Logic: Two Level Simplication
Examples to Illustrate Terms
6 Prime Implicants:
A' B' D, B C', A C, A' C' D, A B, B' C D
essential
Minimum cover = B C' + A C + A' B' D
5 Prime Implicants:
B D, A B C', A C D, A' B C, A' C' D
essential
Essential implicants form minimum cover
AB 00 01 11 10
0 1 1 0
1 1 1 0
1 0 1 1
0 0 1 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
0 0 1 0
1 1 1 0
0 1 1 1
0 1 0 0
00
01
11
10 C
CD
A
D
B
2-12
IntroductionGate Logic: Two Level SimplificationMore Examples
Prime Implicants:
B D, C D, A C, B' C
essential
Essential primes form the minimum cover
AB 00 01 11 10
0 0 0 0
0 1 1 0
1 1 1 1
1 0 1 1
00
01
11
10 C
CD
A
D
B
2-13
IntroductionGate Logic: Two-Level SimplificationAlgorithm: Minimum Sum of Products Expression from a K-Map
Step 1: Choose an element of ON-set not already covered by an implicant
Step 2: Find "maximal" groupings of 1's and X's adjacent to that element.Remember to consider top/bottom row, left/right column, andcorner adjacencies. This forms prime implicants (always a powerof 2 number of elements).
Repeat Steps 1 and 2 to find all prime implicants
Step 3: Revisit the 1's elements in the K-map. If covered by single primeimplicant, it is essential, and participates in final cover. The 1's itcovers do not need to be revisited
Step 4: If there remain 1's not covered by essential prime implicants, thenselect the smallest number of prime implicants that cover theremaining 1's
2-14
IntroductionGate Logic: Two Level SimplificationExample: F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Initial K-map
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
2-15
IntroductionGate Logic: Two Level SimplificationExample: F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Initial K-map Primes aroundA' B C' D'
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
2-16
IntroductionGate Logic: Two Level SimplificationExample: F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Initial K-map Primes aroundA' B C' D'
Primes aroundA B C' D
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
2-17
IntroductionGate Logic: Two-Level SimplificationExample Continued
Primes aroundA B' C' D
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
2-18
IntroductionGate Logic: Two-Level SimplificationExample Continued
Primes aroundA B' C' D'
Primes aroundA B' C' D
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
2-19
IntroductionGate Logic: Two-Level SimplificationExample Continued
Primes aroundA B' C' D'
Primes aroundA B' C' D
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
AB 00 01 11 10
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
00
01
11
10 C
CD
A
D
B
Essential Primeswith Min Cover
2-20
IntroductionGate Logic: Two-Level Simplification
5-Variable K-maps
F(A,B,C,D,E) = m(2,5,7,8,10,13,15,17,19,21,23,24,29 31)
=
BC DE
BC DE
A =0
A =1
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
1
00
1
10
1
10 BC
DE 00 01 11
00
01
11
10
A=0
BC DE 00 01 11
01
11
10
A=1
1 1
1
1 1
1
1 1
1 1 1
2-21
IntroductionGate Logic: Two-Level Simplification
5-Variable K-maps
F(A,B,C,D,E) = m(2,5,7,8,10,13,15,17,19,21,23,24,29 31)
= C E + A B' E + B C' D' E' + A' C' D E'
BC BC DE
BC DE
A =0
A =1
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
BC DE 00 01 11 10
00
01
11
10
A=0
BC DE 00 01 11 10
00
01
11
10
A=1
1 1
1
1
1 1
1
1
1 1 1
1 1 1
2-22
IntroductionGate Logic: Two Level Simplification6- Variable K-Maps
F(A,B,C,D,E,F) =m(2,8,10,18,24,
26,34,37,42,45,50,53,58,61)
=
CD EF
CD EF
AB =00
AB =01
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
CD EF
AB =11
00 01 11 10 00
01
11
10
48 52 60 56
49 53 61 57
51 55 63 59
50 54 62 58
CD EF
AB =10
00 01 11 10 00
01
11
10
32 36 44 40
33 37 45 41
35 39 47 43
34 38 46 42
CD EF
CD EF
AB =00
AB =01
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
CD EF
AB =11
00 01 11 10 00
01
11
10
CD EF
AB =10
00 01 11 10 00
01
11
10
1
1 1
1
1 1
1 1
1 1
1 1
1 1
2-23
IntroductionGate Logic: Two Level Simplification6- Variable K-Maps
F(A,B,C,D,E,F) =m(2,8,10,18,24,
26,34,37,42,45,50,53,58,61)
= D' E F' + A D E' F+ A' C D' F'
CD EF
CD EF
AB =00
AB =01
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
CD EF
AB =11
00 01 11 10 00
01
11
10
48 52 60 56
49 53 61 57
51 55 63 59
50 54 62 58
CD EF
AB =10
00 01 11 10 00
01
11
10
32 36 44 40
33 37 45 41
35 39 47 43
34 38 46 42
CD EF
CD EF
AB =00
AB =01
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
CD EF
AB =11
00 01 11 10 00
01
11
10
CD EF
AB =10
00 01 11 10 00
01
11
10
1
1 1
1
1 1
1 1
1 1
1 1
1 1
2-24
IntroductionGate Logic: CAD Tools for SimplificationQuine-McCluskey Method
Tabular method to systematically find all prime implicants
Implication Table
Column I 0000 0100 1000 0101 0110 1001 1010 0111 1101
1111
F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Step 1: Fill Column 1 with ON-set and DC-set minterm indices. Group by number of 1's.
Stage 1: Find all prime implicants
2-25
IntroductionGate Logic: CAD Tools for SimplificationQuine-McCluskey Method
Tabular method to systematically find all prime implicants
Implication Table
Column I Column II 0000 0-00 -000 0100 1000 010- 01-0 0101 100- 0110 10-0 1001 1010 01-1 -101 0111 011- 1101 1-01
1111 -111 11-1
F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Step 1: Fill Column 1 with ON-set and DC-set minterm indices. Group by number of 1's.
Step 2: Apply Uniting Theorem. Compare elements of group w/ N 1's against those with N+1 1's. Differ by one bit implies adjacent. Eliminate variable and place in next column.
E.g., 0000 vs. 0100 yields 0-00 0000 vs. 1000 yields -000
When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants.
Repeat until no further combinations can be made.
Stage 1: Find all prime implicants
2-26
IntroductionGate Logic: CAD Tools for SimplificationQuine-McCluskey Method
Tabular method to systematically find all prime implicants
Implication Table
Column I Column II Column III 0000 0-00 * 01-- * -000 * 0100 -1-1 * 1000 010- 01-0 0101 100- * 0110 10-0 * 1001 1010 01-1 -101 0111 011- 1101 1-01 *
1111 -111 11-1
F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Step 1: Fill Column 1 with ON-set and DC-set minterm indices. Group by number of 1's.
Step 2: Apply Uniting Theorem. Compare elements of group w/ N 1's against those with N+1 1's. Differ by one bit implies adjacent. Eliminate variable and place in next column.
E.g., 0000 vs. 0100 yields 0-00 0000 vs. 1000 yields -000
When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants.
Repeat until no further combinations can be made.
Stage 1: Find all prime implicants
2-27
IntroductionGate Logic: CAD Tools for SimplificationQuine-McCluskey Method Continued
Prime Implicants:
0-00 = A' C' D'
100- = A B' C'
1-01 = A C' D
-1-1 = B D
-000 = B' C' D'
10-0 = A B' D'
01-- = A' B
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
2-28
IntroductionGate Logic: CAD Tools for SimplificationQuine-McCluskey Method Continued
Prime Implicants:
0-00 = A' C' D'
100- = A B' C'
1-01 = A C' D
-1-1 = B D
-000 = B' C' D'
10-0 = A B' D'
01-- = A' B
Stage 2: find smallest set of prime implicants that cover the ON-set
recall that essential prime implicants must be in all covers
another tabular method : the prime implicant chart
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
X 1 0 1
0 1 1 1
0 X X 0
0 1 0 1
2-29
IntroductionGate Logic: CAD Tools for Simplification
rows = prime implicantscolumns = ON-set elementsplace an "X" if ON-set element is covered by the prime implicant
Prime Implicant Chart
2-30
IntroductionGate Logic: CAD Tools for Simplification
rows = prime implicantscolumns = ON-set elementsplace an "X" if ON-set element is covered by the prime implicant
Prime Implicant Chart
If column has a single X, than theimplicant associated with the rowis essential. It must appear inminimum cover
2-31
IntroductionGate Logic: CAD Tools for SimplificationPrime Implicant Chart (Continued)
Eliminate all columns covered byessential primes
2-32
IntroductionGate Logic: CAD Tools for SimplificationPrime Implicant Chart (Continued)
Eliminate all columns covered byessential primes
Find minimum set of rows thatcover the remaining columns
F= A B' D' + A C' D + A' BF= A B' D' + A C' D + A' B
2-33
IntroductionGate Logic: CAD Tools for SimplificationESPRESSO Method
Problem with Quine-McCluskey: the number of prime implicants grows rapidly with the number of inputs
upper bound: 3 /n, where n is the number of inputsn
finding a minimum cover is NP-complete, i.e., a computational expensive process not likely to yield to any efficient algorithm
Espresso: trades solution speed for minimality of answer
don't generate all prime implicants (Quine-McCluskey Stage 1)
judiciously select a subset of primes that still covers the ON-set
operates in a fashion not unlike a human finding primes in a K-map
2-34
IntroductionGate Logic: CAD Tools for SimplificationEspresso Method: Overview
1. Expands implicants to their maximum sizeImplicants covered by an expanded implicant are removed from further considerationQuality of result depends on order of implicant expansionHeuristic methods used to determine orderStep is called EXPAND
Irredundant cover (i.e., no proper subset is also a cover) is extracted from the expanded primesJust like the Quine-McCluskey Prime Implicant ChartStep is called IRREDUNDANT COVER
Solution usually pretty good, but sometimes can be improvedMight exist another cover with fewer terms or fewer literalsShrink prime implicants to smallest size that still covers ON-setStep is called REDUCE
Repeat sequence REDUCE/EXPAND/IRREDUNDANT COVER to find alternative prime implicantsKeep doing this as long as new covers improve on last solution
A number of optimizations are tried, e.g., identify and remove essential primes early in the process
2.
3.
4.
5.
2-35
IntroductionGate Logic: CAD Tools for SimplificationEspresso Inputs and Outputs
.i 4
.o 1
.ilb a b c d
.ob f
.p 100100 10101 10110 11000 11001 11010 11101 10000 -0111 -1111 -.e
-- # inputs-- # outputs-- input names-- output name-- number of product terms-- A'BC'D'-- A'BC'D-- A'BCD'-- AB'C'D'-- AB'C'D-- AB'CD'-- ABC'D-- A'B'C'D' don't care-- A'BCD don't care-- ABCD don't care-- end of list
F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)
Espresso Input Espresso Output
.i 4
.o 1
.ilb a b c d
.ob f
.p 31-01 110-0 101-- 1.e
F= A C' D + A B' D' + A' B
2-36
IntroductionGate Logic: CAD Tools for Simplification
Espresso: Why Iterate on Reduce, Irredundant Cover, Expand?
Initial Set of Primes found bySteps1 and 2 of the Espresso
Method
4 primes, irredundant cover,but not a minimal cover!
Result of REDUCE:Shrink primes while still
covering the ON-set
Choice of order in which to perform shrink is important
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 1 0 0
1 1 1 1
0 0 1 1
1 1 1 1
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 1 0 0
1 1 1 1
0 0 1 1
1 1 1 1
2-37
IntroductionGate Logic: CAD Tools for SimplificationEspresso Iteration (Continued)
Second EXPAND generates adifferent set of prime implicants
IRREDUNDANT COVER found byfinal step of espresso
Only three prime implicants!
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 1 0 0
1 1 1 1
0 0 1 1
1 1 1 1
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 1 0 0
1 1 1 1
0 0 1 1
1 1 1 1
2-38
IntroductionPractical Matters
Technology Metrics
Metric Bipolar MOS
Gate Delay Low Medium
Integration Low High
Power High Low
Noise Good Good
Cost Low Medium
Fan-out Fair Good
Drive Good Low
2-39
IntroductionPractical Matters
TTL Packaged Logic
Small and Medium Scale Integration dual in-line package (DIP)
Subfamilies of TTL Components have been designed so that they can be interconnected without too much concern about proper electrical operation
74XX 74HXX : high speed 74LXX : low power 74SXX : Schottsky TTL, faster than 74HXX and same power as 74LXX 74LSXX : low power Schottsky TTL AS TTL : 2 times faster than S TTL ALS TTL : less power than LS TTL with higher speed
Speed-Power Product compare the efficiency of logic families multiply the delay through a gate by the power it consumes smaller number - reduced delay and reduced power
2-40
IntroductionPractical Matters
Schematic Documentation Standards
Standard Schematic Symbols
Names
Polarization and Bubbles
Crossovers and Connections
Hierarchical Documentation and Cross-References
2-41
IntroductionPractical Matters
Standard SSI gate symbols
2-42
IntroductionPractical Matters
• MSI component schematic
2-43
IntroductionPractical Matters
• Use of a detail letter
2-44
IntroductionPractical Matters
• Example of polarity inversion
2-45
IntroductionPractical Matters
• Incorrect bubble matching
2-46
IntroductionPractical Matters
• Correct bubble matching
2-47
IntroductionPractical Matters
• A case where polarity and bubbles don’t match
2-48
IntroductionPractical Matters
• Wiring connection(top) and crossover(bottom)
2-49
IntroductionChapter Summary
Primitive logic building blocksINVERTER, AND, OR, NAND, NOR, XOR, XNOR
Canonical FormsSum of Products, Products of Sums
Incompletely specified functions/don't cares
Logic Minimization
Goal: two-level logic realizations with fewest gates and fewest number of gate inputs
Obtained via Laws and Theorems of Boolean Algebra
or Boolean Cubes and the Uniting Theorem
or K-map Methods up to 6 variables
or Quine-McCluskey Algorithm
or Espresso CAD Tool