logic level

8/11/2019 Logic Level

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Logic level power optimization

Reduction of logic power consumptionmajor priority of a designer attempting tomeet implementation requirements

Power optimizationreduction of itsswitching activity of switched capacitance

Optimization for combinational and

sequential circuits are provided Exiting techniques the optimization design

flow followed


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Introduction

Reliabilityhot spot detectionelectro

migration and packaging

Power consumption is major concern

All levels of design flow starting from the

system and reaching down to layout level

Gate level design techniques Logic level optimization


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Logic level optimization

It is the design task where RT level

circuit description is optimized in terms of

some criteria such as area, time and

power

Output is optimized gate net list

Two basic steps

1 the technology independent

2 Technology dependent


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Optimization

Circuit Boolean description is optimized ignoring the technology

No, of literals of the Boolean function

No. of levels of the Boolean network

Above two used to estimate area and delay

Estimation inaccurate, the tech independent optimization step is

important Optimized Boolean network can be reused in a future technology

change

Decomposing the whole optimization problem in two sub problemsand solving each problem individually

initial problem complexity is reducedachieving better results

Output of technology independent optimization is optimizedconsidering the adopted technology


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Technology independent

optimization Technology independent optimization techniques are

classified as

Optimization techniques for combinational circuit

Optimization techniques for sequential circuit

Combinational circuit is further classified number of circuit levels

Two level logic minimization targets at 2level circuit implementation - PLA andPLDsMultilevel logic optimization targets to cell baseddesign such as standard cells and gate array ofFPGAs


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Sequential circuit

State assignment step to encode the

states of FSM aiming at the minimization

of the circuit area

Logic optimization step techniques

retimingreduction of the circuit delay


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Adopted technology library

Logic circuit is optimized considering the adoptedtechnology library

Three steps

technology decomposes ( circuit is decomposed) into

basic gatesTechnology mapping where the circuit is mapped to thegates of the library

Post mapping optimization step where techniques for

instance rewiring are taken place Output of the technology dependent step is an optimized

gate netlistused for floor planning, placement, routingand layout optimization


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Optimization of a logic circuit

Lot of techniques and algorithm have beendeveloped in the past aiming at the optimizationof a logic circuit

Due to dynamic power consumption

becomes three dimensional optimization(area-time-power)

Dynamic power dissipation is proportional tothe switching activity of the circuit

Appropriate switching activity estimators areused to calculate quickly and with highaccuracy the switching activity of the circuitduring optimization


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Combinational circuit technology

independent optimization Two level logic minimization

Minimum area for programmable devices or multilevel circuits

2 level Boolean logic minimization algorithms for area such asExpresso, Expresso Exact , Mini

Employing statistical characteristics of input signal methodthat modifies the expand routine of Expresso has beenproposed

Cost function to reduce the switching activity

Drawbacks

static probability assumed to be equal (0.5) for every inputsignal

input signals are spato temporally uncorrelated

Power dissipation of the input signals is not taken into account


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temporal correlation

Power prime implements was proposedto identify theset of all implicants that are sufficient and necessary forobtaining min power (PPI)

Since all signals are assumed spatiotemp uncorrelated

proposed solution is not accurate Accurate method presentedtemporal correlation of the

signal and power consumption of the primary inputsignals are taken into considerations

It forces the output of the AND gates to stay at low logiclevel for a number of combinations of the applied inputvectors

Reduced switching activity and power consumption


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Two level circuits

Goal: Signal with low switching activity to appear asmany times as it is possible in the first level of circuit

In the example x3 - blocking variableuses in the mainroutines of Expresso

Series of iterations a circuit with reduced powerconsumption

Number of iterations is user specified

Upper and lower bounds of average power

consumption/gateNumber of groups of logic variables with similar statistical

parameters


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MULTILEVEL CIRCUITS

Techniques are classified as

1) Boolean optimization techniquesusedont care set

2) Algebraic optimization techniqueswithout using dont care subset ofDemorgans law is used distribute law is

applied while complement of logic variableis not definedfaster than Booleanquality is smaller


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BOOLEAN TECHNIQUES

Dont care reduces the area and time improvement

Total power consumption may be increasedtransitivefan out nodes are changed

Without increasing the switching activity

The impact of transformation on the function f must beexactly known when g is optimized

Switching activity of node f as a function of g is optimized

Dont care of node g consist

1) External dont care set (EDCs)2) Satisfiability dont care set (SDCs)

3) Observability dont care set(ODCs)


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ODC CALCULATION

ODC can be computed

ODCg=ODCf + ODCfgwith ODCfg

Susbset of ODCs for node f called -Propagated power relevant observability

Dont care (PPODCf)

Using PPODCf to compute ODCgensured that any change in function of g

doesnt increase the switching activity of f


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ODC CALCULATION

p(f) signal probability of f

ODC of node g is modified

Power relevant observability Dont care (PODC)

PODCg= PPODCf+ ODCfg

To ensure that the switching activity of any other

node in the transition fanout of g for instance h

should be increased Monotone power relevant observability dont

care (MPODCg) for node g was introduced


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ALGEBRAIC TECHNIQUES

Power saving factorextraction affect the loading on itsinputs and amount of logic sharing

Multilevel network can be represented by 2 level logicfunction

Efficient methods for node elimination, factorization andlogic decomposition

If Ea(sw) + Eg(sw) > Ec(sw) + Eh(sw) then PA > PB

If prob(a) = 0.5 and prob(b) = prob(c) = 0.25

Then PA-PB = 13/128 Power savings of 18% expected (compared to minimum

literal network)


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LEXICOGRAPHIC COST

Increase in the number of literals in the cktresults into increased switchedcapacitancemore power consumption

Lexicographic cost (Da,Dp) Daliteral saving factor Dppower

saving factor

Power saving factor is very expensive tobe computedBetter to calculate it onlyfor a subset of candidate divisors


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GUARDED EVALUATION

Shutdown techniques

Tl(s)latest arrival time for s

Te(I)earliest arrival time of signal I I - Transparent latches can be added for

reducing the switching activity of F


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SEQUENTIAL CIRCUIT - STATE

ASSIGNMENT

Given the state transition graph (STG) of a FSM

assign binary codes in all states such that a

given cost function G is minimized The number of transitions at the state lines in

two successive clock periods to be minimized

Combing reduced switching activity of the statelines with low power implemented combinational

logicsignificant power reduction


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HAMMING DISTANCE

Minimize the number of transitions of the state

lines

Hamming distance between the codes assigned

to pairs of states Transition probability from one state to another

one is not the same for every pair of states

Hamming distance between pairs of states mustbe weighted with the corresponding transition

probability


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STATE TRANSITION


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STATE TRANSITION

PROBABILITY

pi,j is an approximation - the exact state transition probability Pi,j

pi,j computed by considering only one input combinations - ignoringthe probability the m/c being at state Si

Exact transition probability Pij = Pi pij -solving a system of linearequations called Chapman - Kolmogorov equation

Impact of state assignment in the consumed power of thecombinational circuit - number of heuristics were introduced

Heuristics - combinational circuit optimized in terms of area and lowpower consumption

Wij - modified to take into account the exact state transitionprobability

Linear integer programming was used for solving the stateassignment - genetic algorithm

Cost function are proposed when the combinational circuit isimplemented either as 2 or multilevel gate network


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LOGIC OPTIMIZATION

PRE COMPUTATION

Selectively pre computing of the output logic values of ackt one clock cycle before they are required

use to reduce the internal switching activity of the

combinational logic in the successive clock cycle Partitioned into 2 sets corresponding to registers R1 and

R2

If function g1 or g2 equals 1, the value of the output

function f is fully determined Boolean variables function g1 and g2 are subset of the

input signals

Remaining signals (X k+1, ..XN) can be frozen


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PRE COMPUTATION

Assumption: It is not allowed both g1 and g2 to beevaluated to 1

Logic level of g1 or g2 is high during clock cycle T.

Enable signal of register R2 is low

Output of R2 during clock cycle T+1 are not changed

Output of R1 is updated the function f is evaluated correctly

Input block A changes the switching activity of this block isreduced

g1 and g2 occupy extra area - consumes additional powerAppropriate trade off analysis


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RETIMING

Novel method to reduce the power for pipeline sequential ckt - knownas retiming

The techniques that reposition the filpflop of the ckt resulting into themin. either area or the delay

Idea is to place a flipflop in a ckt node with high glitching activity andhigh load capacitance

Glitches are not propagated to the transitive fanout of the noderesulting in a reduction of the total switching

Attention to be paid because the switching activity of some nodes of thecircuit may be changed due to retiming - increase powerconsumption

Number of used registers should be minimizedPower dissipation of the registers and clock are not negligible

To preserve the timing behavior of the ckt when retiming for low power

SYNTHESIS OF FSM WITH


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SYNTHESIS OF FSM WITH

GATED CLOCK

The operation of the FSM there are conditions where the state andoutput of the FSM dont change

Clocking the ckt wastes power both in the combinational logic andregisters

Stop the clock during idle conditions

Gated clock benefits areClock is stopped no power is consumed by the combinational ckt sinceinputs unchanged

No power consumed by the flipflop and gated clock ling

Setting a new activation signal GCLK

Fa activation signal - uses primary inputs and state lines of the machine

Power savings 10-30%Fa takes place with high probability during the ckt operation

TECHNOLOGY DEPENDENT


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TECHNOLOGY DEPENDENT

OPTIMIZATION

PATH BALANCING

Logic ckt are interconnected can strongly affect the overallswitching activity and hence the power dissipation

Timing skew between signals in a ckt can cause spurious

transition - resulting extra powerDelay paths that converge at each gate must be balanced

f=abcd implemented in two ways

Tree implementation of function f provides glitches

elimination reducing effectively the total powerPath balancing achieved before tech mapping by

selectively collapsing and logic decomposition


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PATH BALANCING

After tech mapping - delay insertion and pin reordering

Selectively collapsing the fanins of a node arrival time atthe output of the node can be changed

Logic decomposition and extraction - minimize the level

difference between the inputs of the node Inserting variable delay buffers - delays of all paths in the

ckt can be made equal

Use min. no. of delay elements to achieve max reduction

in glitching activity Path delay balanced by an appropriate signal to the pin

assignment


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TECHNOLOGY DECOMPOSITION

Next step during logic synthesis of a network toconvert the network to another (contains 2 input

AND/NAND and inverter gates - calleddecomposition

Carried out before mapping Decomposition scheme that minimizes the total

switching activities of the network - powerefficient technology mapping

Given the switching activity at each input a node- Tsui et al suggested a technique for ANDdecomposition


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TECHNOLOGY DECOMPOSITION

Reduces the total switching activity - zero delay -used 2 input AND gate - introduced indecomposition model

Signal d highest switching activity is injected

last in configuration A - better powerperformance

Techniques found being optimal for dynamicCMOS ckt - also produces good results of static

CMOS ckt Decomposition procedure reduces the totalswitching activity by 5% over the conventionalbalanced tree decomposition method


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TECHNOLOGY MAPPING

Some design techniques for low power consumption

Main concepts is to hide nodes with high switchingactivity inside the gates - can drive smaller loadcapacitance

Two steps 1) Computation of power delay curves ( power

consumption Vs arrival time) of all nodes in the network

2) Mapping solution according to the previous curves

and required time at the primary inputs 18% powersaving at 16 % increase in area without any penalty innetwork performance


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TECHNOLOGY MAPPING

Implies that power delay mapper reduces thenumber of high switching activity subnetworks atthe expenses of increasing the number of lowswitching activity

Reduces network average load

Total power cost - steady state transitions andhazards match can be calculated from the

computed power delay curves at the inputs ofthe gate and power delay characteristics of thegate itself


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POST MAPPING OPTIMIZATION

Estimation of power - in tech independent - inaccurate

The final structure of the ckt and load capacitance ofeach node are unknown

Post mapping optimization - allows performing power

and timing analysis on the mapped ckt - provides morerealistic estimation

Freedom for optimization is reduced after the cktmapping

Idea is based on the redundancy addition and removal Some exiting connections become redundant whichconsumes high power - remarkable power reduction


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Zero delay gate model - ckt signals are uncorrelated

Switching activity Ei of a node i= Ei = 2pi(1-pi)

Input capacitance for every gate is Cg

Probability of input lines pa=pb=pd=pe= and pc=

New connections l1 is added to the ckt, this connectionis redundant. l1 conections from C to g3 becomesredundant (ie s-a-1 faults on these lines are undectable)

g4 is ignored

Switching activity has been reduced power consuption ofthe transformed ckt is smaller



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Automatic test pattern generator (ATPG)

able to identify permissible transformations

on the network may reduce power

consumption

Gate resizing smaller gates are slower -

non critical gates in the ckt - algebraic

decision diagrams are used to computethe timing behavior of the ckt


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