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approach an open circuit so that none of the noise in the DC bias circuit reaches the LNA and to

get maximum coupling of the signal from the RF input to the LNA input (Fig. 2).

Fig. 1 Output resistance (Bold Line) in the presence of two tone test signals(f1,f2) with distortion

products.

Fig. 2 Schematic Diagram of a Low Noise Amplifier (LNA) that can be used together with the

IP3 Boost Circuitry.

2.2 Design with Off-Chip Components

An ideal RF choke can be used to achieve a low resistance at low frequencies and high resistance

at the RF frequencies (Fig. 3). However, it is difficult to obtain an ideal RF choke and the

inductance value of a RF choke requires it to be place off-chip which takes up board space and

adds cost. Another way is to use an LC trap filter, but is has very high impedance close to DC

which degrades the P-1dB [5]. A very thorough Volterra series analysis of this concept can be

found in [5] and will not repeated here.

RFinRFinRFinRFin

DCDCDCDC

BiasBiasBiasBias

RF Choke/LC Trap FilterRF Choke/LC Trap FilterRF Choke/LC Trap FilterRF Choke/LC Trap Filter

RoutRoutRoutRout

RF OutRF OutRF OutRF OutLNALNALNALNA

Fig. 3 Schematic representation of an ideal RF choke used to provide DC bias and low Rout atlow frequencies and high Rout at the high frequencies.

f1 f2

2f -f 2f -f2-f1 frequency

RoutSignal Magnitude

RFin

DCbias

RFout

Lbond + Lmatch

Cmatc

h

Lmatc

hCmatc

h

Vcc

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approximate 10dB difference between the IIP3 and P-1dB.

3.4 Measurement Results

The IIP3 two tone spacing was done at 100kHz and 1MHz. The measured IIP3 for both cases

was 12.5dBm. The measured noise figure for the LNA was 2.5dB. The input return loss was 14.3dB and the output return loss was 22.8dB. The S12 was 17.2dB with an S21 of 9.4dB

which maintains stability. The total current drain for the LNA plus biasing circuitry was

12.76mA at a supply voltage of 2.75V. In bypass mode, the IIP3 was +20dBm with an insertion

loss of just 3.5dB. The input return loss is 31.3dB and the output return loss is 11.8dB.

3.5 Summary and Conclusions

The IP3 boost circuitry can be used to increase the IP3 of the suggested RF amplifier without

any disadvantages. Our topology maximizes the feedback gain and therefore, the linearity, at

the higher frequencies needed for CDMA applications and is done without any additional

external components. The measured IIP3 was +12.5dBm in the active mode and +20dBm in the

bypass mode.

Acknowledgements

The authors would like to thank Calvin Leung and Octavia DeCosta for taking the

measurements.

References

[1] H. Lau, G. Watanabe, T. Schiltz, C. Dozier, C. Denig, and H. Fu, High Performance RF

Front-End Circuits for CDMA Receivers Utilizing BiCMOS and Copper Technologies,

RAWCOM 2000.[2] H. Lau, G. Watanabe, R. Holbrook, and K. Leung, Highly Linear CDMA Low Noise

Amplifier(LNA) with IP3 Boost Circuitry for Wireless Applications to be submitted at

ISSCC 2001, February 2001

[3] T. Tracht, A 1.9 GHz Low Noise Amplifier optimised for high IP3 using BFP540,Infineon

Technologies Application Note No. 057, 1999.

[4] J. Durec, An integrated silicon bipolar receiver subsystem for 900 MHz ISM band

applications,IEEE Journal of Solid-State Circuits,vol. 33, no. 9, pp. 1352-1372, September

1998.

[5] K.L. Fong, High Frequency Analysis of Linearity Improvement Technique of Common-

Emitter Transconductance Stage Using a Low-Frequency Trap Network,IEEE Journal of

Solid-State Circuits,vol. 35, no. 8,pp. 1249-1252, August 2000.

[6] C. Kyono, Motorola CDR1 BiCMOS Design Manual,Motorola Internal Repor t, August1999.

[7] J.Ma, etc.,Graded-Channel MOSFET(GCMOSFET) for High Performance, Low Voltage

DSP Application,IEEETrans. VLSI System, vol.5, no.4, 1997, p357

[8] HP-MDS Users Manual, HP EEsof, Westlake Village, California.