lho 12 interfacing
Click here to load reader
Post on 12-Jan-2016
Embed Size (px)
DESCRIPTIONLHO 12 Interfacing. rd'/wr. Processor. Memory. enable. addr[0-11]. data[0-7]. bus. bus structure. A simple bus. Wires: Uni-directional or bi-directional One line may represent multiple wires Bus Set of wires with a single function Address bus, data bus - PowerPoint PPT Presentation
LHO 12 Interfacing
A simple busWires:Uni-directional or bi-directionalOne line may represent multiple wiresBusSet of wires with a single functionAddress bus, data busOr, entire collection of wiresAddress, data and controlAssociated protocol: rules for communication
Timing DiagramsMost common method for describing a communication protocolTime proceeds to the right on x-axisControl signal: low or highMay be active low (e.g., go, /go, or go_L)Use terms assert (active) and deassertAsserting go means go=0Data signal: not valid or validProtocol may have subprotocolsCalled bus cycle, e.g., read and writeEach may be several clock cyclesRead examplerd/wr set low,address placed on addr for at least tsetup time before enable asserted, enable triggers memory to place data on data wires by time tread
Microprocessor interfacing: I/O addressingA microprocessor communicates with other devices using some of its pinsPort-based I/O (parallel I/O)Processor has one or more N-bit portsProcessors software reads and writes a port just like a registerE.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit portsBus-based I/OProcessor has address, data and control ports that form a single busCommunication protocol is built into the processorA single instruction carries out the read or write protocol on the bus
Types of bus-based I/O: memory-mapped I/O and standard I/OProcessor talks to both memory and peripherals using same bus two ways to talk to peripheralsMemory-mapped I/OPeripheral registers occupy addresses in same address space as memorye.g., Bus has 16-bit addresslower 32K addresses may correspond to memoryupper 32k addresses may correspond to peripheralsStandard I/O (I/O-mapped I/O)Additional pin (M/IO) on bus indicates whether a memory or peripheral accesse.g., Bus has 16-bit addressall 64K addresses correspond to memory when M/IO set to 0all 64K addresses correspond to peripherals when M/IO set to 1
Memory-mapped I/O vs. Standard I/OMemory-mapped I/ORequires no special instructionsAssembly instructions involving memory like MOV and ADD work with peripherals as wellStandard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memoryStandard I/ONo loss of memory addresses to peripheralsSimpler address decoding logic in peripherals possibleWhen number of peripherals much smaller than address space then high-order address bits can be ignoredsmaller and/or faster comparators
Consider a simple processor.I call it the simple processing unit (SPU).
The memory read and I/O read timing for a simple processor is shown below.
The Memory write and I/O write timing for a simple processor is shown below.
No separate I/O address space.Some Real processors
No separate I/O address space.
The 8051Atmel AVR
A basic memory protocolInterfacing an 8051 to external memoryPorts P0 and P2 support port-based I/O when 8051 internal memory being usedThose ports serve as data/address buses when external memory is being used16-bit address and 8-bit data are time multiplexed; low 8-bits of address must therefore be latched with aid of ALE signal
8051 instructions for addressing external code and data memory.
Ex: XM(0) XM(1)MOV DPTR,#0MOVX A,@DPTRINC DPTRMOV R7,AMOVX A,@DPTRXCHA,R7MOVX@DPTR,ADECDPTRXCHA,R7MOVX@DPTR,AEx: XM(0) XM(1)CLR P2CLRR0MOVR1,#1MOVX A,@R0MOVR7,AMOVXA,@R1MOVX@R0,AMOVA,R7MOVX@R1,A
RnC EQU P1.1n_BUSY EQU P1.2BYTE EQU P1.3CLRRnCSETBRnCJNBn_BUSY,$MOVR7,P0CPLBYTEMOVR6,P0
Change individual bits on Port C
RESET_8255 EQU P1.0CTL1 EQU 111111111011B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #1PRTA1 EQU 111111111000B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1PRTB1 EQU 111111111001B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1PRTC1 EQU 111111111010B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1CTL2 EQU 111111110111B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #2PRTA2 EQU 111111110100B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2PRTB2 EQU 111111110101B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2PRTC2 EQU 111111110110B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
CLR RESET_8255 ;REMOVE RESET FROM 8255;DO ADDITION C2|C1
Figure 1. AT90S8515 with expanded memory. What should we do with A16? Answer: connect it to an unused port pin.Question: How could we map the entire 128K bytes of memory to the top 32 Kbytes of the AVR address space.Answer: Connect AVR A15 to /CE on U4. Now the memory is selected only when the AVR addresses the top have of the memory address space where A15 = 1. Connect A15 and A16 of U4 to unused AVR port pins. By changing these port pin, any of the four 32 K byte pages of U4 memory can be switched in and out of the AVR address space.