lesson8 cmos gates

8/8/2019 Lesson8 CMOS Gates

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CMOS Logic Gates

Ali El Kateeb

U of M- Dearborn

ECE 514


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Overview

NOR and NAND gates

Logic Formation Layout of complex logic gates

CMOS transmission gates


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NAND2

The nFETs provide a path from the output to ground if and only ifboth A=1 AND B=1

If any one of nFET is OFF, the output has a strong connection pathto the power supply Vdd through one of the pFETs


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NOR2

When either A=1 OR B=1 (or both), then at least one of thenFET is conducting and the output voltage is 0v

The only time the output is high when both A=0 AND B=0


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General CMOS Static Logic Gates

Features of the topology are:

Every input variable is connected to bothnFET and pFET

AB

C

pMOS only

nMOS only


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General CMOS Static Logic Gates

Features of the topology are: Two logic arrays are used to implement the logic

function One array consists of nFETs with the logic block

connecting the output to ground

The other, pFET, build a logic block connected from the

output to VDD When the inputs are stable, only one logic block is

closed, i.e., either pFET or nFET

Low DC power dissipation

N-input gate requires 2N transistors (one for nFETand one for pFET)


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CMOS Static Logic Gates Static logic gate can implement And-Or-Invert (AOI)

and OAI logic functions easily

Correspond to Sum of Products (SOP) and Productof Sum (POS)

The basic rules of logic formation can be summarizedas following:

Rules apply to group of nFETs that implementindividual functions: Series-connected nMOSFETs give the NAND operation

Parallel-connected nMOSFETs give the NOR operation Rules apply to group of pFETs

Series-connected pMOSFETs to implement the NORoperations

Parallel-connected pMOSFETs to implement the NANDoperation


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CMOS Static Logic Gates:AOI example

The structure of the pFET logic array is the dual ofthe nFET connections

nFETs is series require that the correspondingpFETs be in parallel

Example: F = (AB + C)


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CMOS Static Logic Gates:XOR Example

Example: F = A XOR B (i.e., F= AB + AB)

Create the AOI form, which leads directly to the gate logic, i.e.,

F = (AB +AB)

-


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CMOS Static Logic Gates:XNOR Example

Example: F = AB + AB


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Layout of complex logic gates Logic formation rules are based on series and parallel

combinations of MOSFETs

Layout techniques can be divided into these groups Series-connected MOSFETs

Parallel-connected MOSFETs

Input and output wiring

Wiring to ground and VDD


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Layout of complex logic gates Series-connected MOSFETs

n+ and p+ regions can be shared between two transistors

Since drain and source electrodes are not defined until thevoltage are applied, a common n+ region serves as either adrain or source as required

As the transistor resistance are in series, the RC timeconstant of the group can be a limiting factor in the

switching time


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Layout of complex logic gates

Parallel-connected MOSFETs Parallel connections can be achieved by using n+

and p+

regions in connections with metalinterconnect routing


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Layout of NAND2 and NOR2 gates

Series-parallel logic is required forNAND2 and NOR2 layout NAND2: Two nFETs in series and two pFETs in

parallel

NOR2: Two nFETS in parallel and two pFETs in

series


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Basic Layout Guidelines Do wire planning before cell layout

Assign preferred direction to each layer

Group ps and ns Determine input/output port locations

Power, ground must be wide

Determine cell pitch Height of tallest cell

Number of over-the-cell tracks and wire lengths

Use metal for wiring Use poly for intra-cell wiring only

Use diffusion for connection to transistors only

Do stick diagram first!


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Transistor Layout

Good bad bad bad

Transistors should be at least as wideas contacts

Use as many contacts as possible forwider transistors


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Layout Issues

Two types of diffusion ndiff

poly crossing ndiff makes nMOS transistor

pdiff poly crossing pdiff makes pMOS transistor

Cannot directly connect ndiff and pdiff must connect ndiff to metal and metal to pdiff

Cannot get ndiff too close to pdiff because of wells

large spacing rule between ndiff and pdiff need to group nMOS transistors together and pMOS

transistors together


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Stick Diagram

Simplified version of layout

Abstract the layout so that wires are justlines

No need to worry about width or spacing

Good starting point before the layout


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Wiring Layers

Wiring layers represented by different colors diff: green/yellow

poly: red

metal1: blue

metal2: orange

metal3: purple

Wires on the same layer always connect, ifthey touch. No way to jump wires withoutchanging layers

Need contacts to connect wires on differentlayers


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Transistor

Formed when poly (red) crossesdiffusion (green or yellow)

No connection

Connection

connected transistor


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Basic Layout Planning

Need to route power and ground (in metal)

Keep nMOS devices near nMOS devices and

pMOS devices near pMOS devices nMOS near ground and pMOS near Vdd

Run poly vertically and diffusion horizontallywith m1 horizontally

Keep diffusion wires as short as possible

just enough to make transistors

All long wires in m1 and m2


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Typical Cell Layout Plan

Inverter pMOSFETs: near VDD

nMOSFETs: near GND

Translate a stick diagram to a physical layout Replace each line with a polygon of appropriate size and

shape

Vdd

Gnd


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CMOS Gates

Example: Draw the circuit and stick diagramthat represent the AOI circuit CBA )( +

C

A

out

B A B Vdd

Gnd

out

C


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Switches How to built switches from MOS transistors?

N-type switch

Require one transistor and one gate signal

Transmit 0 well, but when Vdd is applied to the drain, thevoltage at the source is Vdd-Vtn

As Vgs is always equal to Vds, the NMOS transistor is either insaturation or off

When switch logic drives gate logic, n-type switches can causeelectrical problems

When n-type switch driving a complementary gate cause the gateto run slower when the switch input = 1

Since pulldown current is weaker when a lower gate voltageis applied

The complementary gates pulldown will not suck current offthe output capacitance as fast as it should be

VddVth

0


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Switches How to built switches from MOS transistors?

P-type switch

When Vin = 0 and Vout = Vdd Cload will be discharged through P transistor until Vout = Vtp

P-device will stop conducting

Logic 0 is somewhat degraded through p-device

Vout

Cload

Vin


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Review: Voltage Degradation

Both nMOS and pMOS have voltagedegradation problems

nMOS degrades logic 1

pMOS degrades logic 0

VddVth

0

Vdd

|Vth|


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CMOS Transmission Gate

To solve voltage degradation problem, useboth nMOS and pMOS Need both true and complement of control

Bi-directional gate

When S=0, both FETs are in cutoff (TG modeled as open

switch) Setting S to 1, turns on both FETs (TG modeled as closed

switch) Other symbols usedS

S

A B

S

SA B


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CMOS Transmission Gate Electrical model of TG

Parasitic resistance and capacitance in the MOSFETs When the TG is used in a circuit, it acts as a passive switch

that intrinsically slows the response due to theparasitic RCstructure


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TGs act as a voltage-controlled switches Used to implement Boolean switching functions

Many logic functions can be placed into canonical SOP formand implemented using TG-based switching logic networks

Example: 2:1 multiplexer circuit

T= D0S + D1S


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Example: XOR and XNOR

F(A,B) = AB + AB (XOR)

F(A,B) = AB + AB (XNOR)


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CMOS Transmission Gate:Layout

lesson8 cmos gates

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