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    We may view the output networkof the gate as consisting of 2switches:

    SWp (an assert-low device)SWn (an assert-high device)

    These are wired in to ensure thatone switch is closed while the other

    switch is open.

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    The Complementary Pair

    CMOS logic circuits are based on the concept of complementary pairsof transistor switching.

    Complementary pair consists of pFET and nFET.

    The input signal xsimultaneously controlsconduction throughboth FETs.

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    The name complementary is derived from the operation: when one FETis on, the other is off.

    The important aspect of this behavior is that the pFET and nFET are

    electrical opposites, which translates directly into a coherent switchingscheme.

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    The NOT Gate or INVERT function is considered thesimplest Boolean operation.

    It has an input x and produces and output of f(x) off(x) = NOT (x) = x

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    This circuit uses a complementary pair of MOSFETs such that an inputx controls both transistors.

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    If the input x has a value of zero, then pFET MP is on and nFET. MP isoff.

    It is clear that this simple circuit does indeed provide the NOT operation.

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    This can be verified analytically by applying theFET logic rules to write the output f as

    f = x 1 + x 0where the first term describes the MP and the

    second is due to Mn. Simplying givesf = x

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    For a given input logic state of x = 0 or 1, the output isconnected to either Vdd or ground and gives a well-defined value.

    It avoids the possibilities where both FETs are off at thesame time or both on at the same time.

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    How to create2-input NOR gates using the sameprinciples. These are:

    Use a complementary nFET/pFET pair for each input

    Connect the output node to the power supply Vddthrough pFETs

    Connect the output node to the ground through nFETs

    Insure that the output is always a well-defined high-

    voltage or low voltage.

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    De MorganTheorem

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    One approach to building the logic gate is to use the Karnaugh map.

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    The first term connects the output to 1 (the power supply Vdd).

    The second and third terms represent two independent nFET

    paths between the output and 0(ground).

    Combining these statements results in the CMOS NOR 2 circuitshown below.

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    Series-parallel transistor arrangement principle that allows us to designmore complex gates.

    Note that the two pFETs are Mpx and Mpy are connected in series suchthat both must be on to establish a conducting path from Vdd to theoutput. The Mnx and Mny are wired in parallel so that a connection

    between the output and ground is created if ither nFET is on.

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