leds 7-segment displays discussion 7.2 sections 10-2, 10-4, 13-8
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LEDs7-Segment Displays
Discussion 7.2
Sections 10-2, 10-4, 13-8
http://electronics.howstuffworks.com/diode1.htm
Covalent bonds -- Insulator
Semiconductors
Adding a very small amount of P or As to Si makes an n-type semi-conductor with an extra electron
Adding a very small amount of B or Ga to Si makes a p-type semi-conductor with a missing electron (a hole)
Diodes
http://www.mtmi.vu.lt/pfk/funkc_dariniai/diod/index.html
+ -
Light Emmitting DiodeLED
+ -
h
http://electronics.howstuffworks.com/led1.htm
Turning on an LED
+5VR LED
PLD output pin
+5VR LED
PLD output pin
1
0
+5V
+0.2V+1.7V
No current
Currentlight
no light
R =voltagecurrent
=5 1.7
15 x 10 -3 = 220 ohms
Turning on an LED
This is whatwe use in Lab
CPLD output pin0 V R
No Current
LED
no light
CPLD output pin+3.2 V R
Current
LED
light
R = voltage = 3.2 - 1.9 = 325 ohms current 4 x 10^-3
+1.9 V 0 V
0 V
0
1
R = 330 ohms
7-Segment Display
a b c d e f g
a b c d e f g
+5V
CommonAnode
CommonCathode
a
b
c
d
e
f
g
7-Segment Displaya
b
c
d
e
f g
a b c d e f g0 1 1 1 1 1 1 01 0 1 1 0 0 0 02 1 1 0 1 1 0 13 1 1 1 1 0 0 14 0 1 1 0 0 1 15 1 0 1 1 0 1 16 1 0 1 1 1 1 17 1 1 1 0 0 0 0
7-Segment Displaya
b
c
d
e
f g
a b c d e f g8 1 1 1 1 1 1 19 1 1 1 1 0 1 1A 1 1 1 0 1 1 1b 0 0 1 1 1 1 1C 1 0 0 1 1 1 0d 0 1 1 1 1 0 1E 1 0 0 1 1 1 1F 1 0 0 0 1 1 1
7-Segment Display
D a b c d e f g0 1 1 1 1 1 1 01 0 1 1 0 0 0 02 1 1 0 1 1 0 13 1 1 1 1 0 0 14 0 1 1 0 0 1 15 1 0 1 1 0 1 16 1 0 1 1 1 1 17 1 1 1 0 0 0 0
a
b
c
d
e
f g
a
b
c
d
e
f g
D a b c d e f g8 1 1 1 1 1 1 19 1 1 1 1 0 1 1A 1 1 1 0 1 1 1b 0 0 1 1 1 1 1C 1 0 0 1 1 1 0d 0 1 1 1 1 0 1E 1 0 0 1 1 1 1F 1 0 0 0 1 1 1
Truth tableseg7decD(3:0) AtoG(6:0)
K-Map for Segment e
1
1
1 1
1
D3 D2D1 D0
00 01 11 10
00
01
11
10
11
1
1
1D3 & D2 D1 & ~D0
~D2 & ~D0
e = D3 & D2 | ~D2 & ~D0 | D3 & D1 | D1 & ~D0
D3 & D1
case(D) 0: AtoG = 7'b1111110; 1: AtoG = 7'b0110000; 2: AtoG = 7'b1101101; 3: AtoG = 7'b1111001; 4: AtoG = 7'b0110011; 5: AtoG = 7'b1011011; 6: AtoG = 7'b1011111; 7: AtoG = 7'b1110000; 8: AtoG = 7'b1111111; 9: AtoG = 7'b1111011; 'hA: AtoG = 7'b1110111; 'hb: AtoG = 7'b0011111; 'hC: AtoG = 7'b1001110; 'hd: AtoG = 7'b0111101; 'hE: AtoG = 7'b1001111; 'hF: AtoG = 7'b1000111;
default: AtoG = 7'b1111110; // 0 endcase
7-Segment Display
a
b
c
d
e
f g
a
b
c
d
e
f g
Behavior
Verilog
seg7decD(3:0) AtoG(6:0)
module hex7seg(D,AtoG); input [3:0] D; output [6:0] AtoG;
reg [6:0] AtoG;
always @(D) case(D)
0: AtoG = 7'b1111110; 1: AtoG = 7'b0110000; 2: AtoG = 7'b1101101; 3: AtoG = 7'b1111001; 4: AtoG = 7'b0110011; 5: AtoG = 7'b1011011; 6: AtoG = 7'b1011111; 7: AtoG = 7'b1110000; 8: AtoG = 7'b1111111; 9: AtoG = 7'b1111011; 'hA: AtoG = 7'b1110111; 'hb: AtoG = 7'b0011111; 'hC: AtoG = 7'b1001110; 'hd: AtoG = 7'b0111101; 'hE: AtoG = 7'b1001111; 'hF: AtoG = 7'b1000111;
default: AtoG = 7'b1111110; // 0 endcase
endmodule
hex7seg.v
Veriloga
b
c
d
e
f g
// Title : Toggle switches to 7-Segment Display // Author : R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG); input [7:0] SW;
output [7:0]LEDR; output [6:0] AtoG; output [6:0] AAtoGG;
wire [6:0] AtoG; wire [6:0] AAtoGG;
wire [7:0] LEDR;
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
SW7seg.v Verilog
d7Lhex7seg
d7Rhex7seg
SW(7..4)
SW(3..0) [a,b,c,d,e,f,g]
[aa,bb,cc,dd,ee,ff,gg]
AAtoGG
AtoG
d7Lhex7seg
d7Rhex7seg
SW(7..4)
SW(3..0) [a,b,c,d,e,f,g]
[aa,bb,cc,dd,ee,ff,gg]
hex7segD(3..0) [a,b,c,d,e,f,g]= AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
Wiring up the top-level design in Verilog
AAtoGG
AtoG
d7Lhex7seg
d7Rhex7seg
SW(7..4)
SW(3..0) [a,b,c,d,e,f,g]
[aa,bb,cc,dd,ee,ff,gg]
hex7segD(3..0) [a,b,c,d,e,f,g]= AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
Wiring up the top-level design in Verilog
AAtoGG
AtoG
#PACE: Start of PACE I/O Pin AssignmentsNET "AAtoGG<0>" LOC = "p66" ;NET "AAtoGG<1>" LOC = "p65" ;NET "AAtoGG<2>" LOC = "p63" ;NET "AAtoGG<3>" LOC = "p62" ;NET "AAtoGG<4>" LOC = "p61" ;NET "AAtoGG<5>" LOC = "p58" ;NET "AAtoGG<6>" LOC = "p57" ;NET "AtoG<0>" LOC = "p17" ;NET "AtoG<1>" LOC = "p14" ;NET "AtoG<2>" LOC = "p19" ;NET "AtoG<3>" LOC = "p21" ;NET "AtoG<4>" LOC = "p23" ;NET "AtoG<5>" LOC = "p18" ;NET "AtoG<6>" LOC = "p15" ;NET "LEDR<0>" LOC = "p44" ;NET "LEDR<1>" LOC = "p43" ;NET "LEDR<2>" LOC = "p41" ;NET "LEDR<3>" LOC = "p40" ;NET "LEDR<4>" LOC = "p39" ;NET "LEDR<5>" LOC = "p37" ;NET "LEDR<7>" LOC = "p35" ;NET "SW<0>" LOC = "p1" ;NET "SW<1>" LOC = "p2" ;NET "SW<2>" LOC = "p3" ;NET "SW<3>" LOC = "p4" ;NET "SW<4>" LOC = "p5" ;NET "SW<5>" LOC = "p6" ;NET "SW<6>" LOC = "p7" ;NET "SW<7>" LOC = "p11" ;
SW7seg.ucf
hex7seg.v