lecture on technology scaling (r. dutton. b. murmann, stanford)
TRANSCRIPT
R. Dutton, B. Murmann 1
Lecture 29Technology Scaling–
Beyond EE114 MOSFETs
R. Dutton, B. MurmannStanford University
EE114
R. Dutton, B. Murmann 2
MOS Level 1 Figures-of-Merit (FoM)
Long Channel Model
ds
m
g
g
Current Efficiency
Transit Frequency
Intrinsic Gain
D
m
I
g
OVV
2=
2
OV
L
V
2
3 µ=
gs
m
C
g
OVV
2
!"
•Simplicity of Level 1 has allowed near-perfect accuracyin having hand-calculations and SPICE-simulations agree
•What are the trends in state-of-the-art MOS technology?
•What modeling and methodology is needed foradvanced MOS devices?
!
IDS =KP
2"W
Leff" VGS #Vt( )
2
" 1+ $VDS( )
Vt =VTO + % 2& #VBS # 2&( )
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1.8V 3.3V
CMOS core
I/O for HV interface
DE core for current sources
Ids
??
STIDrain-Extended
gm/gds
Trends in Scaling
BSIM
Different “flavors” of Transistors:Core Digital, I/O, Special Devices
(we’ll comeback to special
devices)
Two Problems:
•Decrease in intrinsic gain
•Bias dependent
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Dependence on VDS
• The long channel model predicts that gds and gm/gds areindependent of VDS
– As long as device is biased in active region
• This is also no longer true in modern devices– gds (and therefore gm/gds) shows a significant
dependence on VDS
VDS
ID
OP1
Slope = gds1OP2
Slope = gds2
Physical effects beyond“channel length modulation”critical
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Observations – Intrinsic Gain
• gm/gds shows a strong dependence on VDS bias
– Mostly due to varying gds
• There is a gradual transition from triode to active
– Long channel model would have predicted an abrupt changeto large intrinsic gain at VDS = VOV
– Typically need VDS > VOV + 4kT/q to ensure at leastmoderate intrinsic gain
• At high VDS, gds increases due to SCBE (substrate currentinduced body-effect); this causes a decrease in gm/gds
– Highly technology dependent, and usually not present inPMOS devices
– If you are interested in more details, please refer to EE316or a similar course
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The Good News
•Large improvements in fT
•Product of gm/Id times fT isbecoming sharper; closer tothe sub-threshold region
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MOS R&D Prototypes vs. Production Versions
ProductionPrototypes:
R&D PrototypeTechnology:
Non-classical structures, physics limited, drasticvariations, and higher cost
Power- and robustness-constrained, adaptive,billion-scale integration, gigaHz operation
65nm(2005)
45nm(2007)
32nm(2009)
22nm(2011)
16nm(2013)
11nm(2015)
30nm(2000)
20nm(2001)
15nm(2001)
10nm(2003)
7nm(2005)
5nm(?)
Ground Plane
BOX (<20nm)Bulk wafer
FD Si film
Ground Plane
BOX (<20nm)Bulk wafer
FD Si film
Source: Intel, ITRS
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Example--45 nm Technology Node
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
0.01 Fujitsu 45nm nodeL
eff=25nm (N)
35nm(P)1V
0.05V
Ids (
A/µm
)
Vgs
(V)
Data PTM
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
0
100
200
300
400
500
600
700
800
900
0.4V
0.55V
0.7V
0.85V
1VFujitsu 45nm nodeL
eff=25nm (N)
35nm (P)
Ids(µ
A/µ
m)
Vds
(V)
Data PTM
Published data;analysis K. Cao, ASU
•Vgs dependence more linear than quadratic
•Output conductance limits intrinsic gain
•Sub-threshold behavior limits gain and leakage
Sub-Vt
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Empirical Compact Models
2. Physical Parameters
Nch, Eta0, U0, Vsat, K1
estimated based on tech. specs.or extrapolated from data; thenrefined to fit typical IV curves
1. Tech. Specs.
Leff, Tox, Vth, VDD, Rds
(and Tsi for FinFET)
from literatureincluding ITRS
3. SecondaryParameters (~80)
either fitted orremained from
previous generations
Several Examples*:
•BSIM (UC Berkeley)--broadly used and supported (de-facto standard)
•PSP (Penn. State-Philips)--growing support (Europe)
•HISIM--strong support in Asia (Hiroshima U., Japan)
•PTM (Predictive Tech. Mod.)--evolution from BSIM (K. Cao, ASU)
*Compact Modeling Council (CMC) is an organization that benchmarks models
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Problems with Compact Models vs. Level 1
Circuits designed using hand calculations will typically show largediscrepancies between targeted specs and SPICE results
Specifications
Hand Calculations
Circuit
Spice
Results
Square Law
BSIMBSIM, PTM
EE114Model
EE214Model
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Alternative Approach (Solution…EE214)
Use pre-computed SPICE data in hand calculations
Specifications
Hand Calculations
Circuit
Spice
Results
Design Charts
BSIM
SpiceBSIM
CompactModel:
BSIM,PSP,
PTM…
BSIM, PTM…
Must be same
model!
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Example--Intrinsic Gain Simulation (VDS)
* gm/gds versus vds
.param vt1=571.5m
mn1 d g 0 0 nch214 L=0.35um W=10um
vg g 0 dc 'vt1+0.2'vd d 0 dc 1.5
.op
.dc vd 0 3 10m
.probe gm1 = par('gmo(mn1)')
.probe gds1 = par('gdso(mn1)')
.options post brief
.lib './ee214_hspice.txt' nominal
.end
VGS=V
t+200mV
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Results
0 1 2 30
0.5
1
1.5x 10
-3
VDS
[V]
gm
[S]
0 1 2 30
2
4
6x 10
4
VDS
[V]
1/g
ds
[!]
0 0.5 1 1.5 2 2.5 30
10
20
30
40
50
60
70
80
NMOS, W/L=10/0.35, VOV
=200mV
VDS
[V]
gm
/g d
s
Intr
insi
c G
ain
Vds
Ids-Vds
(see commentabout VOV + 4kT/q)
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Example--fT Simulation
* ft versus gate overdrive
.param gs=1
vds d 0 dc 1.5Vvgs g 0 dc 'gs'mn1 d g 0 0 nch214 L=0.35um W=10um
.op
.dc gs 0.4V 1.2V 10mV
.probe ov = par('gs-vth(mn1)')
.probe ft = par('1/2/3.142*gmo(mn1)/(-cgsbo(mn1))')
.options post brief dccap* Note: "dccap" forces HSpice to recalculate caps in* each simulation step (instead of using constant .op* value). See HSpice manual for additional info.
.lib './ee214_hspice.txt' nominal
.end
10/0.35
VDD/2
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Results
22
3
2
1
L
Vf OVT
µ
!=Long channel model:
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50
5
10
15
20
25
30NMOS W/L=10/0.35
VO V
[V]
fT [
GH
z]
EE214 technologyLong Channel FitEE114 technology
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More About Device Technology
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50
5
10
15
20
25
30
35
40
VOV
[V]
gm
/I D [S/A]
EE214 technology
2/VOV
BJT (q/kT)Subthreshold
Operation
EE114 technology
Transition
Region
Sca
led
Tra
nsc
on
du
ctan
ce (
gm
/Id
s)
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Moderate Inversion
• In the transition region between subthreshold and stronginversion, we have two different current mechanisms
dx
dn
q
kT
dx
dnD - (BJT)Diffusion
E - (MOS)Drift
µ!
µ!
==
=
• Both current components are always present
– Neither one clearly dominates around Vt
• Can show that ratio of drift/diffusion current ~(VGS-Vt)/(kT/q)
– MOS equation becomes dominant at several kT/q
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Mobile Charge on a Log Scale
• On a log scale, we see that there are mobile charges before wereach the threshold voltage– Fundamental result of solid-state physics, not short channels
1.E-16
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
-1.00 -0.50 0.00 0.50 1.00
VOV [V]
Mo
bile C
harg
e [
C]
(where is Vt onthis plot?)
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BJT Similarity
• We have– An NPN sandwich, mobile minority carriers in the P region
• This is a BJT!– Except that the base potential is here controlled through a capacitive
divider, and not directly an electrode
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Subthreshold Current
• We know that for a BJT
)//( qkTVSC
BEeII !"
• In MOS case we have)//()(
0qnkTVV
DtGSeII
!"#
• n is given by the capacitive divider
ox
js
ox
oxjs
C
C
C
CCn +=
+= 1
where Cjs is the depletionlayer capacitance
• In EE214 technology n ≅ 1.5
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Subthreshold Transconductance
• Similar to BJT, but unfortunately n (≅1.5) times lower
kT
qI
ndV
dIg D
GS
Dm
!==1
kT
q
ndV
dI
I
g
GS
D
D
m 1==
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50
5
10
15
20
25
30
35
40
VOV
[V]
gm
/I D [S/A]
EE214 technology
2/VOV
BJT (q/kT)~1.5x
(where did thisvalue come from?)
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Other Issues (and Research Perspective)
There are many, many other issues:
•Distortion
•Noise
•Emerging Technologies (“more than Moore”)
•Analog vs. Digital Scaling
THE Issues facinganalog scaling
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Noise in Electrical Elements
• Noise is unwanted signal fluctuations.– Equilibrium: Thermal noise (PSD=4kTg)– Non-Equilibrium: Who knows?
Equilibrium(thermal noise)
R=1/g 4kTg A famous Non-equilibrium case (shot noise)
ID 2qID
PSD
f
22,nnVI
Ec
N P
x
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Noise in MOSFETs
• MOSFET noise sources:Drain
Source
Gate inding
f
ind
!
2
f
1/f noise
White noisef
ing
!
2
f!
" Cgs#( )2
CarrierFluctuations
N+ N+
GateSource Drain
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MOSFET Noise Formulation
• Classical long-channel formulation:
( ) dond gkTf
i3/24
2
=!
( )( )dogs
nggCkT
f
i5/3/44
22
2
!="
j
ii
ii
ngnd
ngnd395.0
22
=
N+ N+
GateSource Drain
2
2
)(
4!"
#$%
&!"
#$%
&=
R
dR
dR
kTId eqn
dR
(Equilibrium Noise)
γ
δ
(a different“gamma”)
(correlation ofdrain and gate
noise)
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“What if” MOS Scaling* (45nm)
NML(increase L)
Asymmetry(omit HALO)
•Source/Drain dopinglevels and junctiondepths, based on ITRSprojections•Lateral dopingprofiles adjusted toachieve the necessarysub-threshold slope
*Dutton research group (TCAD) simulations
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TCAD Simulations: ML-, A-, NML-devices
•Minimum Length (ML)device follows traditionalscaling (Well-Tempered)•Non-ML (NML) devicebacks off on channellength (from minimum)but retains both HALOimplants•Asymmetric device (A)removes the drain-sideHALO and adjusts spacingto maintain sub-thresholdslope
(45nm)
NML
A Dev.
Intr
insi
c G
ain
(gmr o
)
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Looking at each part separately…
gm ro
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A Random PhD Quals Question
A device technologist has created aNEW DEVICE*-- part MOS, partBJT--and with “drive current”given by:IDrive=ID(MOS)+IC(BJT).The device cross-section is shownbelow
To achieve maximum small-signal (ac) gain, how shouldwe bias the NEW DEVICE?
Cgs C!
VinVout
RS
NEW
DEVICE
*Comment: you might ask THEcritical question, “is this device reallyuseful?” (I.e. what is the down-side ofdoing this, aside from technology)
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Hypothetical MOS-BJT Device
LL
Gate 1
Gate 2(=Base)
Common
(Ground)Output
Node
W
N+
P-typeN+
COX (F/cm2)=
4x10-6 F/cm2
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(dc) Log I vs V--MOS vs BJT
Log 1
0 I (I
DS o
r IC)
Drive Voltage(VGS or VBE)
slope =q/kT
“sub
-Thr
esho
ld”
“power-law”
~(VGS-VT)m
VT
MOS
BJT
!
gm "#Ioutput
#Vinput$drive
(Larger slopeimplies larger gm)
VBE(on)
!
"eVBE
Vthermal#
$ %
&
' (
!
"eVGS
mVthermal#
$ %
&
' (
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R. Dutton, B. Murmann 32
Summary
•It’s not likely that this lecture covered all the slidesshown above but…what’s important?
•EE114 technology has made it (relatively) easy to get amatch between hand-calculations and SPICE but…MOSscaling is creating much more complex devices (practicalmodels are now primarily empirical)
•EE214 technology and modeling will deal with thesecomplexities using a methodology that creates designcurves (I.e. gm/Id etc.) that can match SPICE and supportpractical circuit design
•Other issues--distortion, noise, etc.--are critical and willbe addressed as well (ongoing challenges for research)
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