Device Modeling and Simulationfor VLSI Design

Robert W. DuttonStanford University

•Introduction--TCAD•Moore’s Law Scaling using TCAD:

Intrinsic DevicesIsolation (and other Parasitic) Effects

•Kinds of Modeling :Technology Design (Scaling and SPICE Files)

Behavior Modeling (ESD, RF & Substrate Coupling)

•Future Scaling Issues•Transition to SyCaMore Project SyCa More

Circuit

Device

Process

Technology Files

Characterization

Device Scaling

Masks

Interconnects

Isolation

Technology Computer-Aided Design=TCAD

Extrinsic (and Layout) Intrinsic (active/passive devices)

EDA/TCAD Boundaries

IC Layout

Circuit Design & Verification

Process Technology

Device & Interconnect Design

Extraction & ERC

Behavior Models

Behavior Models

SPICE Models

SPICE Models

ECAD

TCAD

(EDA=Electronic Design Automation)

Transistor Scaling versus Year--Moore’s Law

Gate Length (L) decreases witheach technology generation…

Density of gates doubles with each generation…

Cost per transistor isreduced (~ 1/Density)...

0.4

0.3

0.2

0.1

0.0 | | | | | | | | | | | | | | | |1995 2000 2005 2010

Gat

e L

engt

h (m

)

Year

L

=

=

=

Figure 1

Density of IC devices is doubling with each new

generation

Gordon Moore

Robert Dutton, Fairchild Fellow (Cal gEEk, circa-1967)

Figure 2

Moore Dutton Grove

Moore’s Law and Scaling (what are the limits?)

0.4

0.3

0.2

0.1

0.0 | | | | | | | | | | | | | | | |1995 2000 2005 2010

Gat

e L

engt

h (

mm

)

Actual Oxide Atoms

Wavelength at 193 nm

Year

Growing demandson Equipment side

Growing challengeson Materials side

=100 nm

IC Scaling Issues--Front-End, Back-End

& Substrate

Intrinsic Devices:•Junctions•Contacts•Dielectrics

Substrate Engineering:•Parasitics•Packaging

Back-End Simulation:•Multi-layer materials•Electro-Thermal

} Need for New, Faster, Smaller Transistors…

TCAD-based Model Extraction (for SPICE)

Simulations (and Measured Data) of I-V, C-V and transient behavior of Scaled Devices

TCAD

TCAD

Extraction of key SPICE parameters for “compact models” (i.e.

MOS level 3, BSIM…) that are the: “technology file” used for circuit design.

Scaling Effects in MOS--Quantum Mechanical Limits

-1.5 -1 -0.5 0 0.5 1 1.5Vg (V)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

Ig (A)

13A, measured15A, measured18A, measured12.5A, simulated15A, simulated18A, simulated13A, NEMO sim15A, NEMO sim18A, NEMO sim

-3.0 -2.0 -1.0 0.0 1.0 2.0Vg (V)

0.0

50.0

100.0

150.0

200.0

Cg (pF)

tox=15A

: Experiment from HP: QM model

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5Vg (V)

0

5e-07

1e-06

1.5e-06

Cg (F/cm

2)

tox=21A, Npoly=6E19 cm-3

MeasuredDGClassicalNEGF

tox=21A tox=15A

tox=15A

Log

Ig

Vg=0MOS C-V and “gate current”:

Classical for >20Angstroms

Tunneling through gate--Changes C-V

Gate current BIG problem

Challenges on the Road Ahead

100 nm

There are a range of physical, chemical andmaterials changes as IC technology moves intothe sub 100 nm regime

• Intrinsic Devices– Thin oxides– High-dielectrics– Dopant Statistics– Alternatives (single electron, pillars, heterojunctions...)

• Extrinsic Devices– Trenches– Materials (metals, Low-...)– Stress– Alternatives (free space, flip-chip, use of MEMS...)

Future Scaling Issues

metal bitlinevoid/air gap in intermetal dielectric

Si pillar Si pillar Si pillarpoly Si poly Si

metal bitline metal bitline

Interconnect Technology

BeyondScaled-CMOS

Challenges at Atomic Scale(21st Century TCAD and MOS Scaling Limits)

Xox

Silicon

Gate

Fundamental Changes:

Atomic ScalesNew MaterialsBeyond Planar:Pillars3D devicesNano-tubes . . .

Honto nichisaku nattene!

(or in English)

Things are reallygetting small!

Synthesized Compact Models (SyCaMore) for Mixed Signal Design and Noise Analysis

Robert DuttonStanford University

SyCa MoreD A R P A

• Introduction

• Highlights & Project Status:– Algorithms and Model Generation

– Test Circuits for Model Validation

• Plans

Karti MayaramOregon State University

&

What is the “substrate noise” problem?why is it important?

(Atheros, ISSCC 2002,Paper 7.2)

(Atheros, ISSCC 2002,Paper 5.4)

Atheros•Interest in single-chip integration issues

•Using state-of-the-art foundry technology

Digital blocks represent most of the chip; they generate LOTS of switching noise

The radio has very sensitive analog (RF) blocks that don’t like noise!!

Introduction--RF/Mixed-Signal Noise Coupling

VCO Phase Noise

Noise spectra and coupling mechanisms depend on:– Circuit configurations--including layout & technology– Distributed device effects– Substrate behavior (including nonlinear effects)

VCO Digital Block

Substrate Transfer Function

Digital Spectrum

FrequencyFrequency

Noise couples via transistor bulk

regions (gmb)

“Phase Noise” means that frequency of VCO is not exact (=system problem)

Focus of the SyCaMore Project…

Oscillations and Voltage-Controlled Oscillators

Feedback perspective A=a/(1-af), if af=1 we get infinite gain…or oscillations

From EE 122 the phase-shift oscillator specifically uses series-parallel RC network to:

Make |f|=1/|a| and

Guarantee exact 0-degree phase shift

Timing-based oscillations--this can be “ring oscillator” type or “charge-discharge” (of Capacitance) type

Example of Phase-Shift Oscillator (EE122)

s (=j)

Reminder abouts-plane and polesmoving into eitherLHP or RHP

R1

R2

(-)(+)

InvertingGain amp.Av~ -R2/R1 Phase-shift

Network=0 and fo

and attenuatingby 1/Av

Basics of Timing-based Oscillators

+Vcc

Control Logic:S1 on (S2 off)

ThenS2 on (S1 off)

S1

S2

C

Timer Circuits:•Schmitt Trigger•555 IC•Many others...

I =CdVdt

CΔV

xI= xT

“x” is the portion of thetotal period for which therespective “Ix” is in control

T1 T2Time

V

Making a Voltage-Controlled (Ring) Oscillator

Vdd

VoltageControl (for Ix)

Oscillator(“ring” type)

Basic Point:Frequency of Oscillations directly proportional to the Current (Ix) which in turn is Controlled by a Voltage (see previous slide about “timing)

A word about PLLs (and role of VCO)

-to-

VCO

i i

osc

Key Objective of Phase-Locked Loop:Use the “phase comparator” block (X) to keep “red” VCO doing exactly what the incoming signal is doing. This can either: a) guarantee “clock synchronization” or

b) “demodulate” FM signals (coming from “green”).

oVCOi

Input: voice signals…

Output: FM-modulated signals…

o

Test Structures--Create Digital Noise Emulation (DNE) blocks and study the effect of digital noise on Phase-Locked Loops (PLLs)

Power-Current profiles:•Bluetooth (Atheros)•Multiple Freq. Synth. (IBM)

Digital 1Digital 2

Analog 1

Dig

ital

3

Dig

ital

4

Ana

log

2

(Atheros, ISSCC 2002,Paper 7.2)

CounterMulti-outputs su

bstr

ate

Simulation: •Verify noise behavior• Parameterize DNE’s

Hardware Version of DNE:

Test Chip Implementation:•Programmed DNE (parameterized based on digital application domain)•Suitable RF/Analog block(s)

DNE2

DNE1

DNE3

A1

A4A3

A2 Barcelona PLLs

Digital Noise Emulators

ProgrammedDigital Noise

Emulator

Modeling Digital Noise --how does “digital noise” get modeled, both in time and frequency domains

Gate Level Simulator

Total Current Waveform

FFT Analysis

NoiseSpectrum

inputsPower Information

(->Current Spikes) I peak

T

P

| | | | | | |0 0.5 1.0 1.5 2.0 2.5 3.0 Freq. (GHz)

0

−20

−40

−60

−80

Spe

ctru

m [

dBm

A]

Aggregation of block-level currents, based on power estimates, provides parameters of current injection. Transform to frequency-domain give good measure of noise spectrum.

time

Tot

al C

urre

nt

Current Noise Models--simulation and mathematical

Objective: Create mathematical model for current noises on supply rails….

• Basic conceptInoise(t)=Id,sat

1*(fitted curve for transition curve of switch)2

1 : the quadratic model for simplification.

2 :

• ExampleCurrent noise in the supply of an

inverter with trise=tfall=400psRed : Mathematical modelBlue : SPICE simulation

parametersfittingbabta

=+−

,2

1))(tanh(

What happens when a CMOS gate switches?

Current Pulse on Vdd

Behavior simulation--PLL with digital noise(flow chart of models, tools and key results)

Mathematical current

noise model

Voltage noise model

PLL simulationwith noise model

Output spectrum using MatLab

Taking derivative(modelingdi/dt noise)

Adding to VCO input (most sensitive

block in PLL)

Substrate Network Noise Injection (lumped model) Circuitry

VCOIdd CurrentGnd Current

Noise Model:Frequency of the inverter switching, 17MHzPLL:

Reference frequency : 150MHzCenter Frequency : 4.5GHzSampling time : 100ps

Results:Even and Odd harmonics of 17MHz observable with different

amplitudes.

Here’s simulations of PLL frequency response based on substrate noise coupling

Modeling Distributed Substrate Effects--coupled simulation (including automated extraction of models)

Plug-and-Play with Device Simulators:•New materials•New classes of devices and physical coupling effectsAutomated Extraction:

•Maintain physical mapping and technology dependencies•Allows parameterization based on layout details

SPICE Circuit Simulation:

Analysis stageSolution vector

Circuit matrix & RHS

Analytical devices Compact Models

Numerical devicesDevice Simulator(s)

CO-DEvice-Circuit Sim.

1

2

VddVOUT RL

numerical (2D)substrate model

2

1

A Simple Example--CODECS Simulations(two-tone results: complete device and resistor-lumped model)

1

2

VddVOUT RL

2

1VddVOUT RL

RSUBone-lump R

Using two frequencies 1 (gate) and 2 (substrate) what are the observed “tones” at VOUT?•Additional tones mean that there are nonlinear (distortion effects)•Differences between complete 2D device level and lumped model means distributed effects are important

Numerical model for substrate One-lump resistive model for substrate

Simulation Results-- MOSFET Substrate Noise

1KHz

2KHz

1MHz

2MHz

Input Signal Substrate

Signal

3MHz

Frequency Domain Spectrum -- (substantial differences between full numerical and lumped substrates)

Modeling of Substrate Parasitics--a more detailed study of topological effects

• Rsub from numerical simulation of the lateral portion of substrate

Numerical Model

Two Alternative ModelsFor Substrate Resistor

+n +np

+p

S G D B

RsubB′

+n +np

S G D

BRsub

B′+p

+n +np

S G D

B

Rsub

B′

Two-tone CODECS Analysis --First Model

Vin=2+0.4sin(2π ⋅1×103⋅t)

Vsub=0.4+0.4sin(2π ⋅1×106⋅t)

DG

S

B

5V

ΩK1

inV sub

V

outV

Spectrum of outV

Next...

+n +np

S G D

BRsub

B′+pdistributed lumping

Spectre time domain simulations and H&L* analysis for uncorrelated substrate noise injection show jitter peaks at: – n0 (for asymmetric)

– 5n0 (for symmetric)

Oscillator Jitter--Simulations and Analysis (comparisons of symmetric versus asymmetric noise injection)

*H&L--Hajimiri and Lee, The Design of Low Noise Oscillators, Kluwer Academic Press, 1999

0 w0 2w0 3w0 4w0 5w0 6w0 7w0 1

10

100

Frequency of Injected Noise

Peak Jitter (ps)

H&L Spectre

0 5w0 10w0 15w0 20w00.1

1

10

100

Frequency of Injected Noise

Peak Jitter (ps)

H&L Spectre

==

2 112

Model Generation--Synthesized Compact Models (SCMs) for the Substrate Effects

0 5000 10000 15000 200000

5000

10000

15000

20000

X (? m)

(Y?

)m

8

9

1

11

Digital Source Nodes

Coarse Mesh Analysis: •Provides automated element mapping •Includes aggregation of contact effects

Ana

log

Sen

sing

N

ode

Lmas

k

Parameterized Netlist of Components

…..…..D_trap 4 1 trap_modelC1 1 4 scale_fact.1-X-F/cm^2C2 4 2 scale_fact.2-X-F/cm^2R_sub1 4 2 scale_fact.3-X-OhmsR_sub2 4 5 scale_fact.4-X-Ohms.model trap_model D (Is=# TT=# …)

Parameterized Netlist of Components

…..…..D_trap 4 1 trap_modelC1 1 4 scale_fact.1-X-F/cm^2C2 4 2 scale_fact.2-X-F/cm^2R_sub1 4 2 scale_fact.3-X-OhmsR_sub2 4 5 scale_fact.4-X-Ohms.model trap_model D (Is=# TT=# …)

Parameterization of SCMs:•Geometry based on Layout (which can in turn be driven by synthesis)

•Quantified number of lumps (based on 3D TCAD simulations)

•Characteristics of Substrate (extracted from 3D TCAD)

Parameterization of SCMs:•Geometry based on Layout (which can in turn be driven by synthesis)

•Quantified number of lumps (based on 3D TCAD simulations)

•Characteristics of Substrate (extracted from 3D TCAD)

Lumped (SCM) Network: •Physical-based topography; number of lumps frequency dependent •Layout dimensions used to scale resistor; provides bi-directional link

Time to Summarize…

• Simulations and (TCAD) Modeling are useful for Scaling ICs--Moore’s Law and Beyond:– Basic Transistor behavior (including technology scaling)– Extracting SPICE models– Understanding Parasitic Effects

• Substrate Noise Coupling is Key Challenge for future System-on-Chip (SoC) Integration:– Analog blocks are very sensitive (especially RF components)– Modeling of substrate coupling involves: TCAD-, SPICE- and

Behavior-Level representations

• Thanks REUs!!– Justin– Jason– Jiambo– Qi

Where I’ll be Aug. 18-23, 2002

Dinner!

We’reToo little!