Jaeyong Chung

System-on-Chips (SoC) Laboratory

Incheon National University

Digital Integrated Circuits

Lecture 6

S/W controls fixed, versatile CPUs

H/W Design: Create small, specialized task-processing

units and then design a controller, which itself is also

hardware

S/W vs. H/W Design

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RAM

01011..11111..…

int main() {int c;c = 10*2;

}

controller

ALU +

*

RAM

ROM

Reg

A Common Design Practice Decomposes the System in Two Parts:

A Datapath: a collection of interconnected modules that perform all the relevant

computation on the data: it can use both combinational and sequential components

A Control Unit: Coordinates the behavior of the Datapath by issuing appropriate

control signals that guarantee the correct sequence of operations: it is typically

designed as a single or cooperating FSM

Digital Systems Get Work Done Efficiently by Controlling (Allocating and

Scheduling) Datapath (Resources)

3

Controller Datapath

Control

Signals

Status

Signals

Inputs Outputs Inputs Outputs

One Standard Template of Digital Systems

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DATAPATH

Performs specified tasks for given data

Manipulates and processes data

Performs arithmetic and logic operations,

shifting/rotating, and other data-processing tasks

Is composed of registers, multiplexers, adders,

decoders, comparators, ALUs, gates, etc.

Provides all necessary resources and interconnects

among them to perform specified task

Interprets control signals from the Controller and

generates status signals for the Controller

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CONTROLLER

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Controls data movements in the Datapath by

switching multiplexers and enabling or disabling

resources

Provides signals to activate various processing tasks

in the Datapath

Example: enable signals for registers

Example: control signals for muxes

Determines the sequence of operations performed by

the Datapath

Follows Some ‘Program’ or Schedule

1. Break Mission or Specification Down Into Smaller

Tasks

2. Find Common Tasks

Done by Well-known Datapath Components

e.g., Adder, Multiplier, Divider, Shifter,

Comparator, etc

3. Determine Number of Each Type of Component

Needed

4. Connect Them Considering Order of Tasks

5. Design a FSM Controlling Datapath

Schedule & Allocate Components for Tasks

6

PARTITIONING INTO DATAPATH AND

CONTROLLER

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DETERMINE NUMBER OF

RESOURCES

Can get work done faster by using more resources

(e.g., adders and multipliers)

Need to decide how many resources to use

Trade-off between processing time and cost (e.g,

# of counters in a store)

Resources are usually shared over time

The lesser resources are available, the longer the

processing time is (e.g, # of counters in a store)

Number of resources has impact on the complexity of

the controller

The controller gets often more complex when a

smaller number of resources is used

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DETERMINE NUMBER OF

RESOURCES

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Example: A simple processor

add 4 3

add 5 8

sub 2 3

sub 5 3

mul 5 4

mul 10 4

…

…

ALU

add 4 3

sub 2 3

mul 5 4

…

…

ALU

program

counter

add 5 8

sub 5 3

mul 10 4

…

…

ALU

program

counter

RAM RAM

Parallel Processing!

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DETERMINE NUMBER OF

RESOURCES

Example: A 2nd order FIR Filter (i.e. 3 taps)

Y[n] = h[0]x[n] + h[1]x[n-1] + h[2]x[n-2]

Parallel vs. Serial FIR Filter

9

Z-1

Z-1

h[0]

h[1]

h[2]

y[n]

x[n]

x[n] X[n]

X[n-1]

X[n-2]

h[0]

h[1]

h[2]

RAM

ROM

0-2

counterZ-1

Parallel Serial

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Two Dice – Each with Value 1 to 6

After First Roll of Dice

Player Wins If Sum 7 or 11

Player Loses If Sum 2, 3, or 12

Otherwise, Sum Obtained on First Roll

Referred to as Point

► Must Roll Again

On Second or Subsequent Roll of Dice

Player Wins If Sum Equals Point

► Loses If Sum 7

Otherwise, Roll Again Until Win or Lose

10

DICE GAME

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1-to-6

Counter

1-to-6

Counter

Dice Game Module

Outcome 1 Outcome 2Roll Win Lose

Reset Rb

RollRestart

DICE GAME SPECIFICATION

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BCD TO 7-SEGMENT DISPLAY DECODER

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BCD TO 7-SEGMENT DISPLAY DECODER

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BCD TO 7-SEGMENT DISPLAY DECODER

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BLOCK DIAGRAM FOR DICE GAME

Architecture (Data Path)

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BLOCK DIAGRAM FOR DICE GAME

D7 = 1 if Sum of Dice 7

D711 = 1 if Sum of Dice 7 or 11

D23l2 = 1 if Sum of Dice 2, 3, or 12

Eq = 1 if Sum of Dice Equals Number Stored in Point

Reg

Rb = 1 when Roll Button Pressed

Reset = 1 when Reset Rutton Pressed

Roll = 1 Enables Dice Counters

Sp = 1 Causes Sum to be Stored in Point Register

Win = 1 Turns on Win Light

Lose = 1 Turns on Lose Light

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=?

=2? =3?

=7? =11?

=12?

Outcome 1 Outcome 2

Point

Register

Sp

D7 D711 D2312

EQ

EXTRACTING DATAPATH

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D7 D711 D2312

Sp Roll

Rb Reset

Win Lose

s0

s2

Win

s3

loses1

s4

s5

Rb’D711

Rb’

Rb’

Rb/Roll

Rb/Roll

Rb’D2312

Rb’D711’D2312’/Sp

Rb’D7/RollRb’Eq

Reset’Reset’

Reset Reset

DESIGNING FSM TO CONTROL THE DATAPATH

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`define STATE0 3'b000`define STATE1 3'b001`define STATE2_WIN 3'b010`define STATE3_LOSE 3'b011`define STATE4 3'b100`define STATE5 3'b101

module dice_game (rb, reset, clk, outcome0, outcome1, roll, win,lose);input rb, reset, clk;input [3:0] outcome0, outcome1;output roll, win, lose;

reg [2:0] state;reg [2:0] next_state;reg [3:0] point;reg roll, win, lose, sp;wire [4:0] sum;

// DATAPATHassign sum = outcome0 + outcome1;assign D7 = (sum == 7);assign D711 = (sum == 7) | (sum == 11);assign D2312 = (sum == 2) | (sum == 3) | (sum == 12);assign EQ = (sum == point);

always @(posedge clk) beginif(sp == 1) beginpoint <= sum;

endend

State Encoding

Module I/ODeclaration

Registers and Wires Declaration

Combinational logic ofDatapath

Sequential logic ofDatapath

DESCRIBING DATAPATH IN VERILOG

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// CONTOLLERalways @ (rb or reset or sum or stateor D7 or D711 or D2312 or EQ) begin

sp = 0; roll = 0; win = 0; lose = 0;if(reset == 1) beginnext_state = `STATE0;

endcase(state)`STATE0 : begin

if(rb == 1)next_state = `STATE1;

end`STATE1 : beginif(rb == 1)roll = 1;

else beginif(D711)next_state = `STATE2_WIN;

else if (D2312)next_state = `STATE3_LOSE;

else beginsp = 1; next_state = `STATE4;

endendend`STATE2_WIN :

…endcase

endalways @(posedge clk) beginstate <= next_state;endendmodule

Sensitivity list

Case StatementDescribing Behaviors of Each State

Define Initial State

Sequential Logic of Contoller

Combinational Logic of Controller

DESCRIBING FSM IN VERILOG

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DICE GAME WITH TEST BENCH

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TEST BENCH

Initially Supply Rb Signal

When DiceGame Responds with Roll Signal

Supply Sum Signal which Represents Sum of

Two Dice

If No Win or Lose Signal Generated by DiceGame

Repeat Steps 1 and 2 to Roll Again

When Win or Lose Signal Detected

Generate Reset Signal and Start Again

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module t_dice_game (rb, reset, sum, clk, roll, win,

lose);

output clk;

input roll, win, lose;

output rb, reset;

output [3:0] sum;

reg [1:0] t_state;

reg [1:0] t_next_state;

reg [3:0] sum;

reg rb, reset, clk;

reg trig1;

integer sumarray[11:0];

integer idx;

//idx initialized to 0

initial begin

sumarray[0] = 7; sumarray[1] = 11;

sumarray[2] = 2; sumarray[3] = 4;

sumarray[4] = 7; sumarray[5] = 5;

sumarray[6] = 6; sumarray[7] = 7;

sumarray[8] = 6; sumarray[9] = 8;

sumarray[10] = 9; sumarray[11] = 6;

idx = 0;

t_next_state = 2'b00;

reset = 1;

clk = 0;

end

always @ (roll or win or lose or t_state) begin

case(t_state)

2'b00 : begin

rb = 1; //wait for roll

reset = 0;

if(idx >= 12) begin

t_next_state = 2'b11;

end

else if(roll == 1) begin

sum = sumarray[idx];

idx = idx + 1;

t_next_state = 2'b01;

end

end

2'b01 : begin

rb = 0;

t_next_state = 2'b10;

end

2'b10 : begin

t_next_state = 2'b00;

if((win == 1) | (lose == 1)) begin

reset = 1;

end

end

2'b11 : begin

end //top state

default : $display("Please check the states!");

endcase

end

TEST BENCH

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always @(posedge clk) begin

t_state <= t_next_state;

end

always begin

clk <= #20 !clk;

end

endmodule

TEST BENCH

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module b_top;

wire rb, reset, clk;

wire [3:0] sum;

wire roll, win, lose;

dice_game i_dice_game (.rb(rb), .reset(reset), .clk(clk), .sum(sum), .roll(roll), .win(win), .lose(lose));

t_dice_game i_t_dice_game (.rb(rb), .reset(reset), .sum(sum), .clk(clk), .roll(roll), .win(win), .lose(lose));

endmodule

TEST BENCH

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SIMULATION RESULT

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