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Lecture 3: Logic circuit Combinational circuit and sequential circuit TRAN THI HONG HONG IS.NAIST.JP

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Page 1: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Lecture 3: Logic circuit

Combinational circuit and sequential circuit

TRAN THI HONG

HONG@ IS.NAIST.JP

Page 2: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Content

Lecture 1: Computer organization and performance evaluation metrics

Lecture 2: Processor architecture and memory system

Lecture 3: Logic circuit: Combinational circuit and sequential circuit

Lecture 4: Number system and Its Importance

Lecture 5: Hardware design by HDL

Lecture 6: Parallel programming

Lecture 7: Hardware design by high-level synthesis

Lecture 8: Computer system design and its applications

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Page 3: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Lecture Information

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Page 4: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Grading (評価)Mini-test (40%) Score is based on the number of times that you attend the class and your

enthusiastic on doing mini-test.

You may get MAX score although your answer is not correct!

If you cannot attend the lecture with reasonable reason (ex: attend conference), you can get MAX score if you: Inform about your absent to me via email: [email protected]

Study from lecture video and submit mini-test by next time.

Home-work: (60%) Score is based on the correction of your home-work

Bonus (+10%) Your activeness, enthusiastic during the lecture (make question, answer the question,

etc.)

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Page 5: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Basic Logic Circuits

Basic Logic Gates: Not, And, Or, Xor, Xnor, etc.

Combinational Circuits

Arithmetic Operator: adder, multiplier, etc.

Encoder

Multiplexer

Comparators

Sequential Circuits

Memory Elements: Latch, FlipFlop, Register, etc.

Sequential Circuits

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Page 6: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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brick

Page 7: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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Transistor

Page 8: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Overview of Hardware Circuit Design

Block

1

Binary Logic gate:

Not, And, Or, etc.

Transistors

System Block

2

Block

N…

Comb. Circuit: Do specific

function.

Seq. Circuit: Register,

memory, etc.

Adder Mul.

MUX Comp.

Latch Flipflop

Comparator

Adder Register Memory

Hardware System

Analog

Circuit

Design

Digital

Circuit

Design

Verilog HDL

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Page 9: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Transistor There are several types of transistor such as:

Bipolar junction transistor (BJT)

Field-Effect Transistor (FET)

Junction gate FET (JFET)

Metal-Oxide Semiconductor (MOS)

MOSFET

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Page 10: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Basic Logic GatesNOT Gate

Logic gates are the element building blocks of a digital circuit.

Basic element of logic gate is transistor

NOT gate is built from 2 MOS transistors

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Symbol

True-Table

0 1

1 0

Circuit

Page 11: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

NOR gate is built from 4 transistors: 2 p-type in serial and 2 n-type in parallel

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Basic Logic GatesNOR Gate

01

0

10

1

Circuit

Symbol

True-Table

Page 12: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

OR gate is built by adding a NOT gate into NOR gate

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Basic Logic GatesOR Gate

NOR

NOT

00

0

11

1

Symbol

True-Table

Circuit

Page 13: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

NAND gate is built from 4 transistors: 2 p-type in parallel & 2 n-type in serial

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Basic Logic GatesNAND Gate

Circuit

Symbol

True-Table

Page 14: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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Basic Logic GatesAND Gate

NAND

NOT

Symbol

True-Table

Circuit

Page 15: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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Basic Logic GatesXOR Gate

Symbol

True-Table

Circuit

Page 16: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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Basic Logic GatesXNOR Gate

Symbol

True-Table

Circuit

Page 17: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Minitest-3.1How many p-type, n-type CMOS transistors are needed for building:

NAND gate

OR gate

XOR gate

XNOR gate

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Page 18: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Minitest-3.1: Answer How many p-type, n-type CMOS transistors are needed for building:

NAND gate: 2 p-type + 2 n-type CMOS transistors

OR gate: 3 p-type + 3 n-type CMOS transistors

XOR gate: 4 NOT + 2 NAND + 1 OR = 4 (1p + 1n) + 2 (2p + 2n) + 1 (3p + 3n) = 11 p-type + 11 n-type transistors

XNOR gate: 11 p-type + 11 n-type transistors

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Page 19: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Basic Logic Circuits

Basic Logic Gates: Not, And, Or, Xor, Xnor, etc.

Combinational Circuits

Arithmetic Operator: adder, multiplier, etc.

Encoder

Multiplexer

Comparators

Sequential Circuits

Memory Elements: Latch, FlipFlop, Register, etc.

Sequential Circuits

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Page 20: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Combinational Circuits- Arithmetic Circuits - (1/4)

Basic operator: adder

Subtractor is the adder of negative number.

Multiplier is the sum of multiple adders

Divider is very complex and rarely used in hardware design.

Half Adder

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Page 21: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Full Adder

Input Output

Combinational Circuits- Arithmetic Circuits - (2/4)

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Page 22: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

A0 B0 A1 B1 A2 B2 A3 B3

S0 S1 S2 S3 C3

Half

Adder

Full

Adder

Full

Adder

Full

Adder

C0 C1 C2

4-bit Adder

Example:

1 1 0 1 (-3)

+ 0 1 1 0 (6)

1 0 0 1 1 (3)

A3 A2 A1 A0

+ B3 B2 B1 B0C3 C2 C1 C0

S3 S2 S1 S0

Combinational Circuits- Arithmetic Circuits - (3/4)

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Page 23: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Multiplier

Example:

010 (2)

× 101 (5)

010

+ 000

+ 010

01010 (10)

A2 A1 A0

×B2 B1 B0

A2 A1 A0 ×B0 ×1

+ A2 A1 A0 × B1 ×2

+ A2 A1 A0 × B2 ×4

A2×B0

A1×B0

A0×B0

A2×B1

A1×B1

A0×B1

A2×B2

A1×B2

A0×B2

A×B0

A×B1

A×B2

P0P1P2P3P4

Combinational Circuits- Arithmetic Circuits - (3/4)

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Page 24: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Other Combinational Circuits- Decoder -

- An n-to-2n decoder is a multiple output combinational logic circuit with n input and 2n output signals.

- For each possible input condition, one and only one output signal is active.

n-to2n

Decoder

… …

x0

x1

xn-1

LSB

MSB

m0

m1

mB

(B = 2n-1)

Exercise: Design a 2-to-4 decoder

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Input

x1 x0

Output

m3 m2 m1 m0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Page 25: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

- Multiplexer (or MUX) selects one of many input signals to appear on a single output line

- Demultiplexer (or DEMUX) takes a single input signals and routes it to one of several output signals.

Other Combinational Circuits- Multiplexer & Demultiplexer -

D0

D1

Dn

Y

D0

D1

Dn

Y

MUX DEMUX

SEL

D0

Dn

Y Y

SEL

D0

Dn

… ………

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Page 26: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

- A comparator determines the relative magnitude of two binary numbers.

- There are many types of comparators such as:

Other Combinational Circuits- Comparator-

>A

BY1 <

A

BY2

≥A

BY3 ≤

A

BY4

=A

BY5

Input

Relationship

Output

Y1 Y2 Y3 Y4 Y5

A > B 1 0 1 0 0

A < B 0 1 0 1 0

A = B 0 0 1 1 1

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Page 27: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Combinational Circuits

Combinational circuit: used for calculation

◦ Always representing a present state

◦ No past state in the circuit

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A

NOT gate

out = A

out

NAND gate

A

Bout = AB

out

XOR gate

A

B out = A^B

out

“Out” changes

when A or B changes;

No past, nor next info.

Page 28: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Combinational Circuits

Combinational Circuits

◦ Always represent a current state

◦ No past state in the circuit

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Not possible to achieve “counter”

Counter:

◦ 0123… N

+ 1A A_plus1

Comb. Logic

Q: What will happen on A_plus1?

A: A_plus1 will go ∞ w/o stop!

No stable state if input is not stable.

That’s the reason we need sequential circuit.

Page 29: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Minitest-3.2

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0

1

1

0

= 2’b10

?

?

?

?

??

??

?

?

?

?

?

Page 30: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Minitest-3.2: Answer

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0

1

1

0

= 2’b10

0

0

1

0

11

00

0

0

1

0

1

0 0 1 0 SEL = 2’b10 = 2

Y = D2

Page 31: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Basic Logic Circuits

Basic Logic Gates: Not, And, Or, Xor, Xnor, etc.

Combinational Circuits

Arithmetic Operator: adder, multiplier, etc.

Encoder

Multiplexer

Comparators

Sequential Circuits

Memory Elements: Latch, FlipFlop, Register, etc.

Sequential Circuits

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Page 32: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

- Sequential circuit is a circuit that is able to REMEMBER its previous data.

- Two main types:

Latch

FlipFlop

Latch FlipFlop

Controlled by excitation input

signals

Controlled by clock signal

Two types:

- Set latch: force to 1

- Reset latch: force to 0

Many Types:

- Master Slave SR FlipFlop

- Master Slave D FlipFlop

- Master Slave JK FlipFlop

- Edge-triggered D FlipFlop

- Edge-triggered JK FlipFlop

- T FlipFlop

Device state is changed

immediately

Device state is changed after 1

clock cycle

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Memory Elements

Page 33: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Memory ElementsSR Latch

Set Reset Latch◦ “Set” means “output 1”

◦ “Reset” means “output 0”

e.g. reset status◦ The feedback loop creates stable status

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S R Q Q’

0 0 Qprev Q’prev (stored)

0 1 0 1 (reset)

1 0 1 0 (set)

1 1 0 0 (not used)

S

RQ

Q’

0

1

1

0

0

1

Page 34: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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E D Q Q’

0 x Qprev Q’prev (stored)

1 0 0 1 (reset)

1 1 1 0 (set)

Memory ElementsGate D Latch

Page 35: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

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D

cp=0

Q

Accept input Keep (Locked)

cp

cp

D

cp=1

Q

Keep (Locked) Accept input

Memory ElementsMaster/Slave D FlipFlop

Page 36: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Register

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Enable

Clock

Data in

Data outbmsb ... b1 b0

bmsb ... b1 b0

bmsb ... b1 b0

bmsb ... b1 b0

Clock

Write_address

read_address

Write_data

Write_enable

read_data

Memory: is a bank of registers

Memory ElementsMaster/Slave D FlipFlop

Page 37: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Sequential Logic CircuitsDefinition: Outputs depends on stored information (current state) and current inputs

◦ Example: Bank account

◦ State = Waiting for new operation (stored value: your current balance)

◦ Input = Withdraw or deposit

◦ Output = Your new balance

Combinational logic and one/or more memory elements are used in sequential logic

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input output

Mem. Element

Comb.

Logic

Sequential Circuit

Page 38: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Memory element

◦ Provide a lock of current status

Combinational logic

◦ Calculate new status

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input output

Mem. Element

Comb.

Logic

Sequential Circuit

Sequential Logic Circuits

Page 39: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Modeling the Circuit

Looking into the memory

◦ It stores n-bits

◦ 1 bit has two states, as 0 and 1;

◦ 2 bits have four states, as 00, 01, 10, 11;

◦ n bits have 2n states.

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input output

Comb.Logic

Sequential Circuit

Mem. Element

The amount of information to be stored is “finite”

◦ a Finite State Machine (FSM) to describe the 2n states

Page 40: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Two Kinds of FSM Models

Mealy Machine

◦ Outputs are function of the present/current state and the present inputs

Moore Machine

◦ Outputs are independent of the inputs i.e. dependent on present state only

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input output

Comb.Logic

Sequential Circuit

Mem. Element

input output

Comb.Logic

Sequential Circuit

Mem. Element

Major FSM model we use

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Minitest-3.3

41

1

1

?

?

?

?

Page 42: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Minitest-3.3: Answer

42

1

1

?

?

?

?

1

1

0

1

1

0

Page 43: Lecture 3: Logic circuit - NAISTarch.naist.jp/~hong/Lecture/Reconfig_Computing/3_Logic...Lecture Information 3 Grading (評価) Mini-test (40%) Score is based on the number of times

Summary

Basic Logic Gates: Not, And, Or, Xor, Xnor, etc.

Combinational Circuits

Arithmetic Operator: adder, multiplier, etc.

Encoder

Multiplexer

Comparators

Sequential Circuits

Memory Elements: Latch, FlipFlop, Register, etc.

Sequential Circuits

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