lecture 2-3: digital circuits & components (1) logic gates(6) registers parallel load (2)...

Lecture 2-3: Digital Circuits & Components

(1) Logic Gates (6) RegistersParallel Load

(2) Boolean Algebra Shift RegisterCounter

(3) Logic Simplification(7) Sequential Circuits

(4) Combinatorial Circuits Input EquationsAdder State TablesDecoderEncoder (8) MemoryMultiplexers Random-Access

Read-Only(5) Flip-Flops

SR Flip-FlopJK Flip-FlopD Flip-FlopT Flip-Flop

Logic Gates

Transmission Gates & Switches

Gate Implementations Using Switches

Logic Gates

Gate-Level Components

Gate-Level Components

Name Symbol VHDL Equation Truth Table

AND

OR

NOT

X <= A and B

X <= A or B

X <= not A

AB

X

AB

X

A X

A B X0 0 00 1 01 0 01 1 1

A B X0 0 00 1 11 0 11 1 1

A X0 11 0

Composite Gates

Name Symbol VHDL Equation Truth Table

NAND

NOR

XOR

X <= not (A and B)

X <= A xor B

AB

X A B X0 0 10 1 11 0 11 1 0

A B X0 0 10 1 01 0 01 1 0

AB

X

AB

X X <= not (A or B)

A B X0 0 00 1 11 0 11 1 0

Boolean Algebra

Functional Operators

Axiomatic Definitions

Other Identities

Logic Simplification

Two basic methods:Boolean Algebra

ComplicatedAccident ProneOnly way when the number of variables > 5

Karnaugh MapGraphical - PictorialSimple when the number of variables <= 5

Map Simplification

A

B0 1

1

0 (A,B)= 0

(A,B)= 1

(A,B)= 2

(A,B)= 3

A

BC00 01

1

0 (A,B,C)= 0

(A,B,C)= 1

(A,B,C)= 4

(A,B,C)= 5

11 10

(A,B,C)= 3

(A,B,C)= 2

(A,B,C)= 7

(A,B,C)= 6

AB

CD00 01

01

00 (A,B,C,D)= 0

(A,B,C,D)= 1

(A,B,C,D)= 4

(A,B,C,D)= 5

11 10

(A,B,C,D)= 3

(A,B,C,D)= 2

(A,B,C,D)= 7

(A,B,C,D)= 6

(A,B,C,D)= 12

(A,B,C,D)= 13

(A,B,C,D)= 8

(A,B,C,D)= 9

(A,B,C,D)= 15

(A,B,C,D)= 14

(A,B,C,D)= 11

(A,B,C,D)= 1010

11

Map Simplification Example

AB

CD00 01

01

00

11 10

10

11

A B C D X0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 10 1 1 1 11 0 0 0 01 0 0 1 11 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 01 1 1 0 01 1 1 1 1

=> X = sum(1,2,3,6,7,9,10,11,12,15)

Circuit Types

Combinatorial Circuit Example- Half-adder

Half-adder has no Carry-in input

Function table:A B Sum Carry-out0 0 0 00 1 1 01 0 1 01 1 0 1

Logic diagram: VHDL Code:

HALF_ADDER: process (A,B)begin

Sum <= A xor B;Carry_out <= A and B;

end process HALF_ADDER;

AB

Sum

Carry-out

Combinatorial Circuit Example- Full-adder

Full-adder has a Carry-in input

Function table:

Carry-in A B Sum Carry-out0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Combinatorial Circuit Example- Full-adder

Logic diagram:

FULL_ADDER: process (A,B)begin

Sum <= A xor B xor Carry-in;Carry_out <= (A and B) or ((A xor B) and Carry_in);

end process FULL_ADDER;

AB

Sum

Carry-out

CI

VHDL Code:

Combinatorial Circuit Example- Decoder

n inputs and 2n outputs

Function table:

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0

VHDL Code:

DECODER : process ( I(2 downto 0) )begin

Y(7 downto 0) <= others => ‘0’;case ( I(2 downto 0) ) is

when “000” => Y(0) <= ‘1’;when “001” => Y(1) <= ‘1’;when “010” => Y(2) <= ‘1’;when “011” => Y(3) <= ‘1’;when “100” => Y(4) <= ‘1’;when “101” => Y(5) <= ‘1’;when “110” => Y(6) <= ‘1’;when “111” => Y(7) <= ‘1’;

end case;end process DECODER;

Combinatorial Circuit Example- Decoder

Combinatorial Circuit Example- Encoder

VHDL Code:

ENCODER : process ( I(7 downto 0) )begin

case ( I(7 downto 0) ) iswhen “00000001” => Y <= “000”;when “00000010” => Y <= “001”;when “00000100” => Y <= “010”;when “00001000” => Y <= “011”;when “00010000” => Y <= “100”;when “00100000” => Y <= “101”;when “01000000” => Y <= “110”;when “10000000” => Y <= “111”;

end case;end process ENCODER;

Combinatorial Circuit Example- Encoder

Combinatorial Circuit Example- Multiplexer

VHDL Code:

MULTIPLEXER : process ( S(1 downto 0) )begin

case ( S(2 downto 0) ) iswhen “00” => Y <= I(0);when “01” => Y <= I(1);when “10” => Y <= I(2);when “11” => Y <= I(3);

end case;end process MULTIPLEXER;

Combinatorial Circuit Example- Multiplexer

Flip-flops are the most basic of sequential (clocked) circuits

Inputs are only considered valid during a clock edge transition

==> Inputs must be held stable during the transition(called setup and hold interval)

Outputs only change after a clock edge transition

==> Outputs change after an interval called theclock-to-output time

Flip-Flops

SR flip-flops have two inputs, set and reset, that act as follows:

Truth Table (set dominant):S R C Qx x 0 Q_lastx x 1 Q_last1 x 10 1 0

Truth Table (reset dominant):S R C Qx x 0 Q_lastx x 1 Q_last1 0 1x 1 0

Flip-Flop Types - SR

Symbolic representation: VHDL code (set dominant):

Flip-Flop Types - SR

S

R

QSR_FF : process (C)begin if (C’event and (C = ‘1’)) then if (S = ‘1’) then Q <= ‘1’; elsif (R = ‘1’) then Q <= ‘0’; else Q <= Q_last; end if; end if;end process SR_FF;

Q_last <= Q;

C

JK flip-flops have two inputs, that act as follows:

Truth Table:J K C Qx x 0 Q_lastx x 1 Q_last0 0 Q_last0 1 01 0 11 1 /Q_last

Flip-Flop Types - JK

Symbolic representation: VHDL code:

Flip-Flop Types - JK

J

K

Q

JK_FF : process (C)begin if (C’event and (C = ‘1’)) then if ((J = ‘0’) and (K = ‘0’)) then Q <= Q_last; elsif ((J = ‘1’) and (K = ‘0’)) then Q <= ‘1’; elsif ((J = ‘0’) and (K = ‘1’)) then Q <= ‘0’; else Q <= not Q_last; end if; end if;end process JK_FF;Q_last <= Q;

C

D flip-flops have one input, data, that act as follows:

Truth Table:D C Qx 0 Q_lastx 1 Q_last0 01 1

Flip-Flop Types - D


Flip-Flop Types - D

D Q D_FF : process (C)begin if (C’event and (C = ‘1’)) then Q <= D; end if;end process D_FF;

C

T flip-flops have one input, toggle, that act as follows:

Truth Table:T C Qx 0 Q_lastx 1 Q_last0 Q_last1 / Q_last

Flip-Flop Types - T


Flip-Flop Types - T

T Q T_FF : process (C)begin if (C’event and (C = ‘1’)) then if (T = ‘1’) then Q <= not Q_last; else Q <= Q_last; end if;end process T_FF;

Q_last <= Q;

C

Groups of D-type flip-flops, with each FF holding 1 bit of information==> A 32-bit register would require 32 FF’s to implement

Registers can be loaded:In parallel -- all bits at onceIn serial -- one bit at a time, from either end

Registers are used to:Temporarily store information for arithmetic operationsImplement control functions -- sets, resets, enables, etc.Report status -- overflows, error conditions, etc.Implement interrupts

Registers


Registers- Parallel Load

D(n-1..0)Q(n-1..0)

REGISTER : process (C)begin if (C’event and (C = ‘1’)) then if (LOAD = ‘1’) then Q <= D; else Q <= Q_last; end if;end process REGISTER;

Q_last <= Q;

C

LOAD

Truth table:

LOAD C Q x 0 Q_last x 1 Q_last 0 Q_last 1 D

Symbolic representation:

Registers- Serial Load (Shift)

DQ(n-1..0)

C

SHIFT

Truth table:

SHIFT C Q(0) Q(n-1..1) x 0 Q_last(0) Q_last(n-1..1) x 1 Q_last(0) Q_last(n-1..1) 0 Q_last(0) Q_last(n-1..1) 1 D Q_last(n-2..0)

REGISTER : process (C)begin if (C’event and (C = ‘1’)) then if (SHIFT = ‘1’) then Q (7 downto 1) <= Q_last (6 downto 0); Q (0) <= D; else Q <= Q_last; end if;end process REGISTER;

Q_last <= Q;

VHDL code (8-bit register, for example):

Registers- Serial Load (Shift)

Counters

A counter is a register capable of incrementing or decrementing its contents

Q <= Q plus nQ <= Q minus n

The definition of "plus" and "minus" depend on the way the register contents encode the integers

Binary Counters: Encode the integers with the binary number code

Counters - Example: 3-bit Binary Up Counter

Truth Table: Symbolic Representation

CNT C Q_last Qx 0 x x x Q_lastx 1 x x x Q_last0 x x x Q_last1 0 0 0 Q_last+11 . . . Q_last+11 1 1 0 Q_last+11 1 1 1 0 0 0

000

001 010

011

111

110 101

100

CNTCNT

CNT

CNT

CNT

CNTCNT

CNT

State Diagram:

Q(2..0)

C

CNT


Truth Table: Counter Design:

CNT C Q_last Qx 0 x x x Q_lastx 1 x x x Q_last0 x x x Q_last1 0 0 0 Q_last+11 . . . Q_last+11 1 1 0 Q_last+11 1 1 1 0 0 0

Bit Q(0) Toggles on every CNT = 1

Bit Q(1) Toggles on everyCNT = 1 andQ(0) = 1

Bit Q(2) Toggles on everyCNT = 1 andQ(0) = 1Q(1) = 1

000

001 010

011

111

110 101

100

CNTCNT

CNT

CNT

CNT

CNTCNT

CNT

State Diagram:


Logic Diagram (one design): Logic Diagram (another design):

CNTT Q

T Q

T Q

Q(0)

Q(1)

Q(2)

C

This is called series(or ripple) carry logic

CNTT Q

T Q

T Q

Q(0)

Q(1)

Q(2)

C

This is called parallel(or look-ahead) carry logic


VHDL Code:

COUNTER : process (C)begin if (C’event = (C = ‘1’)) then if (CNT = ‘1’) then if (Q_last = “111”) then Q <= “000”; else Q <= Q_last + ‘1’; end if; end if; end if;end process COUNTER;

Q_last <= Q;

Does this make ripple or look-ahead carry logic?

Sequential Circuits

A sequential circuit which satisfies the following conditions:

There is at least one flip-flop in every loop

All flip-flops have the same type of dynamic clock

All clock inputs of all the flip-flops are driven by the same clock signal.

Is called a synchronous sequential circuit

Sequential Circuits

Any synchronous sequential circuit can be drawn in Canonical form by pulling the flip-flops to the bottom of the figure (think of the lines as elastic).

Since all loops have a flip-flop in them, this will leave the remaining circuit without loops, and hence combinational.

CombinatorialLogic

D Q

CombinatorialLogic

Inputs

C

State

Outputs This is called a Moore state machine - outputs depend only on current state

Sequential Circuits

Another way to design a state machine is a follows:

CombinatorialLogic

D Q

CombinatorialLogic

Inputs

C

State

Outputs This is called a Mealy state machine - outputs depend on current state and inputs

Sequential Circuit Descriptions

StructuralLogic diagram

Excitation EquationsLogical equations for the flip-flop inputs as a function of current flip-flop states and circuit input signals

Output equationsLogical equations for circuit outputs as a function of current flip-flop states and circuit inputs signals

Sequential Circuit Descriptions

BehavioralTransition and output equations

Logical equations for next flip-flop states and circuit outputs in terms of current flip-flop states and circuit input signals

Transition tableTwo-dimensional truth table of transition and output equations

State tableTransition table with the states given descriptive names

State diagram (graph)A graph with nodes corresponding to states and directed edges corresponding to state transistions

Sequential Circuit Description- Example

Problem:Build a 2-bit binary up/down counter, with the following I/O:

UP in : increment the countDN in : decrementQ(1..0) out : count

State diagram: VHDL Code:


Transition Table: State Table:

UP DN Q Q_next UP DN Q Q_next


Excitation Equation Q(1): Excitation Equation Q(0):

Q_next(1) = Q_next(0) =

Q(1..0)

UP DN 00 01 11 10

10

11

01

00

Q(1..0)

UP DN 00 01 11 10

10

11

01

00

Sequential Circuit Timing

The following global timing parameters are important to the reliable working of a sequential circuit:

Global Setup and Hold: The window around any FF’s clock edge during which its input must be valid

Global Clock-to-out: The amount of time that it takes to get a signal, from the input clock, out of a circuit.

Maximum Clock Frequency: The fastest a global clock can be run within a design.

Maximum Clock Skew: The greatest difference between when a clock hits two different FF’s clock inputs

Global Setup,Hold,&Propagation Delay

Consider the following circuit:

CombinatorialLogic Delay

D QD_ext

CLK_ext

Q_intD_int

CLK_int

tPC

Clock TreeNetwork Delay

tPNI

tPFF

tPNO

Output NetDelay

Q_ext

Global Setup,Hold,&Propagation Delay

Consider the following timing diagram:

CLK_ext

D_ext

CLK_int

D_int

Q_int

Q_ext

tSU_E tHD_E

tSU_I tHD_I

tPFF

tPNO

tPNI tPC

tP

tSU_E = tSU_I + tPNI - tPC

tHD_E = tHD_I - tPNI + tPC

tP = tPC + tPFF + tPNO

Maximum Clock Frequency

The maximum clock frequency, minimum clock width, is determined by the time required for changes at one flip-flop output to be seen at another flip-flop input.

Consider the following circuit:

tSKEW

D Q CombinatorialLogic Delay

Skew BetweenClocks

D QD1 Q1 D2 Q2

C1

C1

tPNtPFF

Consider the following timing diagram:

C1

C2

Q1

D2

tSKEW tPER = tPFF + tPN + tSU + tSKEW

Maximum Clock Frequency

tPFF

tSU

tPER

tSKEW

tPN

Note the skewing C1 after C2 is the worst case. If the skew had delayed C2 after C1, it would have increased the maximum clockfrequency.

Maximum Clock Skew

Consider the same circuit as above:

tSKEW

D Q CombinatorialLogic Delay

Skew BetweenClocks

D QD1 Q1 D2 Q2

C1

C1

tPNtPFF

Consider the same timing diagram as above:

C1

C2

Q1

D2

tSKEW tSKEW = tPFF + tPN - tHD

Maximum Clock Skew

tPFF

tHD

tPN

Note the skewing C2 after C1 is the worst case. If the skew had delayed C1 after C2, it would have increased the maximum clockskew allowed.

Introduction to Memory

Memory Hierarchy Technology

Random Access:

“Random” is good: access time is the same for all locations

DRAM: Dynamic Random Access Memory

High density, low power, cheap, slow

Dynamic: need to be “refreshed” regularly

SRAM: Static Random Access Memory

Low density, high power, expensive, fast

Static: content will last “forever”(until lose power)

“Non-so-random” Access Technology:

Access time varies from location to location and from time to time

Examples: Disk, CDROM

Sequential Access Technology: access time linear in location (e.g.,Tape)


Performance of Main Memory:

Latency: Cache Miss Penalty

Access Time: time between request and word arrives

Cycle Time: time between requests

Bandwidth: I/O & Large Block Miss Penalty (L2)

Main Memory is DRAM: Dynamic Random Access Memory

Dynamic since needs to be refreshed periodically (8 ms)

Addresses divided into 2 halves (Memory as a 2D matrix):

RAS: Row Access Strobe

CAS: Column Access Strobe

Cache uses SRAM: Static Random Access Memory

No refresh (6 transistors/bit vs. 1 transistorSize: DRAM/SRAM 4-8, Cost/Cycle time: SRAM/DRAM 8-16


Why do computer designers need to know about RAM technology?

Processor performance is usually limited by memory bandwidth

As IC densities increase, lots of memory will fit on processor chip

Tailor on-chip memory to specific needs

Instruction cache

Data cache

Write buffer

What makes RAM different from a bunch of flip-flops?

Density: RAM is much more denser

Logic Diagram of a Typical SRAM

Write Enable is usually active low (WE_L)

Din and Dout are combined to save pins:

A new control signal, output enable (OE_L) is needed

WE_L is asserted (Low), OE_L is disasserted (High)

D serves as the data input pin

WE_L is disasserted (High), OE_L is asserted (Low)

D is the data output pin

Both WE_L and OE_L are asserted:

Result is unknown. Don’t do that!!!

A

DOE_L

2 Nwordsx M bitSRAM

N

M

WE_L

Timing of a Typical SRAM

Write Timing:

D

Read Timing:

WE_L

A

WriteHold Time

Write Setup Time

A

DOE_L

2 Nwordsx M bitSRAM

N

M

WE_L

Data In

Write Address

OE_L

High Z

Read Address

Junk

Read AccessTime

Data Out

Read AccessTime

Data Out

Read Address

Logic Diagram of a Typical DRAM

AD

OE_L

256K x 8DRAM9 8

WE_L

Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low

Din and Dout are combined (D):

WE_L is asserted (Low), OE_L is disasserted (High)

D serves as the data input pin

WE_L is disasserted (High), OE_L is asserted (Low)

D is the data output pin

Row and column addresses share the same pins (A)

RAS_L goes low: Pins A are latched in as row address

CAS_L goes low: Pins A are latched in as column address

RAS/CAS edge-sensitive

CAS_LRAS_L

Timing of a Typical DRAM Write

AD

OE_L

256K x 8DRAM9 8

WE_LCAS_LRAS_L

WE_L

A Row Address

OE_L

Junk

WR Access Time WR Access Time

CAS_L

RAS_L

Col Address Row Address JunkCol Address

D Junk JunkData In Data In Junk

DRAM WR Cycle Time

Early Wr Cycle: WE_L asserted before CAS_L Late Wr Cycle: WE_L asserted after CAS_L

Every DRAM access begins at:

The assertion of the RAS_L

2 ways to write: early or late v. CAS

Timing of a Typical DRAM Read

AD

OE_L

256K x 8DRAM9 8

WE_LCAS_LRAS_L

OE_L

A Row Address

WE_L

Junk

Read AccessTime

Output EnableDelay

CAS_L

RAS_L


D High Z Data Out

DRAM Read Cycle Time

Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L

Every DRAM access begins at:

The assertion of the RAS_L

2 ways to read: early or late v. CAS

Junk Data Out High Z

Motivation for Fast Page Mode DRAM

Regular DRAM Organization:

N rows x N column x M-bit

Read & Write M-bit at a time

Each M-bit access requiresa RAS / CAS cycle

Fast Page Mode DRAM

N x M “register” to save a row

A Row Address Junk

CAS_L

RAS_L


1st M-bit Access 2nd M-bit Access

N r

ows

N cols

DRAM

M bits

RowAddress

ColumnAddress

M-bit Output

Operation of Fast Page Mode DRAM

Fast Page Mode DRAM

N x M “SRAM” to save a row

After a row is read into the register

Only CAS is needed to access other M-bit blocks on that row

RAS_L remains asserted while CAS_L is toggled

A Row Address

CAS_L

RAS_L

Col Address Col Address

1st M-bit Access

N r

ows

N cols

DRAM

ColumnAddress

M-bit Output M bits

N x M “SRAM”

RowAddress

Col Address Col Address

2nd M-bit 3rd M-bit 4th M-bit

Logic Families

Design Considerations

Programmable Logic

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lecture 2-3: digital circuits & components (1) logic gates(6) registers parallel load (2)...

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