lecture 17 adders and multipliers - bwrcs.eecs.berkeley.edu

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UC Berkeley EE241 B. Nikoli c

EE241 - Spring 2000Advanced Digital Integrated Circuits

Lecture 17

Adders and Multipliers


Logarithmic Lookahead Adders

A7

F

A6A5A4A3A2A1

A0

A0

A1

A2A3

A4

A5

A6

A7

F

tp∼ log2(N)

tp∼ N

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Tree Adders

lmG ppP ⋅=

lmmG gpgG ⋅+=

m – more significantl – less significant

Start from the input P, G, and continue up the tree2-bit groups, then 4-bit groups, …

( ) ( ) ( )lmlmmllmm ppgpgpgpgpg ⋅⋅+=•= ,,,),(

Kogge, Stone, Trans on Comp,’73


Tree Adders

( ) ( )jkjkkikijiji PGPGPG :1:1:::: ,,),( −−•=

( ) ( ) ),(,,),( GPPPGPGPGPG =⋅⋅+=•

( ) ( )jvjvkikijiji PGPGPG :::::: ,,),( •=

Associativity:

Idempotency:

Associativity + Idempotency:

jki >≥

jki >≥ kv >

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Examples

( ) ( ) ( ) ( ){ }{ }{ }00:3,0:34:74:78:118:1112:1512:15 ,1,,),( cPGPGPGPG ••••

( ) ( ) ( ) ( )00014141515 ,1,...,, cPGPGPG ••••

16-bit ripple carry

16-bit carry lookahead with 4-bit groups


Brent-Kung Adder(G0,P0)(G1,P1)

(G2,P2)

(G3,P3)

(G4,P4)(G5,P5)

(G6,P6)

(G7,P7)

Co,0

Co,1Co,2

Co,3

Co,4

Co,5

Co,6

Co,7

tadd ∼ log2(N)Brent, Kung, Trans on Comp, 3/82

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Tree Adders


Ling Adder

Variation of CLA

Ling, IBM J. Res. Dev, 5/81

1−⋅+= iiii GpgG

1−⊕= iii GpS

iii bap ⊕=

iii bag ⋅=

11 −− ⋅+= iiii HtgH

11 −−+⊕= iiiiii HtgHtS

iii bat +=

iii bag ⋅=

Ling’s equations

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Ling Adder

1−⋅+= iiii GpgG

( ) 1

11

−

−−

⋅++=

⋅++=

iiii

iiiiii

Gpgg

GpGggG

1−⋅+= iiii GtgG 11 −− ⋅+= iiii GtgH

Ling’s equation

Doran, Trans on Comp 9/88


Ling Adder

01231232333 gtttgttgtgG +++=

0121223

00121122233

gttgtgg

gtttgttgtgH

+++=

+++=

Conventional

Ling

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HP Adder

Naffziger, ISSCC’96

01234 ppppi =


HP Adder

Carry rippleSum select

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Hybrid Adders

Dobberpuhl, JSSC 11/92 DEC Aplha 21064


DEC Adder

l Combination:» 8-bit tapered pre-discharged Manchester

carry chains, with Cin = 0 and Cin = 1» 32-bit LSB carry-lookahead» 32-bit MSB conditional sum adder» Carry-select on most significant bits» Latch-based timing

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Z X·· Y× Zk2k

k 0=

M N 1–+

∑= =

Xi2i

i 0=

M 1–

∑

Yj2j

j 0=

N 1–

∑

=

XiYj2i j+

j 0=

N 1–

∑

i 0=

M 1–

∑=

X Xi 2i

i 0=

M 1–

∑=

Y Yj2j

j 0=

N 1–

∑=

with

Binary Multiplication


1 0 1 1

1 0 1 0 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

×

1 1 1 0 0 1 1 1 0

+

Partial Products

AND operation

Binary Multiplication

2N bits in the final sum

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HA FA FA HA

FA FA FA HA

FA FA FA HA

X0X1X2X3 Y1

X0X1X2X3 Y2

X0X1X2X3 Y3

Z1

Z2

Z3Z4Z5Z6

Z0

Z7

Array Multiplier


Shift-and-Add Multiplier

l Standard adder and shift-in the multiplicand

l Shift the result as well and addl N cyclesl Parallel adders add more hardware

(adders) instead.

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HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2

MxN Array Multiplier— Critical Path


H A HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Vector Merging Adder

Carry-Save Multiplier

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A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

C i

Co

S

Ci

P

P

P

P

P

Identical Delays for Carry and Sum

Adder Cells in Array Multiplier


SCSCSCSC

SCSCSCSC

SCSCSCSC

SC

SC

SC

SC

Z0

Z1

Z2

Z3Z4Z5Z6Z7

X0X1X2X3

Y1

Y2

Y3

Y0

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcastedthrough the complete array.( )

Multiplier Floorplan

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FA

FA

FA

FA

y0 y1 y2

y3

y4

y5

S

Ci-1

Ci-1

Ci-1

Ci

Ci

Ci

FA

y0 y1 y2

FA

y3 y4 y5

FA

FA

CC S

Ci-1

Ci-1

Ci-1

Ci

Ci

Ci

Wallace-Tree Multiplier



Wallace,Trans on Comp. 2/64

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Tree Multipliers

l Time is proportional to log Nl Wiring is complicatedl Different wire lengthsl Optional pipelining

lecture 17 adders and multipliers - bwrcs.eecs.berkeley.edu

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