lec1 intro to computer engineering by hsien-hsin sean lee georgia tech -- intro

ECE2030 Introduction to Computer Engineering

Lecture 1: Overview

Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech

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• Instructor: Prof. Hsien-Hsin “Sean” Lee• Email: [email protected]• Course web:

http://www.ece.gatech.edu/~leehs/ECE2030• My office: Klaus 2318• Teaching Materials:

– Morris Mano and Charles Kime, “Logic and Computer Design Fundamentals,” the 3rd edition

– Course notes and handouts (check out course web)– TA: to be announced later

• Attending classes is important !!

ECE2030 Syllabus

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ECE2030 Syllabus • Grading policy

– 3 Homework assignment: 5% each– 1 Programming assignment: 10%– 3 in-class exams: 15% each – 1 final exam: 30%– [100,90]=A; (90,80]=B; (80,70]=C,(70,55]=D,

(55,0]=F• All homework: turn-in in the first 5 minutes

“in class” of the due day• All exams: closed books, closed notes, no

calculator• Honor code • Use webct (http://webct.gatech.edu) for

your homework and exam grades

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Objective: Digital Design Principle• Number systems• Boolean algebra• Switch and CMOS design • Combinational logic

– Logic gates– Building blocks: de/mux, de/encoder, shifters,

adder/subtractor, multiplier– Logic minimization– Mixed logic

• Sequential logic– Latches, Flip-flops– Counters– State machines: Mealy/Moore machines

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Objective: Digital Design Principle• Memory and Programmable Devices

– Register, RAM, ROM, PLA, PAL • Architectural concept

– Instruction set architecture (ISA)– Stored-Program Computer and Sequential

Control (von Neumann architecture)– Datapath– Branches

• Processor and Software Convention– MIPS ISA– Procedural calls: Stack

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Hierarchy of ComputationProblemProblem AlgorithAlgorith

msmsProgramming inProgramming inHigh-Level LanguageHigh-Level Language

Compiler/Assembler/Compiler/Assembler/LinkerLinker

Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinary

System architectureSystem architecture

Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architecture

Functional units/Functional units/Building blocksBuilding blocks

Gates Level Gates Level Design Design

TransistorsTransistors ManufacturingManufacturing

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System LevelSystem LevelHuman LevelHuman Level

RTL Level RTL Level Logic Level Logic Level Circuit Level Circuit Level Silicon Level Silicon Level

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Our Focus in 2030










System LevelSystem LevelHuman LevelHuman Level

RTL Level RTL Level Logic Level Logic Level Circuit Level Circuit Level Silicon Level Silicon Level

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Zoom-in a System Component

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Moore’s Law

Exponential growthExponential growth2,25

0

Transistor count will be doubled every 18 monthsTransistor count will be doubled every 18 months Gordon Moore, Intel co-founder

42millions

1.7 billionsMontecito

10 μm13.5mm2

0.09 μm596 mm2

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Integrated Circuit Complexity

Source: Intel

1212

Minimum Feature Size

We are currently at 0.065µm (65nm) and moving towards 0.045µm

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Average Transistor Price per year

Source: Dataquest

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Processor Market Segmentation

High PerformanceHigh Performance(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)

Embedded / low-powerEmbedded / low-power(e.g. Intel Xscale, ARM, MIPS)(e.g. Intel Xscale, ARM, MIPS)

Special purposeSpecial purpose(e.g. DSP, NVidia GForce)(e.g. DSP, NVidia GForce)

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Analog Signal vs. Digital

• So, why Digital?

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Binary Signals

• So, why Binary?

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Voltage Range of Binary Signals

0.0 Volts

1.0 Volts

2.0 Volts

3.0 Volts

4.0 Volts

5.0 Volts

INPUTINPUT OUTPUTOUTPUT

HIGH (1)HIGH (1)

LOW (0)LOW (0)

HIGH (1)HIGH (1)

LOW (0)LOW (0)

BACKUP

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A Generic Intel-based PC SystemYour CPU hereYour CPU here

2020

Dual-Core Itanium 2 (Montecito)

lec1 intro to computer engineering by hsien-hsin sean lee georgia tech -- intro

Devices & Hardware