lcis digital arithmetic
TRANSCRIPT
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Algorithms and Number Systems for Digital Arithmetic
Jean-Luc Beuchat
Laboratory of Cryptography and Information Securitymailto:[email protected]
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Current Research Activities
Research Interests
Computer arithmetic
CryptographyComputer architecture
Hardware and software design
Artificial neural networks
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Current Research Activities
Computer Arithmetic
Number systems.Integer, floating point, signed digits, RNS, finite fields,RN-codings, . . .
Algorithms.Addition, multiplication, division, modular multiplication, . . .
Implementations.ASIC, FPGA, DSP, general processor, low-power, . . .
Software libraries and hardware design tools.
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Outline of the Tutorial
I. An Introduction to Digital Circuits
1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design ToolsII. An Introduction to Computer Arithmetic
5 Number Systems
6 AlgorithmsIII. Arithmetic Operators for Cryptography
7 Modular Addition
8 Modular Multiplication
9 ConclusionJean-Luc Beuchat (LCIS) Digital Arithmetic 4 / 187
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Part I: An Introduction to Digital Circuits
1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design Tools
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Part I: An Introduction to Digital Circuits
1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design Tools
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Logic Gates
NOT gate
YA
A Y
0 1
1 0
2-input AND gate
Y
A
B
A B Y
0 0 0
0 1 01 0 0
1 1 1
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Logic Gates
2-input OR gate
YA
B
A B Y
0 0 0
0 1 1
1 0 11 1 12-input XOR gate
A
BY
A B Y = AB AB
0 0 00 1 1
1 0 1
1 1 0
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2-Input NOT AND Gate (NAND2)
YA
B
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Universal gate
B
A
A OR BAA
A
BAB
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2-Input NOT OR Gate (NOR2)
YA
B
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Universal gate
B
AA A OR BB
A
AB
A
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Multiplexer (MUX)
S
B
A
Y
S
A
BY
0
1
S Y
0 A
1 B
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Latch
D
0
1 QQ
Q
D
LD
Q LD
Operation Description LD
HOLD Q Q 0LOAD Q D 1
LD
D
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D Flip-Flop
Q
D
LD
Q
Clk
D Q
Master Slave
Q
D Q
Q
D
LD
QClk Q(t + 1)
0 Q(t)1 Q(t) D
denotes the rising clock edge
Q
Clk
D
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Latch and Flip-Flop
D Q0 Q1
Clk
Clk
D
Q0
Q1
Q
D
LD
Q
Q
D Q
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R i
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Register
7 4
Clk
Ld
D
Q
4
Q
D Q
Q
D Q
Q
D Q
d0
d1
d2 q2
q1
q0
Clk
3 7
7 1
4
34
4 1
Clk
D
Q
4
Ld
Clk Q
D Q
Q
D Q
Q
D Q
d0
d1
d2
q1
q0
q2
3
3 7
7 1
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L k U T bl (LUT)
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Look-Up Table (LUT)
0
1
Y
1
1 0
1
0
0
0
A 3
1
1
2
Y
1
A
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L k U T bl (LUT)
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Look-Up Table (LUT)
D
En
QD
A
Y
2Clk
D
En
00
01
10
11
Q0
Q1
Q2
Q3EnQD
En
QD
En
Q
Programmable tableShift register (programmabledepth)
1 1 0 1 0
0 1 1 0 1
0 1
En
1 0
0
1
D
0
Q0
10
Q1
0
10
1
Q2
1
10
0
Q3
1
10
0
Y
0
10
1
Clk
0
10
1
A
1
10
0
10
1
10
0 0 1
0 1 1 0 1 0 0
0
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Wi
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Wires
A wire allows a 1-bit signal tobe sent on it
More than one device can read avalue from a wire Wire
D4D1 D2 D3
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Wi s
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Wires
A wire allows a 1-bit signal tobe sent on it
More than one device can read avalue from a wire
At most one device can write ona wire
If two devices attempt to write0 and 1 on a wire, then reading
from wire returns anunpredictable value
Wire
D4D1 D2 D3
D2D1 D3 D4
Wire! ! !
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Wires
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Wires
Tri-state buffer: device thatallows to control when currentpasses
Wire
D3
Control
D1 D4D2
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Wires
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Wires
Tri-state buffer: device thatallows to control when currentpasses
Fanout: number of devices an
output is attached toIf the current coming out of agate is i, then each device getsi/fanout of the current
Buffer: signal regeneration(current boosted back to itsoriginal strength)
Wire
D3
Control
D1 D4D2
Wire
Control
D1 D3 D4D2
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Wires
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Wires
Tri-state buffer: device thatallows to control when currentpasses
Fanout: number of devices an
output is attached toIf the current coming out of agate is i, then each device getsi/fanout of the current
Buffer: signal regeneration(current boosted back to itsoriginal strength)
Wire
Control
D1 D3 D4D2
Wire
D3 D4D2D1
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Hardware Complexity
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Hardware Complexity
a 4
y0
y
a 3
a1 a0a2a3a4a5a6a7
a 2a 0a1a
7y 6y
y0y1y2y3y4y5y6y7y0y1y2y3y
5y 4y 3y 2yy0y1y2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
4y5y6y7
B
E
A
D
C
F
b
1
a1 a0a2a3a4a
2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
y 1y 0y
5a6a7
y 0
7 a1 a0a2a3a4a5a6a7a 6a 5
A B C D E F
Area O(n) O(n) O(n) O(n) O( 12 n log2 n) O(12 n log2 n)
Time O(1) O(1) O(log2 n) O(n) O(log2 n + 1) O(log2 n)
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Hardware Complexity
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Hardware Complexity
y1y2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
y0y1y2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
y0y1y2y3y4y5y6y7
b
A
D
C
F
B
E
y0y1y2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
y0y1y2y3y4y5y6y7
a1 a0a2a3a4a5a6a7
a1 a0a2a3a4a5a6a7
y0
a1 a0a2a3a4a5a6a7
y0
A B C D E F
Area O(n) O(2n) O(n) O(n) O( 12 n log2 n) O(12 n log2 n)
Time O(1) O(log2 n) O(log2 n) O(n) O(log2 n + 1) O(log2 n)
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Part I: An Introduction to Digital Circuits
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Part I: An Introduction to Digital Circuits
1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design Tools
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Field-Programmable Gate Arrays
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Field Programmable Gate Arrays
Processors CircuitsGeneral purpose Specific Programmable
Standard Microcontroller DSP ASIPASIC
FPGA DRA
Pentium 68HC11 TMS320 Standard cell Virtex Systolic RingOpteron AT89 M56K Gate array Cyclone II . . .
PowerPC 8048 SHARC Full custom ProASIC3MIPS . . . . . . PolarProAlpha . . .
. . .
Sources: A. Tisserand, Introduction aux circuits FPGA (available at
http://www.univ-perp.fr/see/rch/mano/sem-at-perpi.pdf), and http://www.wikipedia.org
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Field-Programmable Gate Arrays
http://www.univ-perp.fr/see/rch/mano/sem-at-perpi.pdfhttp://www.univ-perp.fr/see/rch/mano/sem-at-perpi.pdfhttp://www.wikipedia.org/http://www.wikipedia.org/http://www.univ-perp.fr/see/rch/mano/sem-at-perpi.pdfhttp://find/http://goback/ -
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Field Programmable Gate Arrays
Why FPGAs?Prototyping
Short time to market
Small series
Hardware accelerators for some applications (e.g. cryptography)
Dynamic reconfiguration, bio-inspired systems (?)
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Field-Programmable Gate Arrays
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Field Programmable Gate Arrays
Why FPGAs?Prototyping
Short time to market
Small series
Hardware accelerators for some applications (e.g. cryptography)
Dynamic reconfiguration, bio-inspired systems (?)
Drawbacks
Power consumption
Speed
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Example: RapidChip Platform ASICs vs. FPGAs
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p p C p S C G(September 2005)
Vendor LSI Logic FPGA Vendor 1 FPGA vendor 2
Device Integrator I/II FPGA device 1 FPGA device 2
Process 0.11m 90nm 90nmCore Voltage 1.2V 1.2V 1.2V
Dynamic Power 1.93W 6.53W 5.27W
Static Power 0.17W 1.62W 1.84W
Total Power 2.1W 8.15W 7.11W
Source: http://www.lsilogic.com/files/docs/marketing_docs/rapidchip/RC_
Power_Comparison_WP.pdf
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Field-Programmable Gate Arrays
http://www.lsilogic.com/files/docs/marketing_docs/rapidchip/RC_Power_Comparison_WP.pdfhttp://www.lsilogic.com/files/docs/marketing_docs/rapidchip/RC_Power_Comparison_WP.pdfhttp://www.lsilogic.com/files/docs/marketing_docs/rapidchip/RC_Power_Comparison_WP.pdfhttp://www.lsilogic.com/files/docs/marketing_docs/rapidchip/RC_Power_Comparison_WP.pdfhttp://find/http://goback/ -
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g y
FPGA manufacturersXilinx (http://www.xilinx.com)
Altera (http://www.altera.com)
Actel (http://www.actel.com)
Atmel (http://www.atmel.com)Lattice Semiconductor (http://www.latticesemi.com)
QuickLogic (http://www.quicklogic.com)
Cypress Semiconductor (http://www.cypress.com)
Achronix (http://www.achronix.com)
Cellmatrix (http://www.cellmatrix.com)
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Field-Programmable Gate Arrays
http://www.xilinx.com/http://www.altera.com/http://www.actel.com/http://www.atmel.com/http://www.latticesemi.com/http://www.quicklogic.com/http://www.cypress.com/http://www.achronix.com/http://www.cellmatrix.com/http://www.cellmatrix.com/http://www.achronix.com/http://www.cypress.com/http://www.quicklogic.com/http://www.latticesemi.com/http://www.atmel.com/http://www.actel.com/http://www.altera.com/http://www.xilinx.com/http://find/ -
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g y
Logic blocks(Processing elements)
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Example: ProASIC3 Logic VersaTile Cell (Actel)
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p g ( )
0
1
Ground
0
1
0
1
0
1
Via (hard connection)
Switch (Flash connection)
Data
X3
CLK
X2
Enable
X1
CLR/
CLR
XC*
YL
F2
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Example: ProASIC3 Logic VersaTile Cell (Actel)
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p g ( )
Configurations
Any three-input logic function
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set (on a fourth input)
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Example: FLEX 10K Logic Element (Altera)
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g ( )
Carryin
Carryout Cascadeout
CascadeinRegister Bypass
data1data2data3data4
labctrl2labctrl1
ResetChipWide
labctrl3
labctrl4
D
ENA
CLRN
PRN
Q
Lookup
Table
(LUT)
Carry
ChainTo FastTrack
Interconnect
To LAB Loc
Interconnect
Cascade
Chain
Clear/
Preset
Logic
Clock
Select
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Field-Programmable Gate Arrays
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0
1
Configuration bit
16 configuration bits
Routing channels
D Q
LUT
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Field-Programmable Gate Arrays
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0
1
Configuration bit
16 configuration bits
Routing channels
D Q
LUT
Virtex-II FPGA family: 60% of the entire power consumed is dissipated inthe routing fabric (Li Shang et al., Dynamic Power Consumption in Virtex-II FPGAFamily, Proceedings of FPGA 2002)
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Example: Spartan Routing Channels (Xilinx)
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PSM: Programmable Switch Matrix
3 longs 2 doubles
8
singles
3l
ongs
2d
oubles
8 singles
CLB: Configurable Logic Block
PSM
PSM
PSM
PSM
CLB
PSM
PSM
CLB
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Example: Spartan Routing Channels (Xilinx)
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Field-Programmable Gate Arrays
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Configuration bit
16 configuration bits
1
LUT
I/O pads
D Q0
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Field-Programmable Gate Arrays
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Y
A
B
C
B
Y
A
C
LUT
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Example: Virtex-II Clock Distribution (Xilinx)
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SESW
8 BUFGMUX
8 BUFGMUX
16 clocks
NW NE
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Example: Virtex-II Clock Distribution (Xilinx)
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16 clocks
88
8 8
SW
NW
SE
NE
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Example: Virtex-II Digital Clock Management (Xilinx)
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CLKFX180
LOCKED
STATUS[7:0]
PSDONE
(M/D)*FREQ CLKIN
Clock
Pad
CLKIN
CLKOUT
DCM
Clock
Buffer
CLKIN
DSSEN
PSINCDEC
CLKFB
RST
PSCLK
PSEN
DCM
CLK0
Clock Distribution
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
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Example: Virtex-II Digital Clock Management (Xilinx)
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Features
Clock de-skew (eliminate clock distribution delays)Frequency synthesis
Phase shifting
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Field-Programmable Gate Arrays
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SummaryFPGA = configurable logic blocks + programmable interconnects +programmable I/O blocks
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Field-Programmable Gate Arrays
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SummaryFPGA = configurable logic blocks + programmable interconnects +programmable I/O blocks
Additional FeaturesMemory blocks
Dedicated carry logic
Multipliers
DSP blocksProcessors
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Example: Virtex-II Family (Xilinx)
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CLB1 CLB = 4 slices = Max 128 bits SelectRAM Blocks
MaximumSystem Array Distributed Multiplier 18-Kbit Max RAM Max I/O
Device Gates Row Col. Slices RAM Kbits Blocks Blocks (Kbits) DCMs Pads
XC2V40 40K 8 8 256 8 4 4 72 4 88
XC2V80 80K 16
8 512 16 8 8 144 4 120XC2V250 250K 24 16 1,536 48 24 24 432 8 200XC2V500 500K 32 24 3,072 96 32 32 576 8 264XC2V1000 1M 40 32 5,120 160 40 40 720 8 432XC2V1500 1.5M 48 40 7,680 240 48 48 864 8 528XC2V2000 2M 56 48 10,752 336 56 56 1,008 8 624XC2V3000 3M 64 56 14,336 448 96 96 1,728 12 720XC2V4000 4M 80 72 23,040 720 120 120 2,160 12 912XC2V6000 6M 96 88 33,792 1,056 144 144 2,592 12 1,104
XC2V8000 8M 112 104 46,592 1,456 168 168 3,024 12 1,108
Expected frequency: 100 MHz
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Field-Programmable Gate Arrays
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Basic Process Technology TypesSRAM
Based on static memory technologyIn-system programmable and re-programmableRequires external boot devices
(reprinted from http://www.wikipedia.org )
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Field-Programmable Gate Arrays
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Basic Process Technology TypesSRAM
EPROM
Erasable Programmable Read-Only Memory technologyUsually one-time programmable in production because of plasticpackagingWindowed devices can be erased with ultraviolet light.
(reprinted from http://www.wikipedia.org )
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Field-Programmable Gate Arrays
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Basic Process Technology TypesSRAM
EPROM
EEPROM
Electrically Erasable Programmable Read-Only Memory technologyCan be erased, even in plastic packagesSome, but not all, EEPROM devices can be in-system programmed
(reprinted from http://www.wikipedia.org )
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Field-Programmable Gate Arrays
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Basic Process Technology TypesSRAM
EPROM
EEPROM
FLASHFlash-erase EPROM technologyCan be erased, even in plastic packagesSome, but not all, FLASH devices can be in-system programmedUsually, a FLASH cell is smaller than an equivalent EEPROM cell andis therefore less expensive to manufacture
(reprinted from http://www.wikipedia.org )
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Field-Programmable Gate Arrays
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Basic Process Technology Types
SRAM
EPROM
EEPROMFLASH
Fuse and antifuse
One-time programmable
(reprinted from http://www.wikipedia.org )
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Example: Virtex-II Bitstream Lengths (Xilinx)
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Device Data size [bits]
XC2V40 360096
XC2V80 635296
XC2V250 1697184
XC2V500 2761888
XC2V1000 4082592XC2V1500 5659296
XC2V2000 7492000
XC2V3000 10494368
XC2V4000 15659936
XC2V6000 21849504
XC2V8000 29063072
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Example: Stratix II Bitstream Lengths (Altera)
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Device Data size [bits]
EP2S15 4721544
EP2S30 9640672
EP2S60 16951824EP2S90 25699104
EP2S130 37325760
EP2S130 49814760
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Part I: An Introduction to Digital Circuits
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1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design Tools
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Gate Delay
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Y Y
A
Delay
YA
Theory PracticeA
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Gate Delay
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Y Y
A
Delay
YA
Theory PracticeA
Q
Clk
D Q
QQ
D
Delay
Metastability
Clk
D
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Critical Path
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a6a7
Flipflop
y0y1y2y3y4y5y6y7
y0y1y2y3y4
a1 a0a2a3a4a5a6a7 a1 a0a2a3a4a5a6a7
y0
a1 a0a2a3a4a5a6a7
y0y1y2y3y4y5y6y7
a1 a0a2a3a4a5
The longest path determines the delay
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Critical Path
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Sources of Delay in FPGAs
Gate delay
Output load (fanout)Interconnect delay (wire, programmable switch matrix, . . . )
I/O blocks
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Critical Path
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Example: color space converter on a Virtex-II FPGA (Xilinx)
Data Path: CSC_module_Cb_KCM_red_Color_Out_0 to CSC_module_Y_Red_Blue_19
Location Delay type Delay(ns) Physical ResourceLogical Resource(s)
------------------------------------------------- -------------------
SLICE_X37Y67.YQ Tcko 0.493 CSC_module_Cb_KCM_red_Color_Out
CSC_module_Cb_KCM_red_Color_Out_0SLICE_X39Y38.F2 net (fanout=2) 1.438 CSC_module_Cb_KCM_red_Color_Out
SLICE_X39Y38.COUT Topcyf 0.755 CSC_module_Y_Red_Blue
CSC_module_csc__n0016lutCSC_module_csc__n0016cy
CSC_module_csc__n0016cySLICE_X39Y39.CIN net (fanout=1) 0.000 CSC_module_csc__n0016_cyo
SLICE_X39Y39.COUT Tbyp 0.092 CSC_module_Y_Red_BlueCSC_module_csc__n0016cy
CSC_module_csc__n0016cy
... ... ... ...
SLICE_X41Y46.BY net (fanout=1) 0.594 CSC_module__n0016
SLICE_X41Y46.CLK Tdick 0.322 CSC_module_Y_Red_BlueCSC_module_Y_Red_Blue_19
------------------------------------------------- ---------------------------Total 5.595ns (3.563ns logic, 2.032ns route)
(63.7% logic, 36.3% route)
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Critical Path
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How to Minimize the Critical Path?
Hardware design tools (topology, logic optimization)
Number systemsAlgorithms
Pipelining
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Example: Pipelining
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a1a6a7
y0y1y2y3y4
a 5a 4a 3a 2
y0y1y2y3y4
a1 a0a2a3a4a5a6a7a 0
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Example: The IDEA Block Cipher
Plaintext block
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DecryptionEncryption
Private key Private key
Ciphertext block Plaintext block
Chaining mode: Electronic Codebook (ECB)
Each block is encrypted separately
Loop unrolling and pipelining
Encryption rate: 8.5 Gb/s (Virtex-II)
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Example: The IDEA Block Cipher
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Modulo 2 +1 multiplication (3 pipeline stages)
Bitwise XOR
16
16bit register
13 pipeline stages
Subkeys
Modulo 2 addition16
16
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Example: The IDEA Block Cipher
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Encryption Decryption
Register
Register
Private key
Initial vector
Private key
Initial vector
Feedback
Ciphertext blockPlaintext block
Plaintext block
mechanis
m
Chaining mode: Cipher Block Chaining (CBC)
All blocks encrypted sequentially (i.e. only one block in the pipeline)Encryption rate: 0.14 Gb/s (Virtex-II)
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Part I: An Introduction to Digital Circuits
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1 Basic Elements
2 Field Programmable Gate Arrays (FPGAs)
3 High-Speed Design
4 Hardware Design Tools
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Hardware Description Languages (HDLs)
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VHDL
VHDL = VHSICHDL = Very High Speed Integrated Circuits HDL
Development initiated from the American Department of Defense(DoD)
International standards
IEEE Std 1076-1987IEEE Std 1076-1993
Free VHDL booklet: The VHDL Cookbook
http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf
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Hardware Description Languages (HDLs)
http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdfhttp://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdfhttp://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdfhttp://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdfhttp://find/ -
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Other Languages
Verilog
AHDL (Altera HDL)
SystemCABEL (Advanced Boolean Expression Language)
HDCaml
. . .
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FPGA Design Flow
S D i
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Functional Simulation
Design Rule Checking
RTL Viewer
RTL Synthesis
I/O Assignment & Analysis
Power Analysis
Static Timing AnalysisTechnology Map Viewer
BoardLevel Timing
GateLevel Simulation
Formal VerificationBoardLevel Signal
IntegrityAnalysis
System Design
Place & Route
FPGA
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Free Design Tools
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Altera (http://www.altera.com)
Model Technology ModelSim-Altera Software(http://www.model.com)
Quartus II Web Edition SoftwareSchematic- and text-based design entry, integrated VHDL and Verilog HDL
synthesis and support for third-party synthesis software, place-and-route,
verification, and programming functions
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Free Design Tools
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Xilinx (http://www.xilinx.com)
ModelSim Xilinx Edition-III (http://www.model.com)Complete HDL simulation environment that enables to verify the
functional and timing models of the design, and the HDL source codeISE WebPACKHDL (VHDL and Verilog) synthesis and simulation, implementation, device
fitting, and JTAG programming
Jean-Luc Beuchat (LCIS) Digital Arithmetic 56 / 187
Part II: An Introduction to Computer Arithmetic I
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5 Number Systems
Historic ExamplesBasic Number SystemsSigned DigitsResidue Number SystemCarry-Save NumbersHigh-Radix Carry-Save NumbersOther Number Systems
6 AlgorithmsAdditionMultiplication
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Part II: An Introduction to Computer Arithmetic I
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5 Number Systems
Historic ExamplesBasic Number SystemsSigned DigitsResidue Number SystemCarry-Save NumbersHigh-Radix Carry-Save NumbersOther Number Systems
6 AlgorithmsAdditionMultiplication
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Example: Roman Numbers
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Il avint apres la Passion Jhesu Crist, .VII.C. et .XVII. ans, que je, li pluspechierres de tous les autres pecheours. . .
Joseph dArimathie
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Example: Jealousy Multiplication (13th Century)
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3
Multip
lier
Multiplicand
1 3 1 5
Least significant digit
9
7
2
Example: 1315 2793
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Example: Jealousy Multiplication (13th Century)
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20
0
90
7
30
9
27
0
2 1
06
02
0 7
09
30
4
51
5
3 5
10
3
Multip
lier
Multiplicand
1 3 1 5
Least significant digit
9
7
2
Example: 1315 2793Computation of the partial products in con-stant time
Redundant number system
Digit setD = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12,14, 15, 16, 18, 20, 21, 24, 25, 27, 28,30, 32, 35, 36, 40, 42, 45, 48, 49, 54,56, 63, 64, 72, 81}
9 1315 = 9 103
+ 27 102
+ 9 10 + 45= 11835
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Example: Jealousy Multiplication (13th Century)
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0
30
4
51
5
3 5
1
Hundredsofthousands
Units
Tens
HundredsThousandsTensoftho
usands
Millions
Tensofmillions
20
0
90
7
30
9
27
0
2 1
06
02
0 7
09
Example: 1315 2793Computation of the partial products in con-stant time
Redundant number system
Digit setD = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12,14, 15, 16, 18, 20, 21, 24, 25, 27, 28,30, 32, 35, 36, 40, 42, 45, 48, 49, 54,56, 63, 64, 72, 81}
9 1315 = 9 103
+ 27 102
+ 9 10 + 45= 11835
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Example: Jealousy Multiplication (13th Century)
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Carries
630
2
7
9
5
Res
ult
+1
+1
+2
+2
30
279
21
07
0
20 0
60
21
0
35
45
51
09
30
90
07
7
Example: 1315 2793Addition of partial products (carry propaga-tions)
1315 2793 = 3672795
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Basic Number Systems
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Radix-r Unsigned IntegersRepresentation of n-digit unsigned integers in radix r:
X = xn1xn2 . . . x1x0 =n1
i=0xir
i,
where
xi D = {0, 1, 2, . . . , r 1}
X {0, 1, . . . , rn 1}
D is the digit set
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Basic Number Systems
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Example
r = 101291 = 1 103 + 2 102 + 9 101 + 1 100
r = 2
1291 = 1 210 + 0 29 + 1 28 + 0 27 + 0 26 + 0 25 + 0 24 +
1 23 + 0 22 + 1 21 + 1 20
= (10100001011)2
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Basic Number Systems
R di 2 Si d I t Si & M it d
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Radix-2 Signed Integers Sign & Magnitude
Representation of n-bit signed integers:
X = xn1xn2 . . . x1x0 = (1xn1 )
n2i=0
xiri,
wherexi {0, 1}
X {2n1 + 1, . . . , 2n1 1}
0 has two representations
0 = 0 0 . . . 0 (n1)
= 1 0 . . . 0 (n1)
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Basic Number Systems
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Example
0000 = 0
0001 = 1
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 0
1001 = 1
1010 = 2
1011 = 3
1100 = 4
1101 = 5
1110 = 6
1111 = 7
How to add such numbers?
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Basic Number Systems
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Ones Complement
LetY {2n1 + 1, . . . , 2n1 1}
01
3
4
5
6
2
77
6
5
4
3
2
1
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Basic Number Systems
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Ones Complement
LetY {2n1 + 1, . . . , 2n1 1}
Add a bias b to negative valuesso that
Y + b > 2n
1Y + b < 2n
0
1
3
4
5
6
2
77
6
5
4
3
2
1
0
89
12
11
10
13
14
15
Most significant
bit = 0
Most significant
bit = 1
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Basic Number Systems
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Ones Complement
LetY {2n1 + 1, . . . , 2n1 1}
Add a bias b to negative valuesso that
Y + b > 2
n
1Y + b < 2n
Let b = 2n 1
X = Y ifY 0Y + 2n 1 otherwise= Y + 2n 1 mod (2n 1)
0
1
3
4
5
6
2
77
6
5
4
3
2
1
0
89
12
11
10
13
14
15
Most significant
bit = 0
Most significant
bit = 1
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Basic Number Systems
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Ones Complement
X = xn1(2n 1) +
n2i=0
xi2i
Modulo 2n 1 arithmetic
0 has two representations (0 2n 1 (mod 2n 1))
0 = 00 . . . 00 n= 11 . . . 11 n
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Basic Number Systems
Ones Complement
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One s Complement
How to compute Z = X?
Z = (X) mod (2n 1)
= 2n 1 X
=
n1i=0
2i
n1i=0
xi2i
=n1
i=0(1 xi)2
i
=n1i=0
xi2i
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Basic Number Systems
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Example (n = 4 and 2n 1 = 15)
3 + (7) = 4
7 8 (mod 15)(3 + 8) mod 15 = 11
4 11 (mod 15)
01
3
4
5
6
2
77
6
5
4
3
2
1
0
89
12
11
10
13
14
15
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Basic Number Systems
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Example (n = 4 and 2n 1 = 15)
6 + (5) = 1
5 10 (mod 15)(6 + 10) mod 15 = 1
01
3
4
5
6
2
77
6
5
4
3
2
1
0
89
12
11
10
13
14
15
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Basic Number Systems
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Twos Complement
Let Y {2n1, . . . , 2n1 1}
01
3
4
5
6
2
78
7
6
5
4
3
2
1
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Basic Number Systems
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Twos Complement
Let Y {2n1, . . . , 2n1 1}
Add a bias b to negative valuesso that
Y + b > 2n 1
Y + b < 2n
Most significant
bit = 0
Most significant
bit = 1
01
3
4
5
6
2
78
7
6
5
4
3
2
1
89
12
11
10
13
14
15
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Basic Number Systems
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Twos Complement
Let Y {2n1, . . . , 2n1 1}
Add a bias b to negative valuesso that
Y + b > 2n 1
Y + b < 2n
Let b = 2n
X = Y ifY 0
Y + 2n otherwise
= Y + 2n mod 2n
Most significant
bit = 0
Most significant
bit = 1
01
3
4
5
6
2
78
7
6
5
4
3
2
1
89
12
11
10
13
14
15
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Basic Number Systems
Twos Complement
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p
How to compute Z = X?
Z = (X) mod 2n
= 2n X
= 1 +
n1i=0
2i
n1i=0
xi2i
= 1 +n1
i=0(1 xi)2
i
= 1 +n1i=0
xi2i
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Basic Number Systems
Twos Complement Overflow
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Two s Complement Overflow
Operands withopposite signs: no overflow
same sign: overflow iff the sign of the result is different from the signof operands
X Y cn cn1 Overflow
+ + 0 0 No
+ + 0 1 Yes
0 0 No
1 1 No
1 0 Yes
1 1 No
n3
FA
xn1
Overflow
n2
yn2
x
FAFA
s n1s n2 s n3
yn1
cn1
cn
n
xy
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Basic Number Systems
0 1 1 1 1 1
3 + 7 = overflow
0 0 0 0 1 1 0 1
2 + 3 = 5
0 0
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010
FA FAFA FA
10
1
1
0 1
1 1 1 1 1 0 0 1
+ (3)(2) = (5)
1
FA FAFA FA0
1
1 0
1 1 1 0 0 0 1 1
011
+ (7)(3) = overflow
FA FAFA FA
101
0
0
0 0
FA FAFA FA1
0
1 1
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Basic Number Systems
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Twos Complement Sign Extension
0
0 1
FA FAFA FA
1 0 0 0 1 1
011
1 1
FA
01
+ (7)(3) = (10)
FA FAFA FA
0 1 1 1 1 1
3 + 7 = 10
010
FA
0
!!! Fanout !!!
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Signed Digits
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Standard Representation
Radix-r representation of X R:
X =
i=
xiri,
where xi Dr = {0, 1, . . . , r 1}
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Signed Digits
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Standard Representation
Radix-r representation of X R:
X =
i=
xiri,
where xi Dr = {0, 1, . . . , r 1}
Signed DigitsRadix-r representation of X R:
X =
i= xiri,
where
xi D = { , . . . , }
r 1 et 2 + 1 r
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Signed Digits
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Non-Redundant Representation
If 2 + 1 = r, then each number has a single representation
Example
Let r = 3 and D = {1, 0, 1}
Radix 10 0 1 2 3 4 5 6 7 8 9
Radix 3 0 1 11 10 11 111 110 111 101 100
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Signed Digits
Red da t Re ese tatio
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Redundant Representation
If 2 + 1 > r, then some numbers have more than one representation
Example (4-digit numbers)
Let r = 3 and D = {2, 1, 0, 1, 2}
Radix 10 0 1 2 3 4 5 6 7 8 9
0 1 2 10 11 12 20 21 22 100
Radix 312 11 120 121 122 110 111 101 1200
122 121 1220 1221 1222 1210 1211 1201
1222 1221
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
11
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 11 1
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 11 1 1
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
1
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
1 0
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
1 0 2
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
1 0 2 0
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Signed Digits
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PropertyIf 2 + 1 > r, then addition can be performed without carry propagation
Example (r = 10 and D = {9, . . . , 9})
8 7 8 3+ 1 4 1 6
1 1 1 11 1 1 1
1 0 2 0 1
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Signed Digits
Constant-Time Addition (Avizienis)
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Require: X = xn1 . . . x0, Y = yn1 . . . y0, r > 2, r 1, and 2 r + 1Ensure: S = sn . . . s0 = X + Y
1: wn 0; t0 0;2: Do in parallel (i {0, . . . , n 1})
ti+1
1 if xi + yi < + 1
0 if + 1 xi + yi 1
1 if xi + yi > 1
wi xi + yi r ti+1
3: Do in parallel (i {0, . . . , n 1});
si wi + ti
Jean-Luc Beuchat (LCIS) Digital Arithmetic 78 / 187
Signed Digits
8 1 3 68 17 4
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8
w
=1
3t
=1
4t
=1
3
w
=1
2 t
=1
2
w
=1
1w
=0
4
s = 10
s = 01
s = 22
s = 03
s = 14
t
=1
1
w
=1
0 t
=0
0
3 687
Jean-Luc Beuchat (LCIS) Digital Arithmetic 79 / 187
Signed Digits
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Applications
On-line arithmetic
(Modified) Booth recodingRounding to the nearest
Jean-Luc Beuchat (LCIS) Digital Arithmetic 80 / 187
Residue Number System (RNS)
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Goal
Replace an operation on large numbers by several operations (carriedout in parallel) on much smaller operands
Avoid some side-channel attacks (?)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 81 / 187
Residue Number System (RNS)
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Chinese Remainder TheoremFind X {0, . . . , 104} such that
X 1 (mod 3)
X 2 (mod 5)
X 5 (mod 7)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 82 / 187
Residue Number System (RNS)
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Chinese Remainder TheoremFind X {0, . . . , 104} such that
X 1 (mod 3)
X 2 (mod 5)
X 5 (mod 7)
Answer
X = 82
Jean-Luc Beuchat (LCIS) Digital Arithmetic 82 / 187
Residue Number System (RNS)
Solution
We have X = (x1, x2, x3) = (1, 2, 5), m1 = 3, m2 = 5, and m3 = 7.
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Let us define M = m1 m2 m3 = 105 and i such that
i
1 (mod mi),
0 (mod mj) j = i.
Then, X = (1x1 + 2x2 + 3x3) mod M.
Jean-Luc Beuchat (LCIS) Digital Arithmetic 83 / 187
Residue Number System (RNS)
Solution
We have X = (x1, x2, x3) = (1, 2, 5), m1 = 3, m2 = 5, and m3 = 7.
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Let us define M = m1 m2 m3 = 105 and i such that
i
1 (mod mi),
0 (mod mj) j = i.
Then, X = (1x1 + 2x2 + 3x3) mod M.Since gcd(mi, mj) = 1, i = j, we obtain:
i = j=i
mj 1j=i
mj
mod mi
Jean-Luc Beuchat (LCIS) Digital Arithmetic 83 / 187
Residue Number System (RNS)
Solution
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X = 1 5 7 15 7 mod 3 2
+
2 3 7
1
3 7
mod 5
1
+
5 3 5
1
3 5
mod 7
1
mod 105
= (70 + 42 + 75) mod 105= 82
Jean-Luc Beuchat (LCIS) Digital Arithmetic 84 / 187
Residue Number System (RNS)
Chinese Remainder Theorem
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Consider a set of k pairwise relative prime numbers m1, . . . , mn N and
define M =k
i=1
mi. Then,
X x1 (mod m1)...
X xk (mod mk)
has a unique solution (modulo M)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 85 / 187
Residue Number System (RNS)
Addition, Subtraction, and Multiplication
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Let denote the addition, the subtraction, or the multiplication. Then
X Y = ((x1 y1) mod m1, . . . , (xk yk) mod mk)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 86 / 187
Residue Number System (RNS)
Addition, Subtraction, and Multiplication
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Let denote the addition, the subtraction, or the multiplication. Then
X Y = ((x1 y1) mod m1, . . . , (xk yk) mod mk)
ExampleAddition of X = 29 and Y = 53 with the moduli set {7, 11, 13}:
X = (1, 7, 3) and Y = (4, 9, 1)
X + Y = (5, 5, 4)
Since X + Y = 82, we check that 82 = (5, 5, 4)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 86 / 187
Residue Number System (RNS)
Drawback
RNS is not a positional number system
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Example (Moduli set {3, 5, 7})
How to perform a comparison?
5 = (2, 0, 5)27 = (0, 2, 6)
82 = (1, 2, 5)
83 = (2, 3, 6)
84 = (0, 4, 0)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 87 / 187
Mixed Radix System (MRS)
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Definition
X is represented by a k-tuple (x1, x2, . . . , x
k) such that
X = x1 + x2m1 + x
3m1m2 + . . . + x
k
k1i=1
mi
Jean-Luc Beuchat (LCIS) Digital Arithmetic 88 / 187
Mixed Radix System (MRS)
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Computation ofxiSince X mod m1 = x1, we have x
1 = x1
Since X mod m2 = x2, we obtain
x1 + x2m1 x2 (mod m2).
Thus, x2 = (x2 x1) (m
11 (mod m2)) (mod m2)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 89 / 187
Mixed Radix System (MRS)
Computation ofxi1
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Let m1i,j denote the multiplicative inverse of mi modulo mj. Then,
x1 = x1 mod m1
x2 = (x2 x1)m
11,2 mod m2
x3 = ((x3 x1)m11,3 x2)m12,3 mod m3
...
xk = ( ((xk x1)m
11,k x
2)m
12,k
xk1)m1k1,k mod mk
Jean-Luc Beuchat (LCIS) Digital Arithmetic 90 / 187
Mixed Radix System (MRS)
x5
x1
x1
x2
x3
x4
x5
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3x4
x5
m11,5 m5
x5_ x
1m5
ROM
x1
x2
x
Jean-Luc Beuchat (LCIS) Digital Arithmetic 91 / 187
Mixed Radix System (MRS)
Positional Number System
+ m + m m + + k1
m
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x = x1
-
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Conversion Algorithms
Specific moduli sets (e.g. {2n 1, 2n, 2n + 1})
Redundant modulus (Shenoy & Kumaresan)
MRS-based algorithms (e.g. Szabo & Tanaka)
. . .
Jean-Luc Beuchat (LCIS) Digital Arithmetic 93 / 187
Residue Number System (RNS)
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Applications
Digital signal processing
Cryptography (?)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 94 / 187
Residue Number System (RNS)
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Applications
Digital signal processing
Cryptography (?)
Warning
RNS is not a carry-free number system!
Jean-Luc Beuchat (LCIS) Digital Arithmetic 94 / 187
Carry-Save Numbers
1 1 1 1 0
1 110110
1
1
0 0
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101010101
Jean-Luc Beuchat (LCIS) Digital Arithmetic 95 / 187
Carry-Save Numbers
0
11
1
0
1
0
0
1
1
0
1
1
1
1
1
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10100
011010
1
1
Sum bits
Carry bits
1st digit2nd digit
0
00
X =n1
i=0 xi2i,
where xi {0, 1, 2}
Jean-Luc Beuchat (LCIS) Digital Arithmetic 95 / 187
Carry-Save Numbers
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Example
1 = (0001)2
2 = (0002)2 = (0010)2
341 = (101010101)2 = (100202101)2
Jean-Luc Beuchat (LCIS) Digital Arithmetic 96 / 187
High-Radix Carry-Save Numbers
Replace the sum bit of the carry-save representation by a sum word
Example
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Example
9
1
7
1
2
0
3
1
2
1
0
0
0
0
1
0
1
words
Carry bits
Sum
1
1 0 1
15
0
2
0
12
10
2 2
X = ((1, 5), (0, 0), (1, 3), (1, 6), (0, 4))
= 1 215 + (5 + 0) 212 + (0 + 1) 29 +
(3 + 1) 27 + (6 + 0) 23 + 4 = 54324
Jean-Luc Beuchat (LCIS) Digital Arithmetic 97 / 187
Number Systems
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Other Number Systems
Floating-point numbers (IEEE 754)
Logarithmic Number System
RN-codings
. . .
Jean-Luc Beuchat (LCIS) Digital Arithmetic 98 / 187
Part II: An Introduction to Computer Arithmetic I
5 Number SystemsHistoric ExamplesBasic Number Systems
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Basic Number SystemsSigned DigitsResidue Number SystemCarry-Save Numbers
High-Radix Carry-Save NumbersOther Number Systems
6 Algorithms
AdditionMultiplication
Jean-Luc Beuchat (LCIS) Digital Arithmetic 99 / 187
Addition Counters
(m, k)-Counter
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( , ) Counter
Computes the sum of m input bits a0, . . . , am1 of the samemagnitude
Returns a k-bit sum S, where k = log2(m + 1)
k1i=0
si2i =
m1i=0
ai
Jean-Luc Beuchat (LCIS) Digital Arithmetic 100 / 187
Addition Counters
Example (Half-Adder or (2, 2)-Counter)
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a p e ( a dde o ( ) Cou te )
2cout + s = a + b
s = (a + b) mod 2 = a bcout = (a + b) mod 2 = ab
cout
cout
a b
s
a b
s
HA
Jean-Luc Beuchat (LCIS) Digital Arithmetic 101 / 187
Addition Counters
Example (Full-Adder or (3, 2)-Counter)
2cout + s = a + b+ cin
s = (a + b + cin) mod 2 = a b cin
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s (a + b+ cin) mod 2 a b cin
cout = ab+ acin + bcin
cincout FA
a b
s
0
1
a b
s
coutcin
Jean-Luc Beuchat (LCIS) Digital Arithmetic 102 / 187
Addition Counters
Example ((7, 3)-Counter)
5a
6a
6a
5a
4a
3a
2a
1a
0a
0a
1a
2a
3a
4a
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s 2 s 1 s 0
FA FA
FA
FA
s2
s1
s0
Crit
icalpath
FA
FA
FA
FA
Jean-Luc Beuchat (LCIS) Digital Arithmetic 103 / 187
Addition Carry-Ripple Adder
Addition of two n-bit operands
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n 1 FAs and 1 HA connected in series
Average length of the longest carry chain: L(n) log2 n
4 x3 x2 x1 x0
s 6 s 5 s 4 s 3 s 2 s 1 s 0
y0y1y2y3y4y5y6y7
s 7s 8
HAFAFAFAFAFAFAFA
x7 x6 x5 x
Jean-Luc Beuchat (LCIS) Digital Arithmetic 104 / 187
Addition Example: Virtex Family (Xilinx)
COUT
YB
Y
YQ
LUT
WE DI
CY
0
O
G4
G3
G2G1
INITQD
EC
I3
I2
I1I0
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BY
F5IN
BX
F5
CE
CLK
SR
CIN
XB
X
XQ
F5
REV
REVLUT
WE
O
DI
F6CY
0
1
0
1
CK WSOWE
A4 WSH
BY
BX DI
DG
F4
F3
F2
F1
EC
INITQD
EC
I3
I2
I1
I0
Jean-Luc Beuchat (LCIS) Digital Arithmetic 105 / 187
Addition Carry-Select Adder
00
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1
0
10
1
1
0
10
1
!!! Fanout !!! !!! Fanout !!!
Jean-Luc Beuchat (LCIS) Digital Arithmetic 106 / 187
Addition Example: Stratix Family (Altera)
LAB CarryIn
CarryIn0
CarryIn1
data1data2
Sum
LAB CarryIn
Sum2
Sum1
Sum3
LE1
LE2
0 1
B1
A1
B2
A2
B3A3 LE3
LE1
LE1
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CarryOut0 CarryOut1
LAB CarryOut
Sum4
Sum5
Sum6
Sum7
Sum8
Sum9
Sum10
LE6
LE7
LE8
LE9
0 1
LE10
B6
A6
B7
A7
B8
A8
B9
A9
B10
A10
LE4
LE5
B4
A4
B5
A5
LE1
LE1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 107 / 187
Addition Carry Propagation & Generation
c 4c 5FA
x3 y3
FA
x5 y5 11
FA
xi yi si ci+1 Description
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3
s 4 s 3s 5
FA
x5
s 5
y5
4
c 4c 5
FA
x3
s 3
y0 1
s
FA
0 0 ci 0 Generate0 1 ci ci Propagate1 0 ci ci Propagate1 1 0 1 Generate
Generate: g = xiyi
Propagate: p = xi yi
Kill: k = xi + yi
Jean-Luc Beuchat (LCIS) Digital Arithmetic 108 / 187
Addition Carry-Skip Adder
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1
0
Propagate
1
0
Propagate
1
0
Propagate
Jean-Luc Beuchat (LCIS) Digital Arithmetic 109 / 187
Addition Parallel-Prefix Adder
Full-Adder Cell
ci +1 = gi + pi ciGP
xi yi
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i+1 gi + pi i
si = pi ci
i
gi pi
i+1cc i
s
Jean-Luc Beuchat (LCIS) Digital Arithmetic 110 / 187
Addition Parallel-Prefix Adder
Full-Adder Cell
ci +1 = gi + pi ciGP
xi yi
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i+1 gi pi i
si = pi ci
c1 = g0 + p0c0
c2 = g1 + p1g0 + p1p0c0
c3 = g2 + p2g1 + p2p1g0 + p2p1p0c0
. . . = . . .i
gi pi
i+1cc i
s
Jean-Luc Beuchat (LCIS) Digital Arithmetic 110 / 187
Addition Parallel-Prefix Adder
Parallel-Prefix Problem
n outputs (bn1, . . . , b0) are computed from n inputs (an1, . . . , a0) using
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an associative operator :
b0 = a0
b1 = a1 a0b2 = a2 a1 a0
. . . = . . .
bn1 = an1 . . . a2 a1 a0
Jean-Luc Beuchat (LCIS) Digital Arithmetic 111 / 187
Addition Parallel-Prefix Adder
7 a6 a5 a4 a3 a2 a1 a0a
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b7 b6 b5 b4 b3 b2 b1 b0
Jean-Luc Beuchat (LCIS) Digital Arithmetic 112 / 187
Addition Parallel-Prefix Adder
7a a6 a5 a 4 a 3 a 2 a 1 a 0 7a a6 a 5 a 4 a 3 a 2 a 1 a 0
7a a
6a
5a
4a
3a
2a
1a
0
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Sklansky HanCarlson
BrentKungCarryRipple
KoggeStone
6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0b b6 b5 b4 b3 b2 b1 b0
7a a6 a5 a 4 a 3 a 2 a 1 a 0 7a a6 a 5 a 4 a 3 a 2 a 1 a 0
7
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
b7 b
Jean-Luc Beuchat (LCIS) Digital Arithmetic 113 / 187
Addition Parallel-Prefix Adder
Algorithm Delay Area Fanout
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Carry-ripple n 1 n 1 2
Brent-Kung 2log2 n 2 2n log2 n 2 log2 n
Sklansky log2 n12 n log2 n
12 n
Han-Carlson log2 n + 1 12 n log2 n 2Kogge-Stone log2 n n log2 n n + 1 2
Jean-Luc Beuchat (LCIS) Digital Arithmetic 114 / 187
Addition Parallel-Prefix Adder
Addition as a Parallel-Prefix Problem1 Compute the gi = xiyi and pi = ai bi signals for all inputs.
2 Compute the ci signals using a m-level parallel-prefix graph:
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G0i:i, P
0i,i
= (gi, pi)
Gli:k, P
li:k = G
l1i:j , P
l1i:j G
l1j:k , P
l1j:k
=
Gl1i:j + Pl1i:j G
l1j:k , P
l1i:j P
l1j:k
, k j i, 1 l m
ci+1 = Gmi:0 + P
mi:0c0, 0 i n 1
3 Compute the sum:
si = pi ci, i {0, 1, . . . , n 1}
Jean-Luc Beuchat (LCIS) Digital Arithmetic 115 / 187
Addition Parallel-Prefix Adder
p1g1 g0 p0
x1 y1 x0 y0xn1 yn1 xn2 yn2
GP GP
1
1
2
2
GP GP
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s 0
c0c1cn1 cn2
p1g1 g0 p0
s n1s n
ParallelPrefix Network
pn
gn
gn
pn
c0
s n2 s 1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 116 / 187
Addition Borrow-Save Adder
Borrow-Save Representation
Redundant Radix-2 representationDigits ai {1 0 1}
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Digits ai {1, 0, 1}
ai = a+i a
i , with a
+i and a
i {0, 1}
a
+
i a
i ai0 0 0
0 1 1
1 0 1
1 1 0
Jean-Luc Beuchat (LCIS) Digital Arithmetic 117 / 187
Addition Borrow-Save Adder
PPM Cell
FA CellPPM Cell
2t+ t = a+ a + b+
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2cout + s = a + b+ cin 2t + t+ = a + a+ b
+
a+
b
+
t
+
a
+
t
+
t+
t
+
b+
a+
a
FA
a b
s
0
c 1incout
coutcin
s
a b
0
1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 118 / 187
Addition Borrow-Save Adder
4 x
+
3 x
3 y
+
3 y
3 x
+
2 x
2 y
+
2 y
2 x
+
1 x
1 y
+
1 y
1 x
+
0 x
0 y
+
0 y
0 0 0x
+
4 x
4 y
+
4 y
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+ ++
+ ++
+ ++
+ + + + + + + + + +
t +5
t 5
t +4
t 4
t +3
t 3
t +2
t 2
t +1
t 1
t +0
t 0
+ ++
+ ++
Jean-Luc Beuchat (LCIS) Digital Arithmetic 119 / 187
Addition Carry-Save Adder
Addition of Three Numbers
Three binary operands or one binary and one carry-save operands
Array of FAs
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Array of FAs
Intermediate carries treated as outputs
Constant delay
0 z 0
c 1
FAFAFAFA FAFA
x2 y2y3x3y4x4y5x5y6x6x7 y7 z 7 z 6 z 5 z 4 z 3 z 2
s 2s 3s 4s 5s 6s 7 c 2c 3c 4c 5c 6c 7c 8
FA
x1 y1 z 1
s 1
FA
s 0
x0 y
Jean-Luc Beuchat (LCIS) Digital Arithmetic 120 / 187
Addition Carry-Save Adder
(4, 2)-Compressor
2( )3 0
(4 2) ci
FA
cincout
x0x3 x2 x1
x3
x1
x2
x
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2(c + cout) + s =i=0
xi + cin(4, 2)
c s
coutcin
FA
c s
Jean-Luc Beuchat (LCIS) Digital Arithmetic 121 / 187
Addition Carry-Save Adder
(4, 2)-Compressor
2( + ) +3
+
0
(4 2)c ci
FA
cincout
x0x3 x2 x1
x3
x1
x2
x
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2(c + cout) + s =i=0
xi + cin(4, 2)
c s
coutcin
FA
c s
2 1x
0
coutcin
c s
10
10
x3
x x
Circuit optimizations
Construction of more shallow
and regular tree structures
Jean-Luc Beuchat (LCIS) Digital Arithmetic 121 / 187
Addition Carry-Save Adder
(m, 2)-Compressor
2
c +m4
ciout
+ s =
m1xi +
m4ciin
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i=0
i=0 i=0
Application: multi-operand adder
(6, 2) (6, 2) (6, 2) (6, 2)
(5, 3)counter
cin0
sc
x0xm1
(m, 2).
.
.
.
.
.
0cout
coutm4
cinm4
FA HAFA
FA
HA FA
Jean-Luc Beuchat (LCIS) Digital Arithmetic 122 / 187
Addition Addition on a Virtex FPGA (Xilinx)
Algorithm 16 bits 32 bits 64 bits
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Algorithm 16 bits 32 bits 64 bits
Carry-Ripple 16 LUTs / 160 MHz 32 LUTs / 121 MHz 64 LUTs / 82 MHz
Brent-Kung 143 LUTs / 73 MHz 194 LUTs / 46 MHz 368 LUTs / 36 MHz
Sklansky 100 LUTs / 64 MHz 177 LUTs / 52 MHz 190 LUTs / 12 MHz
Carry-Save 32 LUTs / 320 MHz 64 LUTs / 320 MHz 128 LUTs / 320 MHz
Borrow-Save 108 LUTs / 185 MHz 220 LUTs / 185 MHz 444 LUTs / 185 MHz
Jean-Luc Beuchat (LCIS) Digital Arithmetic 123 / 187
Addition Ones Complement Addition
Modulo (2n 1) Addition (Single Representation of Zero)
(X + Y) mod (2n 1) = (X + Y + 1) mod 2n ifX + Y + 1 2n,(X + Y) mod 2n otherwise
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X Y
0 1
1
S
1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 124 / 187
Addition Ones Complement Addition
Modulo (2n 1) Addition (Double Representation of Zero)
(X + Y) mod (2n 1) = (X + Y + 1) mod 2n ifX + Y 2n,(X + Y) mod 2n otherwise
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= (X + Y + cout) mod 2
n
Y
3
X Y
0 1
1
S2
S
X
Jean-Luc Beuchat (LCIS) Digital Arithmetic 125 / 187
Addition Ones Complement Addition
Modulo (2n 1) Addition (Single Representation of Zero)
(X + Y) mod (2n 1)
= ((X + Y + 1) mod 2n + cout (2n 1)) mod 2n
= ((X + Y + 1) mod 2n cout) mod 2n
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(( ) )
1
S
X Y4
Jean-Luc Beuchat (LCIS) Digital Arithmetic 126 / 187
Addition Ones Complement Addition
Comparison on a XCV50E FPGA (Xilinx)n = 4 n = 8 n = 12 n = 16 n = 20 n = 24 n = 28 n = 32
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n = 4 n = 8 n = 12 n = 16 n = 20 n = 24 n = 28 n = 32
6 slices 12 slices 18 slices 24 slices 30 slices 36 slices 42 slices 48 slices8.1 ns 9.6 ns 10.5 ns 11.2 ns 12.4 ns 12.8 ns 13.7 ns 14.9 ns
6 slices 12 slices 18 slices 24 slices 30 slices 36 slices 42 slices 48 slices8.2 ns 9.5 ns 10.7 ns 11.2 ns 12.6 ns 13.5 ns 13.7 ns 14.9 ns
4 slices 8 slices 12 slices 16 slices 20 slices 24 slices 28 slices 32 slices9.1 ns 9.9 ns 11.7 ns 12.5 ns 13.8 ns 16.1 ns 16.3 ns 18.1 ns
4 slices 8 slices 12 slices 16 slices 20 slices 24 slices 28 slices 32 slices8.7 ns 10.8 ns 11.4 ns 12.4 ns 13.4 ns 16.1 ns 15.8 ns 16.3 ns
Jean-Luc Beuchat (LCIS) Digital Arithmetic 127 / 187
Multiplication Shift-and-Add Algorithms
Paper-and-Pencil AlgorithmRequire: An n-bit operand X and an operand YE P XY
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Ensure: P = XY1: P 0;2: for i = 0 to n 1 do3: P P + 2ixiY;4: end for
Drawback: requires a variable shifter
Jean-Luc Beuchat (LCIS) Digital Arithmetic 129 / 187
Multiplication Shift-and-Add Algorithms
Constant Shift AlgorithmRequire: An n-bit operand X and an operand YE P XY
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Ensure: P = XY1: P 0;2: for i = 0 to n 1 do3: P (P + xiY) 21;4: end for5: P 2nP;
Jean-Luc Beuchat (LCIS) Digital Arithmetic 131 / 187
Multiplication Shift-and-Add Algorithms
ym1
y0
ym2
Shift...
XLd
x iShift Register
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Register
Clr
Free!
Jean-Luc Beuchat (LCIS) Digital Arithmetic 132 / 187
Multiplication Modified Booth Recoding
Booth Recoding
Originally proposed to reduce the number of partial products in
multiplicationMultiplier written on the digit set {1, 0, 1} (1 = 1)
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11111111
8 1 0000000
71
Property: sign alternation of non-zero digits
10 . . . 010 . . . 011
Drawback:10101 111111
Jean-Luc Beuchat (LCIS) Digital Arithmetic 133 / 187
Multiplication Modified Booth Recoding
Booth RecodingRequire: An (n + 1)-bit twos complement number
X { 2n 2n 1} ith 0
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X {2n, . . . , 2n 1} with x1 = 0Ensure: An (n + 1)-digit radix-2 number Y such that X = Y and
yi {1, 0, 1}1: for i = 0 to n do2: yi xi1 xi;3: end for
Jean-Luc Beuchat (LCIS) Digital Arithmetic 135 / 187
Multiplication Modified Booth Recoding
Radix-4 Modified Booth Recoding
Let Y be the Booth recoding of X
Radix-4 recoding of Y
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zi = 2y2i+1 + y2i= 2x2i 2x2i+1 + x2i1 x2i
= 2x2i+1 + x2i + x2i1 z0
z1
z2
y0
y1
y2
y3
y4
Digit set: zi {2, 1, 0, 1, 2}
Jean-Luc Beuchat (LCIS) Digital Arithmetic 136 / 187
Multiplication Modified Booth Recoding
Example
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(1111111)2 (2001)4 = 2 43 1 = 127
(1110111)2 (212
1)4 = 2 4
3
4
2
+ 2 4
1
1 = 119(1010101)2 (1111)4 = 4
3 + 42 + 41 + 1 = 85
Jean-Luc Beuchat (LCIS) Digital Arithmetic 137 / 187
Multiplication Multiplier-Based Operators
Programmable interconnects
Programmable Input/Output block
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Multiplier block
Configurable Logic
Memory block
Configurable Logic Block (CLB)
Programmable I/Os
Virtex-II family (Xilinx): dedicated 18-bit18-bit multiplier blocks withtwo independent data input ports: 18-bit signed or 17-bit unsigned
Jean-Luc Beuchat (LCIS) Digital Arithmetic 138 / 187
Multiplication Multiplier-Based Operators
net
Tmult
Critical path
(a) Embedded multiplier
Critical path
MULT18x18
Tiockiq
FF
FF
net
Tioock
FF
FF
4 5
5
5.5
6
6.5
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Tmultck
use virtex2.components.all
mult: MULT18x18S port map (
P => XY,
A => X,
B => Y,
C => Clk,
CE => Ce,
R => Clr);
. . .
library virtex2;
(b) Embedded multiplier with an internal
pipeline stage
MULT18x18S
net
Tioock
FF
FFFF
FF
1.5
2
2.5
3
3.5
4
4.5
36302520151051
Delay[ns]
Output size
MULT18x18 MULT18x18S
Jean-Luc Beuchat (LCIS) Digital Arithmetic 139 / 187
Multiplication Multiplier-Based Operators
Divide-and-Conquer
(X1k + X0)(Y1k + Y0) = X1Y1k2 + (X1Y0 + X0Y1)k + X0Y0
n bitsX0
3:0
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X1 * Y0 * k
X0 * Y0
X0 * Y1 * k
X1 * Y1 * k * k
X0X1
Y1 Y0
Y0
X1
Y1
X0
Y1
X1
Y0
concatenation
5:0
3:0
7:4
&
&
Requires 4 multiplier blocks and 2 adders
Jean-Luc Beuchat (LCIS) Digital Arithmetic 140 / 187
Multiplication Multiplier-Based Operators
Karatsuba
(X1k + X0)(Y1k + Y0) = X1Y1(k2 k)+
(X1 + X0)(Y1 + Y0)k + X0Y0(1 k)
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X0X1
Y1 Y0
X0 * Y0
X1 * Y1 * k * k
X1 * Y1 * k
Sign extension
(X0+X1) * (Y0+Y1) * k
X0 * Y0 * k
X0
X1
Y1
Y0
X0
Y0
X1
Y1
13:4 3:0
&
&
Requires 3 multiplier blocks, 3 adders, and 2 subtracters
Jean-Luc Beuchat (LCIS) Digital Arithmetic 141 / 187
Multiplication Multiplier-Based Operators
New Algorithm
. . .
. . .
. . .
. . .
. . .
0
. . .
. . .
0
00
0 0
0
0
0
0
00
00 0
0
PP0
PP1
PP2
PP3m bits
n = 17
X0
Y0
X1
Y1
n = 17
(b) Addi h i l d
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. . .
. . .
. . .
. . .
. . .
...
. . .
...
..
.
. . .
. . .
..
.
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
PP3
PP2 PP0
PP1
n=17
n = 17 MULT18x18
mn
partia
lprodu
cts
PP0
PP1
PP2
PP3
(a) Proposed multiplier (c) Adding the partial products (tree structure)
(b) Adding the partial products
Requires only one multiplier block and some glue adders
Jean-Luc Beuchat (LCIS) Digital Arithmetic 142 / 187
Multiplication Multiplier-Based Operators
300
350
400
450
500
4321
licenumber
8x18blocknum
ber
17
18
19
20
21
22
Delay[ns]
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0
50
100
150
200
250
18 20 22 24 26 28 30 32
Sl
MULT18
Operand size
Div & conq Karatsuba New algo
13
14
15
16
18 20 22 24 26 28 30 32
Operand size
Div & conq Karatsuba New algo
The architecture depends on the operand size
Karatsuba is larger and slower than divide-and-conquer
Jean-Luc Beuchat (LCIS) Digital Arithmetic 143 / 187
Part III: Arithmetic Operators for Cryptography
7 Modular Addition
8 Modular MultiplicationH R l
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Horners RuleModular Multiplication and FPGAs
Modular Multiplication of Small Numbers on FPGAModular Multiplication of Large Numbers on FPGA
9 Conclusion
Jean-Luc Beuchat (LCIS) Digital Arithmetic 144 / 187
Applications of Modular Arithmetic
CryptographyModular exponentiation (RSA, ElGamal, . . . )
P i fi ld i h i (ECC F XTR )
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Prime field arithmetic (ECC over Fp, XTR, . . . )
Binary field arithmetic (ECC over F2m , AES, McEliece, . . . )
Optimal extension field arithmetic (ECC, . . . )
Modulo (2n + 1) multiplication (IDEA)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 145 / 187
Applications of Modular Arithmetic
Residue Number System (RNS)
Replace an operation on large operands by several modular operationsperformed in parallel on small operands.
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128 128
128
i(x +y ) mod mi i
16 16
j(x +y ) mod mj j
1616
. . .
1616
Jean-Luc Beuchat (LCIS) Digital Arithmetic 146 / 187
Part III: Arithmetic Operators for Cryptography
7 Modular Addition
8 Modular MultiplicationH R l
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Horner s RuleModular Multiplication and FPGAs
Modular Multiplication of Small Numbers on FPGAModular Multiplication of Large Numbers on FPGA
9 Conclusion
Jean-Luc Beuchat (LCIS) Digital Arithmetic 147 / 187
Modular Addition
Algorithm
X, Y, and M are n-bit numbers
X, Y {0, 1, . . . , M 1}
(X + Y) mod M =
X + Y if0 X + Y < M,
X + Y M otherwise
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YX
(X+Y) mod M
0 1
(X+Y) mod M
M
YX YX
M
(X+Y) mod M
M
0 1
2 Mn
Jean-Luc Beuchat (LCIS) Digital Arithmetic 148 / 187
Modular Addition
Specific Moduli
2n 1
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2n + 1
2n
2k
1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 149 / 187
Part III: Arithmetic Operators for Cryptography
7 Modular Addition
8 Modular MultiplicationHorners Rule
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Horner s RuleModular Multiplication and FPGAs
Modular Multiplication of Small Numbers on FPGAModular Multiplication of Large Numbers on FPGA
9 Conclusion
Jean-Luc Beuchat (LCIS) Digital Arithmetic 150 / 187
Modular Multiplication
MSDF algorithms
Parallel operator
+
Circuit areaHigh throughput (pipeline)
Parallelserial operator
Lookup tables
( t d
Iterative algorithm+
The architecture does not depend on M
LSDF algorithms
Modulo M multiplier
Sum of moduloreduced
ti l d t
Multiplication with
b t d l
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calculus)
(quartersquared
multiplier, index
of a VHDL descriptionAutomatic generation
Fermat numbers
Mersenne numbers
Montgomery
Kornerup
. . .
of a VHDL descriptionAutomatic generation
Fermat numbers
Mersenne numbers
partial productssubsequent modulo
correction
Bipartite Modular Multiplication
(Kaihara and Takagi)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 151 / 187
Modular Multiplication
Horners Rule
XY = ( ((xr1Y)2 + xr2Y)2 + + x1Y)2 + x0Y
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2
2
2
Y
Q[1]
Y
Y
Y
x0x1
xr2
xr1
Q[0]=XY
Jean-Luc Beuchat (LCIS) Digital Arithmetic 152 / 187
Modular Multiplication
Horners Rule
Require: An r-bit number X N and Y NEnsure: Q[0] = XY
1: Q[r] 0;2: for i in r 1 downto 0 do3: Q[i ] 2Q[i + 1] + xi Y ;
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3: Q[i] 2Q[i + 1] + xiY;4: end for
x i
Y
Q[i]
Q[i+1]
2
Jean-Luc Beuchat (LCIS) Digital Arithmetic 152 / 187
Modular Multiplication
Horners Rule & Modular Multiplication
Require: An n-bit modulus M, an r-bit number X N, andY {0, . . . , M 1}
Ensure: P[0] = XY mod M1: P[r] 0;2: for i in r 1 downto 0 do
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3: P[i] (2P[i + 1] + xiY) mod M;
4: end for
0
M
2M
Critical path
2
x iMY
P[i]
P[i+1]
< M
< 2M
Jean-Luc Beuchat (LCIS) Digital Arithmetic 153 / 187
Modular Multiplication
QuestionIs it possible to shorten the critical path?
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Solution
Compute an (n + 1)-bit number P[i] such that
P[i] 2P[i + 1] + xiY (mod M)
Jean-Luc Beuchat (LCIS) Digital Arithmetic 154 / 187
Modular Multiplication
ASIC-Oriented AlgorithmsCarry-saveC. K. Koc and C. Y. Hung, Y.-J. Jeong and W. P. Burleson, S. Kim
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g, g ,and G. E. Sobelman, E. Peeters, M. Neve, and M. Ciet
Signed digitsN. Takagi and S. Yajima, N. Takagi
Jean-Luc Beuchat (LCIS) Digital Arithmetic 155 / 187
Modular Multiplication and FPGAs
Programmable interconnects
Programmable Input/Output block
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Multiplier block
Configurable Logic
Memory block
Configurable Logic Block (CLB)
Programmable I/Os
Jean-Luc Beuchat (LCIS) Digital Arithmetic 156 / 187
Modular Multiplication and FPGAs
Slice of a Xilinx FPGA
Slice
0 1
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0 1
Jean-Luc Beuchat (LCIS) Digital Arithmetic 158 / 187
Modular Multiplication and FPGAs
Dedicated carry logic
0 1
Slice
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FA cell
10
Jean-Luc Beuchat (LCIS) Digital Arithmetic 158 / 187
Modular Multiplication and FPGAs
Carry-save adder
0 1
cout
Slice
x
e n t i t y f a i s
p o r t (X : i n s t d l o g i c ;Y : i n s t d l o g i c ;C in : i n s t d l o g i c ;C ou t : out s t d l o g i c ;S : out s t d l o g i c ) ;
d f
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FA cell
1
x
cout
s
0
Majx
cin
y
cin
y
en d f a ;
a r c h i t e c t u r e b e h a v i o r a l o f f a i s
s i g n a l x x o r y : s t d l o g i c ;b e g i n b e h a v i o r a l x x o r y
-
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FA cell
1
cout
0
cin
x
y
s
p o r t map (O => Cout ,CI =