KIN THC C BN V VHDL

VHDL l vit tt ca cm t Very High Speed Intergrated Circuit Hardware Description Language - ngn ng m t phn cng cho cc mch tch hp tc rt cao. VHDL l ngn ng m t phn cng c pht trin dng cho chng trnh VHSIC (Very High Speed Intergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m t phn cng tiu chun v thng nht cho php pht trin th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics, IBM v Texas Instruments bt u nghin cu pht trin vo 7/1983. Phin bn u tin c cng b vo 8/1985. Sau VHDL c xut t chc IEEE xem xt thnh mt tiu chun. Nm 1987, a ra tiu chun v VHDL tiu chun IEEE-1076-1987. VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu ti liu k lng. Vi mt ngn ng m t phn cng th vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th c thc thi m phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trong mt m hnh thng nht. Trc khi VHDL ra i, c nhiu ngn ng m t phn cng c s dng nhng khng c mt tiu chun thng nht. V cc ngn ng m phng phn cng c cc nh cung cp thit b pht trin, nn mang cc c trng gn vi cc thit b ca nh cung cp v thuc s hu ca nh cung cp. Trong khi , VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k, b m phng hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi vn s dng mt ngn ng duy nht. VHDL c mt s u im hn hn cc ngn ng m t phn cng khc l:

Tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v hin nay l mt tiu chun ca IEEE, VHDL khng thuc s hu ca bt k c nhn hay t chc no. Do VHDL c h tr ca nhiu nh sn1

xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng. y l mt u im ni bt ca VHDL, gip VHDL tr nn ngy cng ph bin.

Kh nng h tr nhiu cng ngh v phng php thit k: VHDL cho php thit k bng nhiu phng php nh phng php thit k t trn xung, hay t di ln da vo cc th vin c sn. Nh vy VHDL c th phc v tt cho nhiu mc ch thit k khc nhau, t vic thit k cc phn t ph bin n vic thit k cc IC ng dng c bit (Application Specified IC). c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc vo cng ngh ch to phn cng no c s dng (dng CMOS, nMOS, hay GaAs). y cng l mt u im quan trng ca VHDL n cho php ngi thit k khng cn quan tm n cng ngh phn cng khi thit k h thng, nh th khi c mt cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k. Kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s (hp en) cho n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t mc cao v cc h con c m t chi tit. Kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m phng p ng c tiu chun VHDL v cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun theo chun VHDL. Hn na, mt nhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thng; trong khi cc h con c thit k c lp. Kh nng h tr thit k mc ln v kh nng s dng li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th s dng thit k mt h thng ln vi s tham gia ca mt nhm

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nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s thit k. VHDL cng cho php dng li cc phn c sn.

3.1. CC CU TRC C BN CA NGN NG VHDLCc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm nhm c bn nh sau: - Entity - Architecture - Package - Configuration. - Library. Entity: Trong mt h thng s, thng thng c thit k theo mt s xp chng cc Modul, m mi Modul ny tng ng vi mt thc th thit k (c gi l Entity) trong VHDL. Mi mt Entity bao gm hai phn: - Khai bo thc th ( Entity). - Thn kin trc ( Architecture Bodies ) Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t (component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn t . Phn thn ca kin trc c dng m t s thc hin bn trong ca thc th . Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny c s dng bi mt vi Entity no . Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t cn dng no ca mt thit k no c dng mt cu trc v a cc th hin ny vo trong cp Entity v Architecture. N cho php ngi thit k c th th nghim thay i cc s thc thi khc nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v th vin, m mt trong cc th vin ny c dch sn v ct trong mt th vin thit k.

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3.1.1. Khai bo EntityNh trn cp, phn khai bo Entity ch a ra mt ci nhn pha bn ngoi ca mt phn t m khng cung cp thng tin v s thc hin ca phn t nh th no. C php khai bo ca mt Entity nh sau: Entity entity_name is [generic (generic_declaration);] [port (port_declaration);] {entity_declarative_item {constants, types, signals};} end [entity_name]; [] : Du ngoc vung ch ra cc tham s c th la chn. | : Du gch ng hin th mt s la chn trong s cc la chn khc. {} : Khai bo mt hoc nhiu cc i tng, m cc i tng ny c th c nh ngha bi ngi dng. a. Khai bo Generic: Dng khai bo cc hng m chng c th c dng iu khin cu trc v s hot ng ca Entity. C php ca khai bo ny nh sau: generic ( constant_name : type [:=init_value] {;constant_name: type[:=init_value]});

y tn hng constant_name ch ra tn ca mt hng dng generic (hng dng chung). Kiu (Type) c dng ch ra kiu d liu ca hng.

Init_value : ch ra gi tr khi to cho hng. b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity. C php ca khai bo ny nh sau: Port ( port_name : [mode] type [:= init_value] {; port_name:[mode] type [:=init_value]}); Port_name c dng ch ra tn ca mt cng, mode ch ra hng vo ra ca tn hiu ti cng . Type ch ra kiu d liu ca mt cng v init_value ch ra gi tr khi to cho cng . Ch ! Vi VHDL khng phn bit ch hoa v ch thng, chng hn nh: xyz = xYz = XYZ.

C bn mode c s dng trong khai bo cng: - in: Ch c th c c, n ch c dng cho cc tn hiu u vo (ch c php nm bn phi php gn).4

- out: Ch c dng gn gi tr, n ch c dng cho cc cng u ra (n ch c nm bn tri ca php gn). - inout: C th c dng c v gn gi tr. N c th c nhiu hn mt hng iu khin (c th nm bn tri hoc bn phi php gn). - Buffer: C th c dng c v gn gi tr (c th nm bn tri hoc bn phi php gn). Inout l mt cng hai hng, cn Buffer l mt cng khng c hng. c. Entity_declarative_item : c dng khai bo cc hng, kiu d liu, hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity. d. V d : V d v khai bo cc cng vo ra: entity xxx is port ( A : in integer ; B : in integer ; C : out integer ; D : inout integer ; E : buffer integer) ; end xxx; architecture bhv of xxx is begin process (A,B) begin C