july, 2001cms tracker electronics1 i 2 c investigations - some reported problems from some apv users...

July, 2001 CMS Tracker Electronics 1

I2C investigations

- some reported problems from some APV users - sensitivity to “termination” resistance and power supply levels

- I2C scheme very simple, ought to be problem free - so what’s going on?

Outline

probable cause of problemsmeasurements on I2C transactions on CCUM/hybridmeasurements of APV I2C drive strengthpossible solutions

Mark [email protected]

content here summarises e-mail exchanges between:S.Marchioro, R.Hammarstron, V.Commichau, J.Mnich, J-D.Berst, U.Goerlach, G.Hall, M.French, C.Ljuslin, C.Paillard, W.Karpinski.

I2C websitehttp://www.semiconductors.philips.com/i2c/


I2C electrical scheme

APV(slave)

R

I2C line(SDA)

DRIVER(master,

e.g. CCU)

out

inPull-upresistor

C(parasitic)

out

DRIVER 0.25 m CCU directly in CMS. VI2C in lab. CCU module for hybrid presently.

LEVEL SHIFTER Not needed in CMS. Incorporated in CCUM. Various solutions possible.

I2C line RC should be small cf I2C clock period (s). C will be layout dependent.

APV (MUXPLL) hysteresis characteristic gives noise immunity input has to be pulled below lower threshold for APV to correctly recognise data

What’s going wrong?

Suspect problem arises due to output drive capability of level shifter stagescombined with small values of pull-up resistor R.

in5V 2.5V

LEVELSHIFTER

hysteresis


Level shifter circuitsOpto-isolated level shifter (simplified schematic) used in APV test setup in IC lab

DRIVERSDA

APVSDA

isolationbarrier5V side 2.5V side

*

*

*Diodes used to implement bi-directionality use low forward drop devices (Schottky) but still ~ 0.25V or more if Rpullup small

If SDA not pulled low enough to trip APV I/P hysteresis threshold then APVwill fail to recognise its own address and I2C transaction will fail

Rpullup

Rpullup

CCU module/hybrid system

Level shifting is implemented using MOSFET on CCU moduleCopes better with low values of Rpullup, but ON resistance still exists

5V 2.5V

SDACCU side

SDAAPV side


I2C measurements on the IC APV test setup

APVacknowledgesown address

APV fails todecode own

address and sodoesn’t generate

acknowledge

I2C transaction fails on this setup if SDA line not pulled lower than ~ 0.35 Volts

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

SCK, pull-up = 10k

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts SDA, pull-up = 10k

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

SDA, pull-up = 1.5k

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

10 usec/division

SDA, pull-up = 1.3k

APV address 0100001

0 indicateswrite cycle

0.25V

0.35V

>0.35V


Measurements on the CCU module/hybrid setup

APVacknowledgesown address

APV fails todecode own

address and sodoesn’t generate

acknowledge

I2C transaction fails at pull-down voltage > ~ 0.35V corresponding to pull-up resistance of

375 = 1.5k // 5001.5k is built in resistance on CCU module)

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

SCK, pull-up = 1.5k

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts SDA, pull-up = 1.5k

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

SDA, pull-up = 500

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

10 usec/division

SDA, pull-up = 375

0.25V

0.35V

>0.35V

APV address 0100001

‘0’ indicateswrite cycle


APV25 I2C drive strengthHow low can APV pull SDA line for a given pull-up resistor value?

Use strong driver circuit (so that APV can always respond to I2C transaction) and use different values of Rpullup, measuring how low APV can pull SDA during Acknowledge cycle.

700

600

500

400

300

200

100

0

Vd

iff [

mV

]

1002 3 4 5 6 7 8 9

10002 3 4 5

SDA pull-up resistor value []

2.50

2.00

1.50

1.00

0.50

0.00

Vol

ts

10 usec/division

Vdiff

APVACK

bitwritebit

e.g. for Rpullup = 500 APV can pull SDA line down to within 200mV of VSS (0V)

addressbit


CCUM FEH

OH

? ?

?

Pull-up resistor/s (where and what value?)

Seems as though ought to be trivial, but of course isn’t quite In final system 0.25um CCU master talks directly to 0.25um APV/MUXPLL/LD slaves no level shifting required => problems go away

Interim situation present CCUM, test systems incorporate level shifting stages will want to test hybrids (FEH,OH) in isolation, and together, on different test bedse.g. assume worst case cable capacitance ~100pF (reasonable?) for RC < 1s (CR < 5, =5sec) => R ~ 10k

Could split 10k between FEH and OH (20k on each)

May need different variants depending on location in detector

C~cable capacitanceR=pull-up resistor

SCK

SDA

5 s


CCUM FEH

OHPut pull-up here only

(~few k)

Pull-up resistor (where and what value?)

Alternatively

Shouldn’t confuse pull-up with termination

Present choice of resistor on CCUM (1.5k) will probably work in all cases

Components on FEH and OH can be finalised now

Suggestion only – others will want to comment

Leave these resistors out altogether(or make large)


Conclusions

I2C problems experienced probably due to level shifter circuitscoupled with low values of pull-up resistor

Should be no problems in all 0.25m final system

Suggested solution

put large pull-up resistor values on FEH and OH (~20k say) (will, in any case, be dominated by 1.5k on present CCUM)

if necessary (large bus capacitance) put smaller value on CCUM


Other matters

APV25s1 biasing

- manual needs update, I2C values correct for APV25s0, not s1

Recommended bias settings. Because of current mirroring change between s0 and s1 versions the numbers in the manual must change (approx 70% of s0 values).

External bias at 128 A, power supplies = 0, 1.25V, 2.5V

IPRE 85IPCASC 45IPSF 30ISHA ~30 (tune for optimum pulse rise time)ISSF 30IPSP 48IMUXIN 30VFP ~30 (preamp fall time - can be higher but depends on occupancy)VFS ~60 (tune for optimum pulse fall time)

Pulse shape tuning (rough guide): As detector capacitance increases ISHA needs to increase VFS needs to be reduced For capacitances in the range 0 -> 20 pF:

ISHA in range 20 -> 65, VFS in range 65 -> 50


APV25s1 biasing

Internal biasing dependence on value of on-chip resistor testing so far => 15 % increase of all I2C current settings (w.r.t. external (128A) values)

i.e. external (128A) internal

IPRE 85 98IPCASC 45 52IPSF 30 34ISHA ~30 ~34ISSF 30 34IPSP 48 55IMUXIN 30 34

=> values in “internal” column should be used for the hybrid (for now)

Need to find a strategy for choosing I2C bias current settings

Internal Iref will depend on local power supply values, and on internal resistor value (+/-10%)

Can probably be managed by correction factor applied to all values (as above) to achieve “correct” power consumption

Something to look at in system test?


APV25s1 biasing

ICAL I2C register setting determines magnitude of calibration step applied to capacitors feeding preamp inputs

actual value of charge injected will depend on: reference current value (external/internal(on-chip resistor value)) I/V resistor value in bias generator very small charge injection capacitors

can be used to calibrate (tune) pulse shape, but not for accurate gain measurement

rough value to get 1 mip signal

APV25s0 APV25s1 APV25s1external, 128A external, 128A internal

~ 40 ~ 25 ~ 29


APV performance dependence on LV power supplies

Currently under study, no show-stopping discoveries, but some aspects of performanceaffected (mainly dynamic range identified so far)

Pictures show peak mode pulseshapes for signals from -2 to +6 mips in 0.5 mip steps

gain change minimal butloss of headroom in –10% case

assumptions so far:

2.7 V not exceeded

power differences symmetricalon both rails

I2C current settings tuned toget same analogue current fordifferent PSU voltages

400

300

200

100

0

-100

nominal(0, 1.25V, 2.5V)

400

300

200

100

0

-100

AD

C u

nits

+8% (0, 1.35V, 2.7V)

400

300

200

100

0

-100

200150100500time [nsec]

-10% (0, 1.125V, 2.25V)


APV performance dependence on LV power supplies

500

400

300

200

100

0

AD

C u

nits

6543210-1-2signal [Mips]

- 10% (0, 1.125V, 2.25V)

nominal (0,1.25V, 2.5V)

+8% (0, 1.35V, 2.7V)

july, 2001cms tracker electronics1 i 2 c investigations - some reported problems from some apv users...

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