VOL. E99-B NO. 1JANUARY 2016

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PAPER

Phase and Gain Imbalance Compensation in Low-IF Receivers

Teruji IDE†,††a), Takeo FUJII††, Mamiko INAMORI†††, Members, and Yukitoshi SANADA††††, Senior Member

SUMMARY In this paper, we present a modified image rejectionmethod that uses imbalance compensation techniques for phase and gainin low-intermediate frequency (IF) software-defined radio (SDR) receivers.In low-IF receivers, the image frequency signal interferes with the desiredsignal owing to the phase and gain imbalances caused by analog devices.Thus, it is difficult to achieve the required image rejection ratio (IRR) ofover 60 dB without compensation. To solve this problem, we present modi-fied blind compensation techniques based on digital signal processing usinga feedback control loop with a practical computation process. The modi-fied method can reduce the complexity when a hardware logic circuit isused, like an FPGA. The simulation and experimental results verify thatthe modified method achieves an IRR greater than 50–60 dB for both thecarrier and the modulated waves.key words: low-IF receiver, SDR, image rejection, phase and gain imbal-ance

1. Introduction

A recent approach to increasing the number of highly flexi-ble and adaptable systems is termed software-defined radio(SDR). One of the key functions of an SDR is its multibandand multimode operation. An ideal multiband and mul-timode receiver consists of an analog-to-digital converter(ADC) placed immediately after the antenna to directly digi-tize the radio frequency (RF) signal. However, this approachis not practical because it requires high-resolution and high-sampling ADCs with a high clock frequency and high per-formance digital signal processors. Therefore, more real-istic SDR receiver architectures, such as the direct conver-sion (zero-IF) [1] and low-IF [2]–[15] receivers, have beenproposed. The zero-IF or low-IF principle reduces the com-plexity of the receiver architecture. In the zero-IF and low-IF receiver architectures, the RF signal is downconverted toin-phase (I) and quadrature (Q) signals and digitized withlow clock frequency ADCs. Typically, receivers work withIFs, and a majority of them still require discrete compo-nents. Low-IF receivers combine the advantages of both theIF and zero-IF receivers. In the low-IF receiver architecture,

Manuscript received May 17, 2015.Manuscript revised August 21, 2015.†The author is with the National Institute of Technology,

Kagoshima College, Kirishima-shi, 899-5193 Japan.††The authors are with The University of Electro-Communica-

tions, Chofu-shi, 182-8585 Japan.†††The author is with Tokai University, Hiratsuka-shi, 259-1292

Japan.††††The author is with Keio University, Yokohama-shi, 223-8522

Japan.a) E-mail: t-ide@kagoshima-ct.ac.jp

DOI: 10.1587/transcom.2015EBP3209

the RF signal is downconverted to a low-IF frequency closeto direct current (DC), and the low-IF signal is then digi-tized and digitally demodulated to extract baseband I andQ signals. The main problem with the zero-IF receiver isDC offset and 1/f noise. DC offset occurs when a local sig-nal leaks to the input of a low-noise amplifier (LNA) andan antenna. Therefore, the reflected signal is mixed withthe original local signal. This is called self-mixing. Addi-tionally, 1/f indicates that the noise power is proportional to1/f. This has a direct effect on the zero-IF receiver becausemost of the signal components are concentrated on the zerofrequency.

The low-IF principle does not suffer from this prob-lem because it uses complex signal processing for image re-jection. The RF filter method cannot be used in widebandwireless systems using carrier frequencies on the order ofgigahertz, where the image frequency is in the same fre-quency band as that of the system. After the frequency isconverted to low-IF, an analog image rejection filter [5] pro-vides the insufficient image rejection ratio (IRR) of 43 dB.In actual communication systems such as cellular phones,IRRs of 50–60 dB or more are required. The image rejec-tion performance is limited by analog devices such as mixersand π/2 phase-shift circuits, which have their own phase andgain imbalances. Previous studies [6]–[14] have proposedimage rejection methods in low-IF receivers. The IRR per-formance of detection and compensation methods for phaseand gain imbalance using digital processing ranges from 50–60 dB. [6] and [7] present a phase and gain compensationprocess in the digital domain using a test signal applied tothe analog circuit. However, this process requires a longcalibration time, an additional switch, and a test signal in-put port to the mixers. Furthermore, in [7], the IRR is only42 dB because of ambient temperature fluctuation; there-fore, the required IRR mentioned above cannot be achieved.To solve this problem, [8] proposes an improved method inwhich the test signal is required to be continually mixed withthe image signal. However, many test signals are requiredwithin the target bandwidth. Further, for the method withoutusing the test signal, [9] and [10] utilize feedforward pro-cessing to achieve blind detection and compensation. How-ever, practical compensation processes were not discussedin these studies. Moreover, feedforward processing cannottreat a time-varying signal.

To solve these problems, blind compensation methodsfor phase and gain imbalances using a feedback control loophave been discussed in [11]–[14]. However, these methods

Copyright c© 2016 The Institute of Electronics, Information and Communication Engineers

212IEICE TRANS. COMMUN., VOL.E99–B, NO.1 JANUARY 2016

have a large computational cost, or they cannot be imple-mented for practical applications. In this paper, we presenta modified blind compensation method by using a feedbackcontrol loop with small computational complexity and prac-tical implementation. In [14], in order to reduce computa-tional complexity, instead of the division operation, a mul-tiplication operation was introduced; however, implemen-tation issues were not resolved. In [12], an IRR of 60 dBis achieved by applying the least mean square (LMS) al-gorithm. When compared with the four multipliers used in[12], in the modified method, only three multipliers are usedto reduce computational complexity for the same IRR per-formance, as presented in Sects. 4 and 5. Moreover, [11] and[13] use a leaky integrator and the LMS algorithm; however,the detailed IRR performance is not discussed in these re-searches. Additionally, in these approaches, implementationcomplexities have to be reduced. Therefore, to overcome theabovementioned drawbacks, the modified method utilizes afeedback control loop based on digital signal processing forblind detection and compensation of both phase and gainimbalances with only the input signal. In Sects. 3.1 and 3.2,we will theoretically present the modified method. Further,in Sect. 3.3, a comparison between the abovementioned con-ventional methods and the modified method is presented.We show that this method simplifies digital signal process-ing and makes it easier to implement in the low-IF receiver.Furthermore, to verify the validity of the modified method,various simulation and experimental results are presented.

The rest of the paper is organized as follows. In Sect. 2,we analyze the image rejection property of a conventionallow-IF receiver. In Sect. 3, we introduce the modified an-alytical phase and gain compensation methods. In Sect. 4,we present the simulation results for the modified method.In Sect. 5, experimental results are presented. Finally, con-clusions are drawn in Sect. 6.

2. Design Issues for Image Rejection Techniques

2.1 Image Rejection as a Function of Gain and Phase Im-balance

The primary issue in a low-IF receiver is imperfect imagerejection resulting from gain and phase imbalance. Figure 1shows a conventional low-IF receiver with a complex signalprocessing front-end and phase and gain imbalance compen-sation employing the low-IF principle [2]. This architectureis the same as that of the zero-IF receiver. Most of the cur-rent low-IF receivers have a complex mixer with a numeri-cally controlled oscillator (NCO) in a digital signal process-ing domain. This complex mixer downconverts the signalsonly on a positive or negative frequency. When a desiredsignal is located on a positive frequency and an undesiredsignal is located on a negative frequency, these two frequen-cies are referred to as mirror frequencies. When there areno phase and gain imbalances in the complex mixer, the de-sired signal is downconverted with the positive frequencycomponent, and the mirror signal is downconverted with the

Fig. 1 Conventional low-IF receiver with phase and gain imbalance com-pensation.

negative frequency component. Therefore, crosstalk will oc-cur in the positive and negative frequencies because of theimbalance.

Here, we suppose that the RF input signals have boththe desired (ωD) and undesired (ωU) angular frequencycomponents. Further, it is also assumed that

ωD − ωL = ωL − ωU = Δω,

where ωL is the local oscillator (LO) angular frequency(ωL = 2π fL, ωD = 2π fD, ωU = 2π fU).

A1 and A2 are the in-phase gain (shown as MIXi andLPFi in Fig. 1) and the quadrature gain (shown as Mixq andLPFq in Fig. 1), respectively. Moreover, g (= A2/A1) andΔφ are the gain imbalance ratio and phase difference, re-spectively. Hence, the output signal of MIXi (mixer for in-phase), with an undesired input, is as follows:

cos (ωUt + θ) cos (ωLt) .

The output signal of MIXq (mixer for quadrature), with anundesired input, is as follows:

cos (ωUt + θ)[−g sin (ωLt + Δφ)

].

The sum of the frequency components is filtered by eachlow-pass filter (LPF). Consequently, the output signal ofeach LPF is converted into a complex signal as shown be-low:

y(t) = cos (ωUt + θ)[cos (ωLt) − jg sin (ωLt + Δφ)

]

= (1/4)[exp { j (ωL − ωU) t − θ}] · [1 − g exp { jΔφ}]

+ (1/4)[exp { j (ωL−ωD) t+θ}] · [1+g exp {− jΔφ}] .

(1)

Here, cos (ωUt + θ) is an undesired input signal from the an-tenna.

The first term of Eq. (1) indicates that the signal inthe image frequency interferes with the desired signal aftercomplex mixing by the analog-type mixer. The second termof Eq. (1) indicates that the signal in the image frequencycan be eliminated with the complex digital signal process-ing and the LPF. From Eq. (1), the IRR in power is givenby

IRR =

∣∣∣∣∣1 − g exp{jΔφ}

2

∣∣∣∣∣2

∣∣∣∣∣1 + g exp{−jΔφ}

2

∣∣∣∣∣2

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS213

=1 + g2 − 2g cos{Δφ}1 + g2 + 2g cos{Δφ} . (2)

In the abovementioned equations, an amplitude error of 1%leads to an IRR of 46 dB, and a phase error of 1◦ results ina 41 dB IRR. Equation (2) assumes that the phase and gainimbalances are independent of each other. Considering aphase imbalance ratio of g = 1, the IRR can be given by thefollowing equation:

IRR∣∣∣g=1 � Δφ2/4. (3)

Similarly, for a phase imbalance of Δφ = 0 and a gain im-balance of g =

(G + Δg

)/G, the IRR is calculated as

IRR∣∣∣Δφ=0 �

(Δg/G

) 2/4. (4)

Thus, the IRR can be given by the following equation:

IRR � Δφ2/4 +(Δg/G

) 2/4. (5)

2.2 Image Rejection Using a Complex Mixer

Figure 2 shows that the spectrum of the signal in the imagefrequency of the LO (LO frequency minus Δ f ) causes inter-ference to the desired signal (LO frequency plus Δ f ), whenthere is no compensation for phase and gain imbalances.When the analog devices have no imbalance, the desired andundesired signals are downconverted to the baseband signalhaving a frequency spacing of 2Δ f . In the abovementionedcase, because the undesired signal is eliminated by the LPF,there is no interference to the desired signal. On the otherhand, with the imbalance of typical analog devices, the de-sired signal interferes with the undesired signal.

The required IRR is more than 60 dB in wireless com-munication systems such as cellular phones. Thus, for ex-ample, the amplitude error should be within 0.01 dB and thephase error should be less than 0.05◦. In a typical case, thephase and gain imbalances of the phase shift circuit and the

Fig. 2 Image-band interference in low-IF receiver.

mixer range from 1◦ to 3◦ and 0.5 to 1 dB, respectively, mak-ing it impractical to achieve an IRR of 60 dB. Therefore, tosolve this problem, a compensation technique is required.

3. Modified Gain and Phase Imbalance CompensationMethods

Figure 3 shows the detailed block diagram of the conven-tional gain and phase imbalance compensation method inthe low-IF receiver. As can be seen, the phase and gain com-pensation processing units are serially cascaded. In the sub-sequent subsections, for reducing computational complexityfrom a practical viewpoint, we present the modified methodfor phase and gain compensation in the low-IF receiver.

3.1 Analysis of Phase Compensation

Figure 4 shows the modified phase imbalance compensationmethod shown in the block diagram of the low-IF receiver.

From Eq. (1), the real part, yr(t), and the imaginarypart, yi(t), of the input signal before compensation are givenby

yin (t) = yr (t) + j · yi (t)

= (1/2) {cos (α)} − j (1/2) sin {α + Δφ} (6)

= (1/2) {cos (α)} − j (1/2) {sin (Δφ) cos (α)

+ cos (Δφ) sin (α)} (7)

≈ (1/2) {cos (α)}

Fig. 3 Low-IF receiver with detailed phase and gain imbalance compen-sation method.

Fig. 4 Block diagram of modified phase imbalance compensationmethod.

214IEICE TRANS. COMMUN., VOL.E99–B, NO.1 JANUARY 2016

− j (1/2) {sin (Δφ) cos (α) + sin (α)} , (8)

where (ωL − ωU)t − θ = α and cosΔφ ≈ 1. Moreover, thegain imbalance (g) in Eq. (1) is set to 1. Further, we assumethat the amplitude of each signal is normalized as shownin Eq. (1). The in-phase signal, yr (t), is multiplied by thequadrature signal, yi (t), to calculate the following equation:

ypd (t) = (1/4) cos {(ωL − ωU) t − θ}· sin {(ωL − ωU) t − θ + Δφ}

= (1/8) sin (Δφ)

≈ (1/8) (Δφ) , (9)

where sin (Δφ) ≈ Δφ.The input of the phase compensation section is ex-

pressed in Eqs. (8) and (9). We assume that the gain im-balance ratio (g) varies slowly. As can be seen in Fig. 4,the multiplied signal is fed into the LPF through which the(ωL − ωU) component is eliminated. The LPF output signalis then fed into the integrator, which is a perfect integrator(1/S), with the loop constant (Gp) as a reciprocal of the timeconstant (τp = 1/Gp) in the loop. Thereafter, the output ofthe integrator is multiplied by the loop constant (Gp). Next,the output of the abovementioned multiplier is multipliedby the in-phase input signal. This multiplied signal is sub-tracted from the quadrature input signal. The output of thephase compensation section, yout (t), produces the followingequations:

yout(t) = {I} − j{Q′ − I sin (Δφ)

}

= {I} − j {I sin (Δφ) − I sin (Δφ) + Q}= {I} − j {Q} , (10)

where I is the in-phase input signal, cos(α), in Eqs. (6)–(8).Further, Q is the quadrature input signal, sin(α), in Eqs. (6)–(8). Finally, phase imbalance compensation is performedfrom Eq. (10).

3.2 Analysis of Gain Compensation

Figure 5 shows the modified gain imbalance compensationmethod shown in the block diagram of the low-IF receiver.

We assume that the phase difference due to imbalance(Δφ) varies slowly. In Fig. 5, the loop constant (Gg) is thereciprocal of the time constant (τg = 1/Gg) in the loop, and1/S denotes a perfect integrator. From Eq. (1), the real partof the input, yr(t), and the imaginary part, yi(t), of the inputsignal before compensation are given by

yr (t) = (1/2) cos {(ωL − ωU) t + θ} (11)

yi (t) = (1/2)[(g) sin {(ωL − ωU) t + Δφ − θ}] . (12)

Following the squaring operation, we obtain the real part,zr (t), and the imaginary part, zi (t), as follows:

zr (t) = (1/8) (1 + cos {2 [(ωL − ωU) t + θ]}) , (13)

zi (t) = (g)2 (1/8)

· (1 − cos{2[(ωL − ωU) t + Δφ − θ]}) . (14)

Fig. 5 Block diagram of modified gain imbalance compensation method.

Let the gain imbalance ratio (g) be replaced with (1 + ΔA).Here, 1 implies that the amplitudes of both the signals arenormalized. Further, we assume that 1 > ΔA, and (ΔA)2 isnegligible. In Eqs. (13) and (14), the double frequency termbecomes zero because of the LPF. By using Eqs. (13) and(14), the result of zr (t) minus zi (t) is (1/8)

(1 − (g)2

)as the

input of the LPF. The approximate part of the abovemen-tioned result for ygd is (1/8)

(2ΔA + (ΔA)2

)� (1/8) (2ΔA)

by leaving out the term (1/8) (ΔA)2; therefore, the output ofthe LPF is given by the following equation:

ygd ≈ ΔA/4. (15)

The residual error results from the term (1/8) (ΔA)2. Theinfluence of this error is discussed in Sects. 4.1 and 4.2.

From Eq. (1), the input of the compensation block inthe loop, yin (t), is given by the following equation:

yin (t)= (1/2) {cos (α)}− j (1/2) (1+ΔA) {sin (α)} .(16)

Using Eq. (15) and the imaginary part of Eq. (16) multipliedby (1 − ΔA), the output of the compensation block in theloop, yout (t), is given as

yout (t) = (1/2) {cos (α)}− j (1/2) (1 + ΔA) (1 − ΔA) {sin (α)}

≈ (1/2) {cos (α)} − j (1/2) {sin (α)} . (17)

In Eq. (17), the gain compensation is carried out bymultiplying (1+ΔA) by (1−ΔA). Instead of a division pro-cess, the multiplication process is used in the above equa-tion. The abovementioned methods can be applied to boththe undesired and desired input signals to compensate forthe phase and gain imbalances. We assume that the above-mentioned compensation methods can be applied to the re-ceiver with an automatic gain control (AGC) operation.

3.3 Comparison of Modified and Conventional Compen-sation Methods

Initially, we will focus on the practical method for gain com-pensation. In [11] and [13], by using a leaky integrator and

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS215

the LMS algorithm, the division process is used for the com-pensation. In general, the computational complexity of thedivision operation is greater than that of the multiplicationoperation (multiplier). In [14], to avoid the division pro-cess, equations for the multiplication operation were pre-sented without a practical implementation method. The gaincompensation of the modified method is achieved by multi-plying (1 + ΔA) by (1 − ΔA) in Eq. (17). This method ispractical and different from the method proposed in [14]. Inthe abovementioned multiplying process using a field pro-grammable gate array (FPGA) for the 16-bit fixed-point pro-cess, we estimate that the number of gates is 5696. On theother hand, in the case of the conventional method [11] us-ing the division process, the estimated number of gates is21184, which is more than three times larger than that of themodified method. In the case of another method for avoidingthe division process, by using memory for multiplying Gg, alookup table method is used. In this method, extra memoryblocks are needed. For a 16-bit fixed-point process, it needs1048576 (= 216 · 16) bits at minimum. It is a large burdenfor the FPGA as a logic circuit.

An advantage of the modified method is that the ap-proximations in Eqs. (8) and (17) can be performed in thefeedback control loop because the error for the approximateprocess is exponentially reduced in the loop. Moreover, thecomputational complexity of the modified method is lessthan or equal to that in [12]. In Fig. 6 of [12], the LMScomplex image rejection algorithm contains four multipli-ers. The modified method, shown in Fig. 4, can achieve thesame function with two multipliers. In this case, the multi-plier for the loop constant (2−m, m: positive integer) can bereplaced with a bit shift operation, and LPF has no multiplierbecause it uses addition and bit shift operations. When weapply the gain compensation shown in Fig. 5, both squar-ing operations can be replaced with an absolute operation.Further, one multiplier can be used instead of the other mul-tipliers in Fig. 5, as accomplished in Fig. 4. As a result, inthe modified method, a total of three multipliers are used asagainst four multipliers used in [12].

In consideration of the above assumptions, by using theFPGA with the 16-bit fixed-point process, we estimate thenumber of gates as shown below. For the number of esti-mated gates in Fig. 4, the two multipliers and “the three ad-ditions and bit shift operations” use 11392 and 11520 gates,respectively. Other than the gates mentioned in Fig. 4, theaddition and delay operations use 566 gates. The total esti-mated number of gates is 23478 in Fig. 4. Next, in the samemanner as shown in Fig. 4, we estimate the number of gatesin Fig. 5. One multiplier and “the three addition and bit shiftoperations” use 5696 and 11520 gates, respectively. Otherthan the gates shown in Fig. 5, the addition and delay oper-ations use 976 gates. The total estimated number of gates is18192 in Fig. 5, and the sum total of the estimated numberof gates is 41670 in Figs. 4 and 5. In the abovementionedfour multipliers for loop constant and LPF in both phaseand gain compensations, the estimation of the reduced com-plexities are 1856 gates in each multiplier (replaced with

Table 1 Estimated and reduced gates for the modified method.

Fig. 6 Simulation block diagram for (a) phase compensation and (b) gaincompensation.

addition and bit shift operation); therefore, 7424 gates arereduced in total. For the division operation and the abovefour multipliers, the estimation of the total amount of thereduced gates are 22912, including the 15488 reduced gatesfor the division process. Owing to the reduced gates, thesum total of the estimated number of gates is 41670. Thus,the modified method can practically achieve remarkable re-duction of complexity. The total number of estimated andreduced gates is summarized in Table 1.

4. Simulation Results

The performance of the modified method is evaluated withnumerical results obtained through computer simulation. Inthe simulation for the desired and the undesired input sig-nal, the convergence performance of the compensation, theimage rejection performance, and the bit error rate (BER)performance of demodulation are evaluated.

4.1 Basic Characteristics of Phase and Gain Compensa-tion

For the simulation of the phase and gain compensation, weused the modified algorithms presented in Figs. 4 and 5, re-spectively. Figure 6 shows the simulation block diagram forphase and gain compensation.

Figures 7(a) and 7(b) show the simulation results of thephase and gain compensation responses, with detected phaseimbalance. The parameters and block diagrams used for thesimulation are shown in Table 2 and Figs. 6(a) and 6(b), re-spectively. In this simulation, the basic characteristics ofphase and gain compensation are evaluated from Eqs. (10)and (17). The 16-bit fixed-point process is employed for

216IEICE TRANS. COMMUN., VOL.E99–B, NO.1 JANUARY 2016

Fig. 7 Performance of (a) phase and (b) gain compensation methods. (c)Phase and (d) gain compensation performance with approximate and exactvalues.

Table 2 Simulation parameters.

the compensation algorithm, and the initial maximum phaseand gain imbalances are assumed to be 10◦ and 6 dB, re-spectively. When Eqs. (8) and (9) (for phase compensation)and Eqs. (15) and (17) (for gain compensation) are approx-imated, the simulation results show that the feedback looplocks and converges to the initial values of the imbalance.The computational complexity can be reduced by using theabovementioned methods (particularly for the division pro-cess in gain compensation). The simulation results of thecorrection values for the approximate and the exact compu-tations are shown in Figs. 7(c) and 7(d), respectively. Thesimulation parameters are the same as those in Table 2.

In the abovementioned simulation, the approximationsare applied. In Eq. (8), for phase compensation, the approx-imation of cos(x) reduces the complexity for multiplication.The gain compensation is carried out by the multiplication(approximate) process instead of the division process. Themodified method has two multiplication processes and re-moves the division process in Eqs. (15) and (17) includ-ing a residual error as follows. For the gain compensation,the approximation of multiplication reduces the complex-ity caused by the division. In Eq. (15), we assume 2 > ΔA(from 2ΔA+(ΔA)2), and (ΔA)2 is negligible. Additionally, inEq. (17), because the other term (ΔA)2 is negligible, assum-ing that the coefficient of 1/2 is omitted, the approximateequation is given by (1 + ΔA) (1 − ΔA) = 1 − (ΔA)2 ≈ 1.In the above equation, we assume 1 > ΔA, and (ΔA)2 isnegligible again. Here, 1 indicates a normalized gain fac-tor; therefore, the compensation can be performed. How-ever, the residual error increases because (ΔA)2 is neglectedtwice, for approximations in Eqs. (15) and (17), as shownin Fig. 10(b) of Sect. 4.2. Particularly in gain compensation,the multiplication process, instead of the division process,is very useful from the viewpoint of the number of requiredcomputations. If we compare the approximate process withthe exact process by setting the same time constant, the con-vergence time for the approximated case is smaller than thatfor exact computation as shown in Fig. 7(d) of Sect. 4.1 be-cause of the abovementioned residual errors in Eqs. (15) and(17). The reason is that, in general, convergence time is in-versely proportional to error variance in a control loop.

Owing to the difference between the exact and approx-imate computations caused by the residual errors in the ap-proximate computation, the loop is slightly different from

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS217

Fig. 8 Responses of (a) phase and (b) gain compensation for differentamplitudes of input signal and number of bits.

the first-order loop. In Eqs. (15) and (17), strictly speaking,because (1 + ΔA) (1 − ΔA) involves the second-order termof (ΔA)2, it has a slightly different behavior as a second-order loop.

On the other hand, we presume that the gain error vari-ance will be worse than that of the exact computation. Withrespect to the abovementioned gain error variance, the eval-uation result is shown in Fig. 10(b).

Figure 8 shows the simulation results of phase and gaincompensation responses for different amplitudes of the in-put signal and different amounts of bits in the fixed-pointprocess. The block diagram used for simulation is the sameas that in Fig. 7, and the parameters are listed in Table 3.

Figure 8(a) shows the numerical results of phase com-pensation responses for different input signal amplitudes(0 dB, −10 dB, −20 dB, and −26 dB) and different numbersof fixed-point process bits (16 bits, 14 bits, and 12 bits). Fig-ure 8(b) shows the results of gain compensation responsesfor different input signal amplitudes and different amountsof bits in the fixed-point process. In this simulation, whenthe amplitude is 0 dB, the amplitude of the input signal isappropriate for fixed-point processing with 16 bits.

As can be seen in Fig. 8(a), the input signal amplitude

Table 3 Simulation parameters.

Fig. 9 Relationship between normalized bandwidth and variance.

has a large impact on the phase compensation performancewhen the number of bits in the fixed-point process is lim-ited. From Fig. 8(b), we can see that the gain compensationperformance is less sensitive to the value of the input signalamplitude.

Note that, in the abovementioned simulation, these pa-rameters have a greater impact on the phase imbalance thanthat on the gain imbalance. As can be seen from Eq. (5),the influence on phase imbalance is directly related to thefirst term, Δφ2. In the case of gain imbalance, it is related tothe second term, (Δg/G)2. Because Δg is divided by G, theeffect on the gain imbalance is small.

Figure 9 shows the relationship between the varianceand the normalized bandwidth. The parameters and blockdiagram used for the simulation are shown in Table 2 (inwhich the initial phase and gain imbalances are 10◦ and1 dB, respectively) and Figs. 6(a) and 6(b), respectively. Inthis simulation, the time constant parameter in the loop isvaried from 16384 to 1048576 samples. As described inthe following subsection, an IRR of approximately 60 dBcan be achieved by setting the parameter to 1048576 sam-ples. In this simulation, “normalized bandwidth” meansthe bandwidth of the desired and undesired input signalsthat is normalized when the sampling frequency is set to1. Further, “the number of oversamples” means the num-ber of oversamples of a root-Nyquist filter when the band-width of the desired and undesired input signals is limitedin the above simulation. Moreover, “the desired and unde-

218IEICE TRANS. COMMUN., VOL.E99–B, NO.1 JANUARY 2016

sired signal bandwidth” means the bandwidth of the desiredand undesired signals with the bandwidth limitation that isfed into the modified compensation block (the control loop)as well. From Fig. 9, we can see that the variances of thephase and gain errors are inversely proportional to the nor-malized bandwidth of the desired and undesired signals byusing a root-Nyquist filter. In this simulation, the samplingfrequency is set to 1 for normalization; therefore, the num-ber of oversamples is inversely proportional to the normal-ized bandwidth of the desired and undesired signals. Thebandwidth of the signals is limited by using a root-Nyquistfilter. Thus, the normalized bandwidth of the desired andundesired input signals is a ratio of the sample frequency.The number of oversamples is 4, 8, 16, 32, 64, and 128;therefore, the normalized bandwidth is 1/4, 1/8, 1/16, 1/32,1/64, and 1/128, respectively.

Additionally, the time constant in the loop and the vari-ances of the phase and gain errors are inversely proportionalto each other. In other words, the variances of the compensa-tion errors are inversely proportional to the bandwidth of thedesired and undesired input signals with the bandwidth lim-itation that is fed into the control loop. Further, “the band-width of the (control) loop” is the bandwidth of the modi-fied compensation block in Figs. 4 and 5 that is composedof a control loop; the variances of the compensation errorsare proportional to the bandwidth of the loop. This impliesthat the bandwidth of the desired and undesired input signalsand the bandwidth of the loop are independent of each other.The modified compensation method can be performed in thecontrol loop.

4.2 Effect of Time Constant in the Loop

The error performance of the modified phase and gain com-pensation algorithms are evaluated from the viewpoint ofthe effect of the time constant in the loop. In the followingsimulations (Figs. 10 to 12), the time constant in the loop isvaried from 65536 to 1048576 and 2097152. Additionally,these results show that the effect of additive white Gaussiannoise (AWGN) can be almost neglected. For these simula-tions, we use Table 2 (the initial phase and gain imbalancesare 10◦ and 1 dB) and Figs. 6(a) and 6(b).

Figure 10 shows the variances of the phase (◦) and gain(dB) errors as a function of the carrier-to-noise ratio (C/N)varying from 0 dB to 60 dB. As can be seen in Fig. 10, thevariance approximately remains the same regardless of thevalues of C/N. From the results of Figs. 9 and 10, we cansee that the variances of the phase and gain errors are morestrongly affected by signal bandwidth than that by AWGN.As for the time constant of the loop, from Fig. 10, we cansee that the variances of the phase and gain errors decreaseexponentially with an increase in the time constant. More-over, there is no significant difference between the exact andapproximate computations. These results show that the be-havior of the phase and gain compensation processes is rep-resented in the first-order control loop. Therefore, the vari-ances of the errors depend on the time constant.

Fig. 10 (a) Phase and (b) gain errors vs. C/N for approximate/exact com-putations and different values of time constant.

However, in the case of the gain compensation, the per-formance of approximate computation is slightly inferior tothat of the exact computation for the variance, as shown inFig. 7(d). Because of the residual errors in Eqs. (15) and(17), in Fig. 10(b), we observe that, compared with the gainerror variance for the exact case, the approximate case hasa slightly large gain error variance. The difference is up to0.02–0.03 dB in the case that the time constant is 16384–65536 samples for the approximate computation. If we con-sider the results of Figs. 7(d) and 10(b) in the approximateprocess, it is clear that setting a small time constant valueresults in the large variance of gain error. The reason of theabovementioned assumption is that, in general, a time con-stant is inversely proportional to an error variance in a con-trol loop. The residual error of 0.02–0.03 dB in Fig. 10(b)results from neglecting (ΔA)2 twice, for approximation inEqs. (15) and (17)), as shown in Sect. 4.1. However, becausethe difference of the gain error (residual error) variance of0.02–0.03 dB is small, gain compensation can be practicallyperformed and implemented using a multiplication process.In particular, in Figs. 4 and 5, both compensation processesare the second-order control loop that includes the LPF and

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS219

Fig. 11 IRR vs. C/N for approximate/exact computations and differentvalues of time constant.

Fig. 12 Relationship between time constant and convergence time.

the integral (1/S ) process. In fact, the time constant in theintegral process is greater than that in the LPF. Therefore,the time constants τp (= 1/Gp) and τg (= 1/Gg) are domi-nant in the integral process as opposed to the LPF.

Consequently, Fig. 11 shows the time constant requiredto achieve an IRR of 60 dB from the results of Fig. 10 usingEq. (2). These results are subject to a time constant similarto Fig. 10. In this case, it is presumed that the phase andgain compensation are independently performed.

Figure 12 shows the relationship between the time con-stant and the convergence time. From the results shown inFig. 12, the time constant approximately corresponds to theconvergence time. Therefore, the behavior of the modifiedmethod can be regarded as a first-order control loop.

As can be seen from the results in Figs. 10 and 12, theproblem is that the relationship between the time constantand the imbalances of phase and gain is contradictory toeach other. To improve the converging time, the time con-stants for the phase and gain compensation responses shouldbe selected in a certain range such as the time constant inFigs. 10 and 12. From the above simulation, we can see thatwhen the mean value of the phase or gain error is large, theloop selects a small value of the time constant. Although theconvergence time is small in this case, because of a large er-ror variance, by setting a large value of time constant in theloop, the variance of error will be small after the loop locks

Fig. 13 IRR performance (output spectrum) (a) with and (b) withoutcompensation.

Fig. 14 Simulation block diagram for IRR (output spectrum).

and converges.

4.3 IRR Performance

By considering the abovementioned simulation results, weevaluate the IRR and BER performances of the modifiedphase and gain compensation algorithms.

Figure 13(a) shows the simulation result of the out-put spectrum of the modified phase and gain compensationblock in Fig. 3. An IRR of 60 dB or more is realized whencompared with Fig. 13(b). Figure 14 shows the block dia-gram of the abovementioned simulation with the phase andgain compensation processes in cascade.

The parameters of the simulation are listed in Table 2(the initial phase and gain imbalances are 10◦ and 1 dB), inwhich the number of oversamples of the desired and the un-desired signals are 16 and 8, respectively. In Fig. 14, the firststage is for phase compensation, and the second stage is forgain compensation. The simulation shown in Fig. 14 is dif-ferent from that in the previous section in terms of the phase

220IEICE TRANS. COMMUN., VOL.E99–B, NO.1 JANUARY 2016

Fig. 15 BER vs. CNR with and without compensation.

Fig. 16 Simulation block diagram for IRR (BER).

and gain compensation blocks in cascade. As can be seenfrom the results in Fig. 8, the influence of the phase imbal-ance is more significant than that of the gain imbalance. Theperformance of the abovementioned configuration is betterthan that of the others because the residual error of the phasecompensation process is converted to the gain error, whichwill be finally compensated by the gain compensation pro-cess.

Figure 15 shows the simulation results of the BER ver-sus C/N performance of the modified phase and gain com-pensation blocks in Fig. 3, with and without compensation.The block diagram and parameters used in the simulationare shown in Fig. 16 and Table 4, respectively. For the de-sired and undesired signals with equal power, 16 quadra-ture amplitude modulation (QAM) /64QAM and quadraturephase shift keying (QPSK) signals are randomly generated.The frequencies of the desired and undesired signals are LOfrequency plus 1/8 · f s and LO frequency minus 1/8 · f s,respectively. Moreover, oversampling is set to 16 times, andthe receive filter is assumed to be a root-raised cosine (α= 0.5). Additionally, 16-bit fixed-point processing is em-ployed, and the initial phase and gain imbalances are set tobe 10◦ and 1 dB (assuming the imbalance is due to mixer,phase shift circuit, amplifier, and LPF), respectively. Theresults show that the BER performance of the modified com-pensation method is better than that of the method withoutcompensation. In this simulation, the time constant in theloop is set to be 16384 to 262144 samples. The results show

Table 4 Simulation parameters.

that the BER performance is directly related to the time con-stant (similar to Fig. 11). When the time constant equals262144 samples, the overall characteristics asymptoticallyapproach those of the case without imbalance.

4.4 Discussions

The simulation results illustrated in Figs. 10–12 indicate thatthe degradation of the IRR performance caused by the ap-proximations is small. The IRR performance is depen-dent only on the time constant in the approximate and ex-act cases. Therefore, assuming that the behavior of phaseand gain compensation loop is first order, these errors de-crease exponentially with time constant. From Fig. 10, thevariance of the phase and gain imbalances shows that anIRR of 60 dB can be obtained. In this case, we assume thatthe phase and gain compensation processes are independentof each other. Therefore, in Fig. 11, from the individualphase and gain results of Fig. 10 using Eq. (2), the time con-stants required to achieve an IRR of 60 dB are 1048576 to2097152. From the result of Fig. 12, the modified methodcan be supposed as a first-order control loop. Therefore,the variances of phase and gain errors are dependent on thetime constant. From a comparison of the results of Figs. 11and 13, the abovementioned assumptions are validated. InFig. 13, the phase and gain compensation processes are se-rially cascaded to achieve 60 dB of IRR by setting the timeconstant to be 1048576. Both the results show that 60 dBof IRR can be achieved by setting the time constant from1048576 to 2097152. Therefore, it is considered certain that60 dB of IRR can be attained by setting the time constantfrom 1048576 to 2097152, as can be seen from Figs. 10 to12. In addition, we can see from the simulation results ofFigs. 10–12 that the IRR performance is not related to thenoise level of AWGN; however, it relies exclusively on theinput signal bandwidth.

The effect of the phase imbalance is greater than that ofthe gain imbalance, as can be seen in Eq. (5) and Fig. 8, be-cause the phase compensation block is the first stage. There-fore, we can assume that the performance of the IRR ofFigs. 13 and 15 is enhanced because the residual error ofthe phase compensation process is converted to gain error.

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS221

5. Experimental Results

Figure 17 shows the block diagram of the experiment, andthe experimental conditions are listed in Table 5. In this ex-periment, the theoretical and simulation analyses discussedin earlier sections are validated. Figure 17 shows the low-IF receiver that comprises the quadrature demodulator, LO,LPFs, ADCs, and digital signal processing block. Afterthe AD conversion, the modified method is applied to 16-bit fixed-point digital signal processing implemented in theFPGA. In the modified algorithm, the phase and gain com-pensation processing units are serially cascaded. This con-figuration is the same as that of Fig. 14. As can be seen inFig. 17, the unmodulated and modulated signal from the sig-nal generator is fed into the quadrature demodulator. In thisspecification, the phase and gain imbalances of the quadra-ture demodulator are varied from 1.5◦ to 4◦ and 0.15 to0.3 dB, respectively. Additionally, in Fig. 17, the imbalancesof the phase and gain should be considered as an analog-typeLPF.

In the case without compensation, the IRR is approx-imately 25 dB, as can be seen in Figs. 18(a) and 18(b).Figures 18(c) and 18(d) show that the modified methodsimprove the IRR to over 60 dB. Even in the case of themodulated signal (16QAM, root-Nyquist filter; α = 0.35,24.3 ksps), Figs. 18(e) and 18(f) show that more than 50 dBof IRR is realized. Figure 19 shows that the IRR varies withthe amplitudes of the input carrier and the modulated signal.

Fig. 17 Experimental block diagram.

Table 5 Experimental parameters.

For the same reason as shown in Fig. 8, the IRR degrada-tion is particularly sensitive to variations in the input sig-nal amplitude. With fixed-point processing, an IRR greaterthan 50–60 dB is obtained when the input signal amplituderanges from 5 to 10 dB. To solve the limited range problem,the use of AGC is practical for IRR.

Figure 19 shows that the results with the modulated sig-nal are inferior to those with the unmodulated signal. Forthe modulated signal, the results indicate that the imbal-ances in phase and gain depend on the variance. We cansee from the results of the signal modulated randomly withQPSK or 16QAM that it is related to the variance of the ran-domly modulated baseband signal. The modified methodsare verified experimentally with both the carrier and modu-lated waves.

Fig. 18 Image rejection performance of continuous wave (CW) andmodulated signals.

Fig. 19 IRR performance vs. input signal level.

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6. Conclusions

In this paper, we presented an image rejection method forthe low-IF architecture, using blind imbalance detection andcompensation in the control loop. In the control loop, ourapproximations reduce the complexity of digital signal pro-cessing.

The modified method that applies the approximationsachieves an IRR of more than 50–60 dB. In the modifiedmethod, the phase and gain compensation processing blocksare serially cascaded. The performance of this configurationis verified by simulation and experimental results for boththe carrier and modulated waves. For the modulated signal,the results show that the phase and gain imbalances dependon the variances and bandwidth of the input signal. More-over, the influence of fixed-point processing is seen whenvarying the input signal amplitude; a change of 5 to 10 dBresults in an IRR of 50–60 dB indicating that the use of AGCis practical for IRR.

Moreover, a sufficient improvement in the convergencetime in the loop can be achieved by selecting the time con-stant on the basis of the amount of the detected error in thefirst-order loop. We can easily apply the modified methodusing a digital signal processor such as an FPGA for im-age rejection in low-IF receivers. For avoiding the divisionoperation and reducing the number of multiplications, themodified method can achieve reduction in complexity forpractical operations by using the FPGA. Furthermore, themodified method is expected to be implemented in practicalsystems (modulation type, signal bandwidth, and samplingfrequency) to enhance their performance.

Acknowledgment

This work is supported by the National Institute of Technol-ogy, Kagoshima College.

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Teruji Ide received the B.E. degree inElectrical Engineering from Chiba University,Chiba, Japan in 1985 and the M.E. degreein Information Systems from the Universityof Electro-Communications, Tokyo, Japan in1994. He is a candidate for the Ph.D. degree atthe University of Electro-Communications. Hejoined Kokusai Electric Inc. (presently HitachiKokusai Electric Inc.) in 1985. He is currentlya Professor in the Department of Electrical andElectronics Engineering, National Institute of

Technology, Kagoshima College. His main research interests are in thefield of digital signal processing for radio communication equipment andsoftware defined radio. Mr. Ide is a member of IEEE.

IDE et al.: PHASE AND GAIN IMBALANCE COMPENSATION IN LOW-IF RECEIVERS223

Takeo Fujii was born in Tokyo, Japan, in1974. He received the B.E., M.E. and Ph.D. de-grees in electrical engineering from Keio Uni-versity, Yokohama, Japan, in 1997, 1999 and2002 respectively. From 2000 to 2002, he wasa research associate in the Department of Infor-mation and Computer Science, Keio University.From 2002 to 2006, he was an assistant profes-sor in the Department of Electrical and Elec-tronic Engineering, Tokyo University of Agri-culture and Technology. From 2006 to 2014, he

has been an associate professor in Advanced Wireless Communication Re-search Center, The University of Electro-Communications. Currently, heis a professor in Advanced Wireless and Communication Research Cen-ter, The University of Electro-Communications. His current research in-terests are in cognitive radio and ad-hoc wireless networks. He receivedBest Paper Award in IEEE VTC 1999-Fall, 2001 Active Research Award inRadio Communication Systems from IEICE technical committee of RCS,2001 Ericsson Young Scientist Award, Young Researcher’s Award from theIEICE in 2004, The Young Researcher Study Encouragement Award fromIEICE technical committee of AN in 2009, and Best Paper Award in IEEECCNC 2013. He is a member of IEEE.

Mamiko Inamori was born in Kagoshima,Japan in 1982. She received her B.E., M.E., andPh.D. degrees in electronics engineering fromKeio University, Japan in 2005, 2007, and 2009,respectively. In 2009, she joined Keio Univer-sity as an assistant professor. In 2013, she joinedFaculty of Engineering, Tokai University, whereshe is now a lecturer. She received the YoungScientist Award from Ericsson Japan in 2010.Her research interests are mainly concentratedon software defined radio.

Yukitoshi Sanada was born in Tokyo in1969. He received his B.E. degree in elec-trical engineering from Keio University, Yoko-hama Japan, his M.A.Sc. degree in electrical en-gineering from the University of Victoria, B.C.,Canada, and his Ph.D. degree in electrical engi-neering from Keio University, Yokohama Japan,in 1992, 1995, and 1997, respectively. In 1997,he joined the Faculty of Engineering, Tokyo In-stitute of Technology as a research associate. In2000, he joined Advanced Telecommunication

Laboratory, Sony Computer Science Laboratories, Inc., as an associate re-searcher. In 2001, he joined Faculty of Science and Engineering, KeioUniversity, where he is now a professor. He received the Young EngineerAward from IEICE Japan in 1997. His current research interests are insoftware defined radio, cognitive radio, and OFDM systems.