Chapter 13

Summary and Perspectives

Jan M. Rabaey

SummaryandPerspectives

Slide 13.1

[Ref: J. Rabaey, Intel’97]

Low-Power Design Rules – Anno 1997

Minimize waste (or reduce switching capacitance)– Match computation and architecture– Preserve locality inherent in algorithm– Exploit signal statistics– Energy (performance) on demand

Voltage as a design variable– Match voltage and frequency to required performance

More easily accomplished in application-specific than in programmable devices

Slide 13.2

Adding Leakage to the Equation

The emergence of power domainsLeakage not necessarily a bad thing– Optimal designs have high leakage (ELk /ESw ≈ 0.5)

Leakage management requires runtime optimization– Activity sets dynamic/static power ratio

Memories dominate standby power– Logic blocks should not consume power in standby

[Emerged in late 1990s]

Slide 13.3

Low-Power Design Rules – Anno 2007

Concurrency Galore– Many simple things are way better than one complex thing

Always-Optimal Design– Aware of operational, manufacturing, and environmental variations

Better-than-worst-case Design– Go beyond the acceptable and recoup

The Continuation of Voltage Scaling– Descending into ultra low voltages– How close can we get to the limits?

[Ref: J. Rabaey, SOC’07]

Explore the Unknown

Slide 13.4

Some Concepts Worth Watching

Novel switching devices

Adiabatic logic and energy recovery

Self-timed and asynchronous design

Embracing non-conventional computational paradigms

– Toward massive parallelism?

Slide 13.5

Novel Switching Devices

Nanotechnology brings promise of broad range of novel devices

– Carbon-nanotube transistors, NEMS, spintronics, molecular, quantum, etc.

– Potential is there – long-term impact unclear

– Will most probably need revisiting of logic design technology

Outside-the-box thinking essential

Slide 13.6

[Ref : H. Kam, UCB’08]

Example: Nano-Mechanical Relays

Minimum energy in CMOS limited by leakage– Even if it had a perfect (zero leakage) power gate

How about a nano-scale mechanical switch?– Infinite Roff, low Ron

Source Drain

Slide 13.7

Relay Circuit Design and Comparison

90nm CMOS

A

B

A

B

A

B

Cin Cout

A

B A

B

A

BCin Cout

A

BA

B

Sum

Relay FA Cell

tp (ns)

EO

P (

fJ)

90 nm CMOS

[Ref : E. Alon, UCB’08]

Slide 13.8

Adiabatic Logic and Energy RecoveryConcept explored in the 1990s

– Proven to be ineffective at that timeWith voltage scaling getting harder, may become attractive again

Example: Resonant AdiabaticMixed-Signal Processor Array forCharge-Based Pattern Recognition

Adiabatic mixed-signal multiply-accumulation (MAC). Charge-coupled MOS pair represents

[Ref: R. Karakiewicz, JSSC’07]variable capacitive load.

Adiabatic logic modeled as transmission gate driving capacitive load from resonant clock

© IEEE 2007

Slide 13.9

Self-timed and Asynchronous Logic

Synchronicity performs best under deterministic conditions and when duty cycle is highHowever, worst-case model does not fair well when variability is highIn ideal case, self-timed logic operates at “average conditions”

delay

num

ber

Delay distribution as a function of variability

Protocol and signaling overhead of self-timed logic made it unattractive when delay distributions were narrowThis is no longer the case, especially under ultra low-voltage conditions– Effective “synchronous island” size is shrinking

The “design flow” argument does not really hold either− Example: Handshake Solutions [Ref: Handshake]

Slide 13.10

Exploring the Unknown–Alternative Computational Models

• 10–15% of terrestrial animal biomass109 Neurons/“node”Since 105 years ago

Humans

• 10–15% of terrestrial animal biomass

[Courtesy: D. Petrovic, UCB]

105 Neurons/“node”Since 108 years ago

Ants

Easier to “make” ants than humans“Small, simple, swarm”

Slide 13.11

Example: Collaborative Networks

Networks are intrinsically robust → exploit it!Massive ensemble of cheap, unreliable components

Network Properties:– Local information exchange → global resiliency– Randomized topology & functionality → fits nano

properties– Distributed nature → lacks any “Achilles’ heel”

Bio-inspired

Metcalfe’s Law to the rescue ofMoore’s Law!

Boolean Collaborative Networks

Slide 13.12

Learning from Sensor Network Concept

[Ref: J. Rabaey, I&C’04]

Slide 13.13

“Sensor Networks on a Chip”“Large” number of very simple unreliable components provide estimates of resultFusion block combines estimates exploiting the statistics

[Ref: S. Narayanan, Asilomar’07]

Fusion block only “reliable”component

Estimators need to be independentfor this scheme to be effective

Sensor NOC

© IEEE 2007

Computation

y1

yx

Sensor 1

Sensor 2

Sensor 3

Sensor 4

x

Statistically similar

Decomposition

y1

y4

y3

y2

Fusion Block

y

Slide 13.14

100X

with 40% energysavings

Example: PN-Code Acquisition for CDMA

Statistically similar decomposition of function for distributed sensor-based computation.

Robust statistics framework for design of fusion block.

Creates better result with power savings of up to 40% for 8 sensors in PN-code acquisition in CDMA systems

New applications in filtering, ME, DCT, FFT, and others

[Ref: S. Narayanan,Asilomar’07]

Prob (Detection)

© IEEE 2007

Slide 13.15

Book Summary

Energy Efficiency one of the (if not the most) compelling issues in integrated-circuit design today and in the coming decadesThe field has matured substantially– From “getting rid of the fat” and reducing

waste– To “truly energy-lean” design technologies

Still plenty of opportunities to move beyond what can be done today

– There is plenty of room at the bottom

Slide 13.16

Interesting References for Further ContemplationBooks and Book Chapters

L. Svensson, “Adiabatic and Clock-Powered Circuits,” in C. Piguet, Low-Power Electronics Design, Ch. 15, CRC Press, 2005.R. Wasser (Ed.), Nanoelectronics and Information Technology, Wiley-CVH, 2003.

ArticlesE. Alon et al,, “Integrated circuit design with NEM relays,” UC Berkeley Technical Report, 2008.A.P. Chandrakasan, S. Sheng and R.W. Brodersen, “Low-power CMOS digital design,” IEEE Journal of Solid-State Circuits, 27, pp. 473–484, Apr.1992.D.M. Chapiro, “Globally asynchronous locally synchronous Systems,” PhD thesis, Stanford University, 1984.Digital Light Processing (DLP), http://www.dlp.comHandshake Solutions, “Timeless Designs,” http://www.handshakesolutions.comT. Indermaur and M. Horowitz, “Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design,” Symposium on Low Power Electronics, pp. 102–103, Oct.1994.H. Kam, E. Alon and T.J. King, “Generalized scaling theory for electro-mechanical switches ,” UC Berkeley, 2008.R. Karakiewicz, R. Genov and G. Cauwenberghs, "480-GMACS/mW resonant adiabatic mixed-signal processor array for charge-based pattern recognition," IEEE Journal of Solid-State Circuits, 42, pp. 2573–2584, Nov. 2007.D. Liu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE Journal of Solid-State Circuits, 28, pp. 10–17, Jan.1993.S. Narayanan, G.V. Varatkar, D.L. Jones and N. Shanbhag. "Sensor networks-inspired low-power robust PN code acquisition”, Proceedings of Asilomar Conference on Signals, Systems, and Computers, pp. 1397–1401, Oct. 2007.J. Rabaey, “Power dissipation, a cause for a paradigm shift?”, Invited Presentation, Intel Designers Conference, Phoenix, 1997.J. Rabaey, “Embracing randomness – a roadmap to truly disappearing electronics,” Keynote Presentation, I&C Research Day, http://www.eecs.berkeley.edu/~jan/presentations/randomness.pdf, EPFL Lausanne, July 2004.J. Rabaey, “Scaling the power wall”, Keynote Presentation SOC 2007, http://www.eecs.berkeley.edu/~jan/presentations/PowerWallSOC07.pdf, Tampere, Nov. 2007.

Slide 13.17