jan m. rabaey the devices digital integrated circuits© prentice hall 1995 introduction

Jan M. Rabaey

The Devices

Digital Integrated Circuits © Prentice Hall 1995IntroductionIntroduction

Goal of this chapter

• Present intuitive understanding of device operation

• Introduction of basic device equations

• Introduction of models for manual analysis

• Introduction of models for SPICE simulation

• Analysis of secondary and deep-sub-microneffects

• Future trends


The Diode

n

p

p

n

B A SiO2Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol


Depletion Region

hole diffusionelectron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.


Diode Current


Models for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model


Junction Capacitance


Diode Switching Time

Vsrc

t = 0

V1

V2

VD

Rsrc

t = T

ID

Time

VD

ON OFF ON

Space chargeExcess charge


Secondary Effects

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)0.1

0

0

Avalanche Breakdown


Diode Model

ID

RS

CD

+

-

VD


SPICE Parameters


The MOS Transistor

n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor


Cross-Section of CMOS Technology


MOS transistors Types and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact


n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

Transistor: No Voltages


Introduction to VLSI Design © Steven P. Levitan 1998IntroductionIntroduction

Transistor “Off” Vgs<Vt

Vgd

Vgs

Ids

Vds

I=V/R

No Channel exists: Enhancement mode transistor

R

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

Vds does not matter

Ids

Threshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel


The Threshold Voltage


GND

Out

?A

B

Body Effect


n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

Channel Formation Vgs>Vt

Vgd

Vgs

Ids

Vds

I=V/R

Positive Charge on Gate:Channel exists, but no current

since Vds = 0

R

Ids

Current-Voltage Relations

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions



Linear Region Vgs>Vt & Vgd>Vt

Positive Charge on Gate:Channel exists, Current Flows

since Vds > 0Ids = k’(W/L)((Vgs-Vt)Vds-Vds

2/2)

R

Vgd

Vgs

Ids

Vds

I=V/R

R= 1/(k’(W/L)(Vgs-Vt))

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

Ids

Transistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-



Saturation: Vgs>Vt & Vgd<Vt

Positive Charge on Gate:Channel exists, Current Flows

since Vds > 0But: channel is “pinched off”

Ids = (k’/2)(W/L)(Vgs-Vt)2

Vgdn+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

Vgs

Ids

“constant current source”

Ids

Vds

Vgs

Ids

Current-Voltage Relations


I-V Relation

0.0 1.0 2.0 3.0 4.0 5.0

VDS (V)

1

2

I D (

mA

)

0.0 1.0 2.0 3.0VGS (V)

0.010

0.020

÷ I

D

VT

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2V

VGS = 1V

(a) ID as a function of VDS (b) ID as a function of VGS

(for VDS = 5V).

Sq

ua

re D

ep

end

en

ce

VDS = VGS-VT

NMOS Enhancement Transistor: W = 100 m, L = 20 m


A model for manual analysis



Saturation Effects

Which is the resistor?

Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor.


Regions of Operation Summary

REGION NMOSVtn = .7vk’ = 80A/V2

PMOSVtp = -.7vk’ = 27mA/V2

Off Vgs<Vtn

Ids=0Vgs>Vtp

Ids=0

Linear Vgs>Vtn & Vgd>Vtn Vgs<Vt & Vgd<Vtp

Ids= k’(W/L)(Vgs-Vt)Vds-Vds2/2)

Saturation Vgs>Vtn & Vgd<Vtn Vgs<Vtp & Vgd>Vtp

Ids= (k’/2)(W/L)(Vgs-Vt)2(1+Vds)


Computed Curves

Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

Linear Resistor


Spice Curves

Vgs = 5v

Vgs = 4v

Vgs = 3v

Vgs = 2v

Vgs = 1v

Fitting level-1 model for manual analysis

VGS = 5 V

VDS = 5 V VDS

ID

Long-channel

approximation

Short-channelI-V curve

Region of

matching

Select k’ and such that best matching is obtained @ Vgs= Vds = VDD



Retrofitted Level 1 Parameters1.2um CMOS

NMOS» VTO = 0.743 V

» K’ = 19.6 A/V2 (20 vs 80) = 0.06 V-1

PMOS» VTO = -0.739 V

» K’ = 5.4 A/V2 (5 vs 27) = 0.19 V-1

Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


The Gate Capacitance


Average Gate Capacitance

Most important regions in digital design: saturation and cut-off

Different distributions of gate capacitance for varying

operating conditions


Diffusion Capacitance


The Sub-Micron MOS Transistor

• Threshold Variations

• Parasitic Resistances

• Velocity Sauturation and Mobility Degradation

• Subthreshold Conduction

• Latchup


Parasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


Velocity Saturation (2)

VDS (V)

I D (

mA

)

Lin

ea

r D

ep

en

de

nc

e

VGS = 5

VGS = 4

VGS = 3

VGS = 2

VGS = 1

0.0 1.0 2.0 3.0 4.0 5.0

0.5

1.0

1.5

(a) ID as a function of VDS (b) ID as a function of VGS(for VDS = 5 V).

0.0 1.0 2.0 3.0VGS (V)

0

0.5

I D (

mA

)

Linear Dependence on VGSDigital Integrated Circuits © Prentice Hall 1995IntroductionIntroduction

Sub-Threshold Conduction

0.0 1.0 2.0 3.0VGS (V)

10 12

10 10

10 8

10 6

10 4

10 2

ln(I

D)

(A)

Subthreshold exponential region

Linear region

VT


Latchup

(a) Origin of latchup (b) Equivalent circuit

VDD

Rpsubs

Rnwell p-source

n-source

n+ n+p+ p+ p+ n+

p-substrateRpsubs

Rnwell

VDD

n-well


SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular


MAIN MOS SPICE PARAMETERS


SPICE Parameters for Parasitics


SPICE Transistors Parameters


Technology Evolution


Spice Parameters for Parasitics


Process Variations

Devices parameters vary between runs and even on the same die!

Variations in the process parameters, such as impurity concentration den-sities, oxide thicknesses, and diffusion depths. These are caused by non-uniform conditions during the deposition and/or the diffusion of theimpurities. This introduces variations in the sheet resistances and transis-tor parameters such as the threshold voltage.

Variations in the dimensions of the devices, mainly resulting from thelimited resolution of the photolithographic process. This causes (W/L)variations in MOS transistors and mismatches in the emitter areas ofbipolar devices.


Impact of Device Variations

1.10 1.20 1.30 1.40 1.50 1.60

Leff (in mm)

1.50

1.70

1.90

2.10

De

lay

(nse

c)

–0.90 –0.80 –0.70 –0.60 –0.50

VTp (V)

1.50

1.70

1.90

2.10

De

lay

(nse

c)

Delay of Adder circuit as a function of variations in L and VT


jan m. rabaey the devices digital integrated circuits© prentice hall 1995 introduction

Documents