itrs 2008の概要semicon.jeita.or.jp/strj/strj/2008/5a_irc.pdfhalf-pitch, gate-length 1.0 10.0...

STRJ WS: March 5, 2009, IRC 1

ITRS 2008の概要

半導体技術ロードマップ専門委員会（STRJ）委員長

石内秀美（東芝）


主要略語一覧（アルファベット順）

• ERD: Emerging Research Devices 新探究デバイス• ERM: Emerging Research Materials 新探究材料• EUV: Extreme Ultra Violet• FEP: Front End Process (ITRSの章の名前でもある）• High-k: 高誘電率（比誘電率の記号としてkを使うことから）絶縁膜。MOSFET用のゲート

絶縁膜• ITRS: International Technology Roadmap for Semiconductors 国際半導体技術ロード

マップ• JEITA: 社団法人電子情報技術産業協会（Japan Electronics and Information

Technology Industries Association）• Low-k: 低誘電率（比誘電率の記号としてkを使うから）絶縁膜。多層金属配線用絶縁膜• M1: Metal-1 最下層（第１）の金属配線層• MPU: Micro Processor Unit マイクロプロセッサ• NTRS: National Technology Roadmap for Semiconductors 米国のSIAが編集した半導

体技術ロードマップ• PIDS: Process Integration, Devices and Structures (ITRSの章の名前）• SIA: Semiconductor Industry Association 米国半導体工業会• STRJ: Semiconductor Technology Roadmap committee of Japan 半導体技術ロード

マップ専門委員会。JEITA半導体部会半導体技術委員会の専門委員会


STRJ, ITRSの歴史と現状

1998Update

JapanKorea

Europe

TaiwanUSA

1991 MicroTech 2000

Workshop Report

1992NTRS

1994NTRS

1997NTRS

1999ITRS

2000Update

2001ITRS

2002Update

2003ITRS

2004Update

2005ITRS

ITRSSIA Roadmap

STRJ1998年発足半導体産業・技術開発の経済性委員会

1999

STRJ報告

2000

STRJ報告

2001

STRJ報告

2002

STRJ報告

2003

STRJ報告

タスクフォース、クロスカット活動

1990 1999 20051998

2004

STRJ報告

2005STRJ報告

2006Update

2006

2007ITRS

Web版

2006STRJ報告

2007STRJ報告

20072001 20042000 2002 2003

STRJ WS: March 5, 2009, IRC

2008Update


ITRS 2008 Update の概要

2008年の改訂は全面改訂ではなく、基本的には表の数字の見直しのみ。

各章ごとに改訂内容の要約を作成し、公開

NAND Flashメモリの微細化トレンドについて議論中。微細化トレンドをさら

に前倒しするかどうかがポイントであるが、今回は改訂を見送る。

MPUとロジックLSIのMOSトランジスタの微細化トレンドを遅らせる。特に、

HP (High Performance, 高性能）用途のゲート長の微細化はITRS 2007年

版より遅れており、2007年以降、0.7倍／3.8年のスケーリングトレンドを採

用する。LOP （Low Operating Power, 低動作電力)やLSTP (Low

Standby Power, 低スタンバイ電力)のゲート長との差は、縮まる方向。

上記に伴い、FD-SOI(完全空乏型のSOI基板）とFinFET（フィン型のトランジ

スタ）の導入時期も遅らせる

ERD（新探究デバイス）WGでは新探究デバイスの候補を７つに絞り込み、

カーボン系の材料（グラフェン、カーボンナノチューブ）を有望とする。


2007 Definition of the Half Pitch - unchanged[No single-product “node” designation; DRAM half-pitch still litho driver; however,

other product technology trends may be drivers on individual TWG tables]

Poly Pitch

Typical flash Un-contacted Poly

FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2

8-16 Lines

Metal Pitch

Typical DRAM/MPU/ASIC Metal Bit Line

DRAM ½ Pitch = DRAM Metal Pitch/2

MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2

Source: 2005 ITRS - Exec. Summary Fig 2


Production Ramp-up Model and Technology Cycle TimingVo

lum

e (P

arts

/Mon

th)

1K

10K

100K

Months0-24

1M

10M

100M

AlphaTool

12 24-12

Development Production

BetaTool

ProductionTool

First Conf.

Papers

First Two CompaniesReaching

Production Volu

me

(Waf

ers/

Mon

th)

2

20

200

2K

20K

200K

Source: 2005 ITRS - Exec. Summary Fig 3

Fig 3


7

2007 ITRS Product Technology Trends - Half-Pitch, Gate-Length

1.0

10.0

100.0

1000.0

1995 2000 2005 2010 2015 2020 2025

Year of Production

Prod

uct H

alf-P

itch,

Gat

e-Le

ngth

(nm

)

DRAM M1 1/2 Pitch

MPU M1 1/2 Pitch(2.5-year cycle)

Flash Poly 1/2 Pitch

MPU Gate Length -Printed

MPUGate Length -Physical

MPU M1.71X/2.5YR

Nanotechnology (<100nm) Era Begins -1999

GLpr IS =1.6818 x GLph

2007 - 2022 ITRS Range

MPU & DRAM M1& Flash Poly

.71X/3YR

Flash Poly.71X/2YR

Gate Length.71X/3YR

Before 1998.71X/3YR

After 1998.71X/2YR

[WAS]


8

“10nm” 5yrGLph delay




• GLphysical 2008 Update IS: 3.8yr cycle after 2007; enabled by “Equiv. Scaling”• FEP and PIDS have proposed shifted/interpolated tables; full model redo in ‘09• GLprinted parallel to MPU/DRAM M1 Half-Pitch; shrinking etch ratio to GLphy

[IS]


9

2007 ITRS Product Function Size Trends - Cell Size, Logic Gate(4t) Size

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

2000 2005 2010 2015 2020 2025

Year of Production

Cel

l, Lo

gic

Gat

e Si

ze(u

m2

)

DRAM Cell Size (u2)

MPU SRAM Cell Size(6t)(u2)

MPU Gate Size(4t)(u2)

Flash Cell Size (u2)SLC

Flash Eqv.bit Size(u2)2bit MLC

Flash Eqv.bit Size(u2)4bit MLC - New

Figure 9[’07] ITRS Product Function Size 2008 Update:[NO CHANGE to MPU and Flash;Small change ’07-’09 to DRAM]

Flash: 4f2 LastDesign Physical AreaFactor Improvement

DRAM: 6f2 is lastDesign Area

Factor Improvement

Logic Gate: NODesign Area

Factor Improvement(Only Scaling)

SRAM: gradualDesign Area

Factor Improvement

Flash: (MLC @ 2 bits/cell =2f2 Equivalent Area Factor)

Flash 4 bits/cell1f2 Beginning 2010

(@ 2 MLC bits/physical cell area)

(@ 4 MLC bits/physical cell area)

DRAM 6f2Pull-in to ‘06

Flash cell areaReduced due to

2YR cycleExtension


Past Future

DRAM - SmallAdjustments

In 2008


10

Figure 10 ITRS Product Functions per Chip

Average Industry"Moores Law“ :

2x Functions/chip Per 2 Years

2007 ITRS Product Technology Trends - Functions per Chip

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1995 2000 2005 2010 2015 2020 2025

Year of Production

Prod

uct F

unct

ions

/Chi

p[ G

iga

(10^

9) -

bits

, tra

nsis

tors

]

Flash Bits/Chip (Gbits)Multi-Level-Cell (4bitMLC)

Flash Bits/Chip (Gbits)Multi-Level-Cell (2bitMLC)

Flash Bits/Chip (Gbits)Single-Level-Cell (SLC )

DRAM Bits/Chip (Gbits)

MPU GTransistors/Chip- high-performance (hp)

MPU GTransistors/Chip- cost-performanc (cp)


Past Future

DRAM Bits/chip

1-yearDelay;

Flash MLC 4 bits/chip

Added

Flash SLCBits/chip

for 1-year Pull-in

[Unchanged for 2008]

Moore’s LawOn

Track!


11

D esign M ax O n-C hip C lock Frequency

1.0

10.0

100.0

1995 2000 2005 2010 2015 2020 2025

Year

(Ghz

)

D esignM ax.Freq.2001 ITR S

D esignM ax.Freq.2003ITR S

Extrapo la tion /In terpo la tion o f2005W A SITR SProposa l

F ina l M axO n-C hipLoca l C lockFreq(Aug'07)

Including 2005 ITR S and F inal (Aug'07) 2007 D esign TW G

1.17x/year (2x/4 .5yrs)

1 .29x/year (2x/2 .5yrs)

"G ap" D e layed by 3 years

in 2005 ITR S

1.41x/year (2x/2yrs)

IS : Design/A rchitecture: reduction of m axim um # 0f inverter de lays to fla t a t 12 beg inning 2007 W AS: (2001 ITR S: fla t a t 16 a fter 2006)

W AS/IS

P ast <-----> Future

2007 Des TWG Actual History of Average On-Chip

~ 21% CAGR

Gamers“Clock-Doubling?”

New Design TWG2007 ITRS Final “IS”

Ave 8% CAGR

2005/06ITRS

“WAS”


Performance and Power ManagementEnabled by “Equivalent Scaling”


12

MPU “GHz” by “Cores”

0.0001

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010 2020 2030

CP

U "G

Hz"

CLK (GHz)Clk RoadmapCores * Clock

Actual Forecast

Assumes 2007 CLK & cores roadmap

Multiple cores will continued historic "GHz" trend with a slower ramp in CLK rates

4004

8080

Pentium

~17x

Source: ITRS Public Conference in Seoul, Dec. 2008


ITRS Low-k RoadmapEf

fect

ive

Die

lect

ric C

onst

ant;

keff

Year of 1st Shipment

ITRS1999

ITRS2001

ITRS2005ITRS2005ITRS2007-2008

ITRS2003

Source: ITRS Public Conference in Seoul, Dec. 2008


Moore’s Law & MoreMore than Moore: Diversification

Mor

e M

oore

: M

inia

turiz

atio

nM

ore

Moo

re:

Min

iatu

rizat

ion

Combining SoC and SiP: Higher Value SystemsBas

elin

e C

MO

S: C

PU, M

emor

y, L

ogic

BiochipsSensorsActuators

HVPowerAnalog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm...V

130nm

90nm

65nm

45nm

32nm

22nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Beyond CMOS

2007 ITRS Executive Summary Fig 5[updated for 2007]

Traditional ORTC Models

[Geo

met

rical

& E

quiv

alen

t sca

ling]

Scal

ing

(Mor

e M

oore

)Functional Diversification (More than Moore)

[2007 –add Definitions;Update Graphic]

Continuing SoC and SiP: Higher Value Systems

HVPower Passives


1. Scaling (“More Moore”)a. Geometrical (constant field) Scaling refers to the continued shrinking of

horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers.

b. Equivalent Scaling which occurs in conjunction with, and also enables, continued Geometrical Scaling, refers to 3-dimensional device structure (“Design Factor”) Improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip.

2. Functional Diversification (“More than Moore”)Functional Diversification refers to the incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law," but provide additional value to the end customer in different ways. The "More-than-Moore" approach typically allows for the non-digital functionalities (e.g.RF communication, power control, passive components, sensors, actuators) to migrate from the system board-level into a particular package-level (SiP) or chip-level (SoC) potential solution.

2007 ITRS Definitions: “More Moore” and “More than Moore”


year

Beyond CMOS

Elements

Source: ERD-WG/JEITA in Japan

Existing technologies

New technologies

Evolution of Extended CMOS


17

ERD（新探究デバイス）の７候補

（２００９年版に反映予定）委員の投票の結果ではCarbon-based Nanoelectronicsが１位

• Nano-electro Mechanical Switches• Collective Spin Devices• Spin Torque Transfer Devices• Atomic Switch / Electrochemical Metallization• Carbon-based Nanoelectronics• Single Electron Transistors• CMOL / Field Programmable Nanowire

Interconnect (FPNI)


SP2 Carbon: 0-Dim. to 3-Dim.（炭素原子ｓｐ２混成軌道が作る構造：０次元から３次元まで）

Fullerenes (C60) Carbon Nanotubes GraphiteGraphene

0D 1D 2D 3D

Atomic orbital sp2 σ

π


• ITRSの公式ホームページ– http://www.itrs.net/ または http://public.itrs.net/– ITRS 2008 Update, ITRS 2007 Editionはじめ、ITRSの

最新情報

• JEITAのロードマップのホームページ– http://strj-jeita.elisasp.net/strj/index.htm– ITRS 2007の日本語訳（過去の版の和訳もあり）

– ITRSの過去の版（英文）へのリンク

– STRJ（半導体技術ロードマップ専門委員会）の活動情報

関連ｗｅｂサイトのURLさらに詳しい資料については下記を参照願います

http://www.itrs.net/

itrs 2008の概要semicon.jeita.or.jp/strj/strj/2008/5a_irc.pdfhalf-pitch, gate-length 1.0 10.0...

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