issn 1755-4535 three-phase hybrid multilevel inverter … · the proposed mli consists of a reduced...

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Published in IET Power ElectronicsReceived on 29th March 2013Revised on 7th November 2013Accepted on 28th November 2013doi: 10.1049/iet-pel.2013.0237

256The Institution of Engineering and Technology 2014

ISSN 1755-4535

Three-phase hybrid multilevel inverter with lesspower electronic components using space vectormodulationMd. Mubashwar Hasan1, Saad Mekhilef1, Mahrous Ahmed2

1Power Electronics and Renewable Energy Research Laboratory (PEARL), Department of Electrical Engineering, Faculty of

Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia2Aswan Faculty of Engineering, Aswan University, Aswan, Egypt

E-mail: [email protected]

Abstract: This study presents a new design and implementation of a three-phase hybrid multilevel inverter (MLI) using spacevector modulation. The proposed MLI consists of a reduced number of dc sources and switches to minimise the controlcomplexity. The developed topology consists of two stages: main stage and auxiliary stage. The main stage is a conventionalthree-phase inverter with one high-voltage input dc source and six switches. The auxiliary stages contain three individualcells. Each cell consists of two switches and one low-voltage input dc source. This topology is a modular type and withoutchanging the previous connection it can be extended for more number of output voltage levels by adding certain number ofauxiliary stages. A space vector modulation control technique has been utilised in order to generate different switchingsequences. The special feature of the proposed system is its capability to maximise the number of voltage levels using areduced number of isolated dc voltage sources and electronic switches. A prototype has been developed and tested for variousmodulation indexes to verify the control technique and performance of the topology. Experimental results validate thesimulation results and the experimental results show a good similarity with the simulation results.

1 Introduction

Neutral point clamped (NPC) topology was the firstmultilevel inverter (MLI) design proposed by Nabae et al.[1]. The MLI topologies can be categorised in three basicgroups; NPC, the flying capacitor and the cascadedH-bridge (CHB) multilevel inverter [2–4]. The CHB MLIconsists of a number of series connected H-bridge units.Each unit consists of four switches and one dc voltagesource. The MLI output voltage is synthesised bycombination of all the H-bridge unit input dc voltages [5,6]. Each H-bridge unit can be used with lower-voltagerating components. This topology has modularcharacteristic, since all the units are similar and their controlstrategies are same. It is easy to replace a faulty unit. It isalso possible to bypass the faulty module by applying anefficient control technique, even without discontinuing theload [7]. The CHB topology can be divided into twogroups: (i) symmetric structure and (ii) asymmetricstructure. In case of symmetric structures, the magnitudes ofall the dc supplies are same and magnitude of the dc inputsupplies are unequal in asymmetric cases. If there arek-numbers of H-bridge units per phase arm, then thenumber of levels in the output line voltage should be 2k +1. Each unit consists of four switches and one isolated inputdc supply. The isolated dc supply can be obtained bysingle-phase or three-phase diode-based rectifier

arrangement [8, 9]. Transformers are used to ensure properelectrical isolation. Nowadays, high-frequency link (HFL)transformer modules have been used for efficient design [9,10]. Sometimes for high-power applications, theconventional diode rectifier-based dc–dc converters becomebulky, but HFL dc–dc converter becomes compact as thesize of the transformer becomes smaller [11]. This HFLalso is suitable for regenerative applications.Hybridisation is performed using similar and dissimilar

circuit configurations in MLI. This hybridisation can bedone in several ways depending on the designer’s will. Itincreases the number of voltage levels and enhanceperformance by minimising the number of systemcomponents. Actually, the ultimate goal of the researches isto obtain the maximum number of voltage levels using aminimum number of input dc sources and switches [12,13]. Therefore the definition of the level number per switch(LSR) has been emerged recently to figure out the trade-offbetween increasing MLI levels and decreasing its powerelectronic device count.A couple of techniques have been developed previously in

order to increase the LSR. Each technique has someadvantages and disadvantages with respect to the controltechnique and topology. Some systems use conventionalthree-phase and three-level inverter [14]. Conventionalselective harmonic elimination control and space vectorpulse width modulation (SVPWM) technique have been

IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1256–1265doi: 10.1049/iet-pel.2013.0237

Fig. 1 General proposed hybrid MLI topology circuit

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applied in order to work as an induction motor drive. Thesesystems are suitable for only limited power requirementbecause of the severe harmonic component injection. Dualthree-phase three-level inverters are being used in someother systems [15–19]. Some systems utilise one open endof the induction motor to validate a second emergency pathfor the power flow [17, 18]. These systems are more robust.In case of any inverter failure, the second one is capableenough to serve the total operation. These systems allowlow-harmonic contents towards the load and eligible forhigh-power demand. Five-level output voltage waveformscan be generated; those do not meet the requirements ofhigh-performance induction motor (IM). In other words,five-level voltage waveforms are not improved enoughcompare with the three-level waveforms. In addition, a lowvalue of LSR is obtained [15–19].The other MLI topologies use cascaded system and show
better performance [20–22]. To obtain better performance,some systems [22] utilise four cells in each phase armhaving 48 switches to produce 81-levels in line voltages.However, the overall system complexity increases becauseof using high number of switches. Here, LSR is equal to81/48, which is very high in comparison with some otherproposed systems [15–22]. The higher the value of LSRindicates certainly a better system.The main aim of this paper is to overcome some selective

prime difficulties of MLI. Those are: the necessity of largenumber of isolated dc supply and semiconductor switches,high switching frequency, high switching loss at thehigh-voltage stage. The overall cost is lower because of thereduced number of dc supply and system components ofthe suggested topology. The switching complexity has beenminimised by reducing the number of switches. Thehigh-voltage stage minimises the switching loss whileavoiding high switching frequency. The inverter circuit, itsswitching variables and the operational principle of theproposed MLI have been introduced in Section 2. Thespace vector control strategy has been described in Section3. In Section 4, simulation results and discussion have beenpresented. Experimental results have been presented inSection 5. Finally, Section 6 summarises the proposedsystem concepts.

2 Operational principle of the proposedmultilevel inverter model

Fig. 1 shows the generalised three-phase configuration of theproposed hybrid multilevel inverter topology for (2k + 1)thlevel in the line voltage. This inverter topology consists ofone main stage, (k−1) units of auxiliary stages, ‘6k’switches and ‘3(k−1) + 1’ isolated dc voltage sources. Allthe auxiliary stages are connected in series with the mainstage. The main stage is a conventional three-phase sixswitch inverter. Each auxiliary cell consists of two switchesand one dc input voltage. The basic auxiliary cell of theproposed inverter contains two switches (S1 and S2). S1 andS2 always operate in a complementary mode. By usinginput dc supply in each auxiliary cell, two output voltagelevel can be obtained. Therefore each of the auxiliary cellsgives either Vo = 0 (when switch S2 is ON) or Vo = Vdc

(when S1 is ON). To avoid short-circuit condition, theswitches S1 and S2 never be switched on at a time.If each phase arm consists of ‘k−1’ number of auxiliary

cells and one main cell, then the dc source voltages of any


phase arm can be expressed by a geometric series form.The series can be written as follows.Vk (The main stage) = 2(k−1)Vdc, V(k−1) = 2(k−2)Vdc, V(k−2) =

2(k−3)Vdc, …, V1 = Vdc, where k−1 = the number of auxiliarycell. The number of levels in the load node voltages (polevoltages) (vaN, vbN, vcN) referred to the dc bus voltage canbe expressed as (1 + 1) + 2 + 4 +… + 2(k−1). If the MLIhas k = 2, then it would have one main stage with V2 = 2Vdc

and one auxiliary stage. Therefore the pole voltages (vaN,vbN, vcN) have four levels (1 + 1 + 2) with values of (0, Vdc,2Vdc, 3Vdc).The line-to-line voltages can be calculated from the

inverter pole voltages vaN, vbN and vcN as follows

vab = vaN − vbNvbc = vbN − vcNvca = vcN − vaN

(1)

Therefore the phase voltages (van, vbn, vcn) of a Y-connectedbalanced three-phase load are related to the inverter polevoltages by (2)

vanvbnvcn

⎡⎣

⎤⎦ = 1

3

2 −1 −1−1 2 −1−1 −1 2

⎡⎣

⎤⎦ vaN

vbNvcN

⎡⎣

⎤⎦ (2)

1257& The Institution of Engineering and Technology 2014

Fig. 2 Switching vectors of three-level converter in the complexd–q -plane

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Using Park’s transformation, the voltage vector of anyinverter state can be defined by (3)
vdvq

[ ]= 1

3

1 −0.5 −0.5

0

��3

√

2−

��3

√

2

⎡⎣

⎤⎦ van

vbnvcn

⎡⎣

⎤⎦ (3)

The voltage vector approximation method is suitable for theinverters to generate large number of levels. The l-levelinverter has [3 × l × (l−1) + 1] equally spaced voltagevectors in its voltage space diagram. For seven-level, wehave [3 × 7 × (7–1) + 1] = 127 voltage vectors.

3 Space vector modulation for the proposedMLI topology

Generally, every switching state creates specific three-phasevoltages (vaN, vbN, vcN) with respect to the neutral of the dcbus voltage, which can be defined by (4)

vaN = kaVdc

vbN = kbVdc

vcN = kcVdc

(4)

where ka, kb and kc∈ [0, 1, 2, 3, …, + (2k−1)] and switchingstates of inverter line-to-line voltages (vab, vbc, vca) can becalculated by (5)

vab = ka − kb( )

Vdc = kabVdc

vbc = kb − kc( )

Vdc = kbcVdc

vca = kc − ka( )

Vdc = kcaVdc

(5)

Equation (5) can be expressed in matrix form as follows

V l−l(kab, kbc, kca)= vab vbc vca

[ ]T= Vdc ka − kb

( )kb − kc( )

kc − ka( )[ ]T

(6)

where kbc, kbc and kca∈ [−(2k−1), …, −3, −2, −1, 0, 1, 2, 3,…, (2k−1)]. The vector form of the line-to-line referencevoltage vector in steady state can be stated by (7)

VREF = VREF

∣∣ ∣∣ cos(vt) cos vt − 2p

3

( )cos vt + 2p

3

( )[ ]T

(7)

Vl−l(kab, kbc, kca) and VREF defined by (6) and (7) in d–qstationary plane are represented by the followingtransformations

V(l−l)d V(l−l)q

[ ]T = V ∗l−l = 1 ej(2p/3) ej(4p/3)

[ ]× V l−l kab, kbc, kca( ) (8)

V ∗REF = V(REF)d V(REF)q

[ ]T= 1 ej(2p/3) ej(4p/3)

[ ]VREF

(9)

Using the definition of the vector normalisation, the length ofthe reference vector V ∗

REF

∣∣ ∣∣ is given by (10)

V ∗REF

∣∣ ∣∣ = ��VREF VREF

√ = V l−l

��3

2

√(10)


In addition, using the same definition, the length of the largestvoltage space vector of Vl−l(kab, kbc, kca)

is given by (11)

V l−l(kab, kbc, kca)

∣∣∣ ∣∣∣max

=��2

√(l − 1)Vdc (11)

For simplicity, the 19-switching vectors of a three-levelinverter have been shown in Fig. 2 and the position of theequivalent phase switches have been defined in (8). Themaximum length of the reference vector can be obtainedfrom the radius of the largest circle, which inscribes in theoutermost hexagon as shown in Fig. 2. The maximumlength of the reference vector is given by (12)

VREF

∣∣ ∣∣max= V l−l(kab, kbc, kca)

∣∣∣ ∣∣∣max

cosp

6

( )(12)

In Fig. 2, the length of the largest space vector


∣∣∣ ∣∣∣max

( )represents the limit of the linear

modulation index (Ma), which is equal to 2��2

√Vdc. The

largest reference voltage vector VREFmax has beenrepresented by a circle, which touches the outer hexagon.The length of |VREF|max is equal to 2

��2

√Vdc cos(p/6). The

modulation index (Ma) is defined by the ratio of thereference voltage length to the largest space vector length


∣∣∣ ∣∣∣max

[23, 24]

Ma =VREF

∣∣ ∣∣2

��2

√Vdc

The circle, which has been represented by the largestreference voltage vector (VREFmax), which also representsthe limit of the linear operation. Here, the modulation index(Ma) can be written as, Ma = cos(π/6) = 0.866.

3.1 Determination of switching times of inverterswitches

The reference voltage vector V ∗REF has been defined by the

control algorithm in (9); is sampled at the rate of switchingfrequency fs. The sampling time interval, Ts = 1/fs. Thesampling time interval extends over three subcycles t1, t2and t3. V

∗REF is an arbitrary complex quantity and it cannot

be generated by the inverter. Therefore it is approximatedby the voltage space vectors V ∗

l−l(kab,kbc,kca). This has been


Fig. 3 Simulation results of the seven-level MLI at modulation index = 0.3

a Pole voltages vaN, vbN and vcNb Line-to-line load voltages vab, vbc and vcac Load line currents ian, ibn and icnd Line current spectra

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given by (8), where during each modulation subcycle aswitching sequence is generated. Consequently, the inverterpole voltages van, vbn and vcn can be evaluated as well asswitches states. To normalise the reference voltage vectorand locate its sector to genearte switching pulses of theproposed hybrid MLI are described below [22–24].

Step 1: normalisation of the reference line-to-line space vectorvoltage is as follows

V ∗REF = (l − l)

VREF

Vdc(13)

Normalisation depends on the number of voltage levels ‘l’and the value of the dc bus voltage ‘Vdc’. For seven-levelinverter, l = 7.Step 2: the normalised voltage vector V ∗

REF is transformedinto Vn. Here, the imaginary part of V ∗

REF is multiplied by1/

��3

√( )which flattens the hexagon in to the normal

hexagon and the flat hexagon [24]. Transformation of V ∗REF

into Vn makes it possible to avoid simple on-linecomputation of the switching states and times. Three zones(zone 1, zone 2 and zone 3) are found in the complex planed–q depending on the angle ϑ of Vn as follows

q = 180

p

( )tan−1 Vqn

Vdn

( )

Here, Vdn and Vqn are the d–q components (real and imaginary


parts) of the V ∗REF

q =0 to 135◦ zone 1135 to 225◦ zone 2225 to 360◦ zone 3

⎧⎨⎩

Step 3: calculating the three vectors vn1, vn2 and vn3 of thetriangle where the vector Vn is located, calculating thenearest three switching states kab, kbc and kca and theircorresponding switching times t1, t2 and t3are in the next step.Step 4: by inserting switching states kab, kbc and kca in (4),switches states ka, kb and kc of van, vbn and vcn can beevaluted as follows by (14)

1 −1 00 1 −1−1 0 1

⎡⎣

⎤⎦ ka

kbkc

⎡⎣

⎤⎦ = 1

Vdc

vabvbcvca

⎡⎣

⎤⎦ =

kabkbckca

⎡⎣

⎤⎦ (14)

It should be noted that (14) contains three unknowns ka, kband kc. Solution of this set of equations is not unique. Onemethod is to reduce the number of unknowns from three totwo. It is done by assuming an appropriate solution for oneof the three unknowns. We assume ks is the solution of kcand substituting it into (14), the other two variables ka andkb becomes

kc = kska = ks − kcakb = ks + kbc

(15)



a Pole voltages vaN, vbN and vcNb Line-to-line load voltages vab, vbc and vcac Load line currents ian, ibn and icnd Line current spectra


a Pole voltages vaN, vbN and vcNb Line-to-line load voltages vab, vbc and vcdc Load line currents ian, ibn and icnd Line current spectra

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Fig. 6 Functional block diagram of the experimental setup for twostages (k = 2) configuration

Fig. 7 Experimental results of the seven-level MLI at modulation index

a Switching signals of auxiliary and main stages switches [2 V/div, 2.5 ms/div], reb Pole voltages vaN, vbN and vcN [50 V/div, 10 ms/div]c Line-to-line load voltages vab, vbc and vca, and load phase current ian [100 V/divd Line current spectra

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To ensure that ka, kb and kc are not located outside theirboundary limits [0, 1, 2, 3, …, (2k−1)], a better choice forks can be derived from (14) as follows

0 ≤ ka ≤ 2k −1 ⇒ 0 ≤ − vcaVdc

+ ks ≤ 2k −1

0 ≤ kb ≤ 2k −1 ⇒ 0 ≤ − vbcVdc

+ ks ≤ 2k −1

0 ≤ kc ≤ 2k −1 ⇒ 0 ≤ − vbcVdc

+ ks ≤ 2k −1

(16)

To satisfy the above (15) and (16), the condition has beenchosen in order to obtain a proper ks and it can be writtenas follows

ks = max 0, max − vcavdc

( ), − vbc

vdc

( )[ ][ ]

Obtaining a proper value of ks, the values of ka, kb and kc canbe caculated using (15).

= 0.3

spectively

, 1 A/div, 10 ms/div]


Fig. 8 Experimental results of the seven-level MLI at modulation index = 0.7

a Switching signals of auxiliary and main stages switches [2 V/div, 2.5 ms/div], respectivelyb Pole voltages vaN, vbN and vcN [50 V/div, 5 ms/div]c Line-to-line load voltages vab, vbc and vca, and load phase current ian [100 V/div, 1 A/div, 10 ms/div]d Line current spectra

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4 Simulation results

MATLAB/SIMULINK® software is used to simulate theproposed topology using aforementioned SVM controlalgorithm described in Section 3. For simplicity, an inverterwith one main stage and one auxiliary stage (k = 2) ischosen to present the simulation and experimental resultsduring different modulation indexes. This configurationgenerates three-phase seven-level output line voltages. Theinput dc supply voltage ratio between low-voltage auxiliarystage and high-voltage main stage is 1:2. The modulationindexes 0.3, 0.7 and 0.8 are chosen to show all the requiredresults and outputs. A balanced Y-connected three-phaseload is used, that consists of 24 Ω and 5 mH in each phaseas well as Vdc = 40 V is used. The selected high resistiveload is connected to check the worst case condition of load.Figs. 3–5 show simulation results of the proposed MLI

during modulation indexes of Ma = 0.3, 0.7 and 0.8,respectively. Each figure shows inverter pole voltages (vaN,vbN, vcN), line-to-line voltages (vab, vbc, vca), line currents(ian, ibn, icn) and line current harmonic spectra, respectively.The line current total harmonic distortion (THD) are 7.45,3.04 and 1.91% during modulation indexes of Ma = 0.3, 0.7


and 0.8, respectively. The THD of the line current must be<5% to satisfy IEEE 1547–2003 standard and IEEE 519standard [25, 26]. Therefore the proposed MLI should beacceptable for modulation index beyond 0.5 for this specificworst case of load test.Only the auxiliary stage input dc supplies contribute to the

output voltage, when the modulation index is ≤0.35. In suchcase, the behaviour of the proposed hybrid MLI is similar tothe conventional three-phase three-level inverter and the linevoltages contain three levels (−Vdc, 0, Vdc). On the otherhand, the main stage input dc voltage also contributes to theoutput as well, if the modulation index becomes larger than0.35. Moreover, the magnitude and the number of levels inthe output voltages also increase during modulation index isgreater than 0.35.During modulation index of 0.7, the pole voltages (vaN,

vbN, vcN) show four levels of (0, Vdc, 2Vdc), whereas theline-to-line voltages (vab, vbc, vca) contain seven levels(−2Vdc, −Vdc, 0, Vdc, 2Vdc). The proposed hybrid MLI polevoltages (vaN, vbN, vcN) show four levels of (0, Vdc, 2Vdc,3Vdc), whereas the line-to-line voltages (vab, vbc, vca)contain seven levels (−3Vdc, −2Vdc, −Vdc, 0, Vdc, 2Vdc,3Vdc) during modulation index of 0.8.


Fig. 9 Experimental results of the seven-level MLI at modulation index = 0.8

a Switching signals of auxiliary and main stages switches [2 V/div, 2.5 ms/div], respectivelyb Pole voltages vaN, vbN and vcN [100 V/div, 5 ms/div]c Line-to-line load voltages vab, vbc and vca, and load phase current ian [100 V/div, 1 A/div, 10 ms/div]d Line current spectra

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5 Experimental results and discussion

A 100 W prototype for the proposed system is developed inthe laboratory to validate the proposed MLI topology usingSVM control scheme. The experimental work is done usingan open-loop controller using constant input dc busvoltages. A digital signal processor (DSP) TMS320F2812 isutilised to generate switching pulses. Fig. 6 shows thefunctional block diagram of the experimental setup andmain steps of generating switching pulses, whateverexplained in Section 3. Same system parameters are usedfor both simulation and experimental models in order tocompare simulation and experimental results. A balancedY-connected three-phase load, that consists of 24 Ω and 5mH in each phase and Vdc = 40 V is used.Figs. 7–9 show experimental results of the proposed MLI

for modulation indexes of Ma = 0.3, 0.7 and 0.8,respectively. Each figure contains the switching pulses ofthe main and auxiliary stages, pole voltages (vaN, vbN, vcN),line-to-line voltages (vab, vbc, vca), line current (ian) and linecurrent harmonic spectra, respectively.As mentioned earlier, only the auxiliary stage works and

Fig. 7b shows two levels (0, Vdc) in the generated polevoltages as well as Fig. 7c shows three levels (0, −Vdc, Vdc)in the line-to-line voltages during modulation index is less


than or equal to 0.35. The main stage input dc supply hasno contribution on the output voltages, which is alsoindicated by the switching pulses. However, both the mainand auxiliary stages contribute on the output voltages whenthe modulation indexes is >0.35. Fig. 8b shows three levels(0, Vdc, 2Vdc) in the pole voltages and Fig. 8c shows fivelevels (0, −Vdc, −2Vdc, Vdc, 2Vdc) in the output line-to-linevoltages during modulation index of 0.7. Similarly, whenmodulation index is increased to 0.8, the generated polevoltages in Fig. 9b show four levels (0, Vdc, 2Vdc, 3Vdc) andline-to-line voltages in Fig. 9c show seven levels (0, −Vdc,−2Vdc, −3Vdc, Vdc, 2Vdc, 3Vdc). The magnitude of theoutput voltage can be controlled by changing themodulation indexes. When higher voltage is required, themodulation index should increase beyond 0.35. Both themain stage and auxiliary stages contribute to the outputvoltage and load power.Figs. 10a and b show the simulation and the experimental

results of the input dc supply currents during MI = 0.8,respectively. It should be noticed that the average inputsupply current is always directed from the dc source to theload. Therefore the average power is always delivered to theload. Therefore the proposed topology can be used formodule integrated (ac modules) configuration of therenewable energy systems [27]. Another vital issue for


Fig. 10 Auxiliary and main cells dc sources current waveforms forMI = 0.8

a Simulation resultsb Experimental results

Table 1 Comparison between the proposed hybrid MLI topology and

Proposed hybridcascaded MLI topologyusing SVM

Cascaded HsymmetricSVPWM co

number of switching devices(three-phase)

18

phase-to-neutral voltagelevels

8

level/switch ratio 0.44number of isolated dcvoltage sources (three-phase)

7

THD (Ma = 0.8–0.9), % 8.7

Table 2 Comparison between the proposed hybrid MLI topology and

Proposed hybrid cascadedMLI topology using SVM

Hybrtopo

number of switching devices(three-phase)

18

phase-to-neutral voltage levels 8level/switch ratio 0.44number of isolated dc voltagesources (three-phase)

7

THD (Ma = 0.8–0.9), % 8.7

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inverters is the ratings of the semiconductor switches, sincethe current and voltage ratings of switches are responsiblefor the cost and efficiency. As the inverter main andauxiliary stages are connected in series, therefore themaximum current rating of any switch is equal to the loadpeak current. Moreover, the blocking voltage of any switchis equal to the input dc voltage of its stage circuit. Hence,the maximum blocking voltage is the main stage inputvoltage and which is equal to 2(k−1)Vdc.The simulation and experimental results are very similar to

each other, according to the number of voltage levels, voltageamplitude, voltage waveforms and output frequency. As themodulation indexes increase, the main stage switchingfrequency decreases and it reduces switching losses. Thisbehaviour indicates that the system efficiency increases athigher modulation index.Tables 1 and 2 compare the suggested system with respect

to other designs and control methods [28–31] for the samenumber of levels and the same number of switches,respectively. The comparison involves the number ofswitching devices, output voltage levels and THD. Theproposed topology has the highest LSR and better THDperformance during 0.8≤M≤ 0.9, in comparison with allthe other designs, except the reversed voltage (RV) MLItopology in [31], since it requires only three isolated dcsources. However, that shows the number of levels inphase-to-neutral voltage is ‘4’. Here, the value of LSR islower, since RV topology requires an additional three fullbridge inverter with total 12 switches. These indicate thatRV MLI topology requires of extra system components.

6 Conclusion

A new hybrid multilevel inverter topology using an SVMcontrol scheme is presented. The proposed MLI has variousadvantages in compare with existing MLI topologies. A

two other systems for nearly the same number of levels

-bridgeal optimisedntrol [27]

Cascaded MLI using power cells, PWMphase-shifted multicarrier modulationtechnique [29]

36 48

7 9

0.19 0.199 24

10.5 –

two other systems for the same number of switches

id multilevellogy, RV [30]

Hybrid three-level NPC arm plus half bridgedc shifter, selective harmonic elimination [28]

18 18

4 60.22 0.333 9

– 16.5


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lower number of power electronics components are required.That indicates a lower-system complexity, more reliability,lower cost and higher efficiency. The proposed topologycan be extended to higher stages without changing theprevious circuit configuration since it has modularcharacteristic. An SVM scheme has been applied for widerange of modulation indexes to control the proposed MLI.Mathematical and theoretical analyses are presented alongwith selected simulation results to support the theoreticalconsiderations. The proposed system simulation model andits control algorithm are developed using MATLAB/SIMULINK to validate the proposed hybrid MLI topology.Experimental results show the verification of the simulatedresults. It is found that the experimental results have a goodsimilarity with the simulation results.
7 Acknowledgement

The authors would like to thank the Ministry of HigherEducation and University of Malaya for providing thefinancial support under the research grant No. UM.C/HIR/MOHE/ENG/16001-00-D000017&UMRG project No.RP015A/13ET.

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issn 1755-4535 three-phase hybrid multilevel inverter … · the proposed mli consists of a reduced...

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