ISOLATED ZETA-SEPIC BIDIRECTIONAL DC-DC CONVERTER WITHACTIVE-CLAMPING

Adriano Ruseler, Ivo BarbiFederal University of Santa Catarina - UFSC, Power Electronics Institute - INEP

PO box 5119, ZIP code 88040-970, Florianópolis, SC, BRAZILruseler@inep.ufsc.br, ivobarbi@inep.ufsc.br

Abstract—This paper proposes an isolated bidirectional dc-dc converter, based on the duality between Zeta and SEPICconverters. Active-clamping is used to recycle the energy trappedin the transformer leakage inductance and to protect the powersemiconductors against over-voltages. Theoretical analysis, mo-dulation strategy and experimental results are included in thepaper. A laboratory prototype, rated at 1kW, with an inputvoltage of 100 V, an output voltage of 133 V and 50 kHz ofswitching frequency validates the predicted theoretical results.The proposed converter is suitable for several practical applica-tions such UPS, electric vehicle, energy storage end smart grids.

Keywords—Isolated, Zeta-SEPIC, bidirectional, dc-dc con-verter, active-clamping, step-up, step-down.

I. INTRODUCTION

Bidirectional dc-dc isolated step-up step-down converterscan be used in various applications. Bidirectional power flowis a key feature for storage systems and power distributionsystems. The converter is suitable for applications where gal-vanic isolation is required, otherwise the use of a transformerwould only increase cost, volume, and losses.

A. Overview of Isolated Bidirectional dc-dc Converter Appli-cations

Bidirectional dc-dc converters are increasingly used in ap-plications such as:• Uninterrupted Power Supplies (UPS) [1];• Electric Vehicle (EV) [2], [3];• Fuel Cell (FC) generation system [4], [5];• Storage System [6], [7];• Power distribution [8];• Photovoltaic [9];• Residential Microgrid System [10];

B. Overview of Isolated Bidirectional dc-dc Converter Topolo-gies

Bidirectional isolated dc-dc converters presented so far canbe summarized as:• Dual Half-Bridge (DHB) [11], [12];• Bidirectional Full-Bridge dc-dc converter [13], [14];• Bidirectional Cùk dc-dc converter [15], [16];• Forward Based bidirectional Converter [17];• Push-pull bidirectional power converter [18];• Bidirectional Flyback dc-dc converter [19], [20];• Full Bridge – Push-Pull Converter [21];• Integrated Full-Bridge-Forward dc-dc Converter [10];

Fig. 1. Nomenclature used to describe the dc-dc converter

• Forward-Flyback bidirectional dc-dc Converter [22];• Half-Bridge – Push-Pull dc-dc converter [23];• Bidirectional Current-Fed Flyback-Push-Pull [24];Active-clamping has already been applied to Zeta [25]

and SEPIC [26], [27] converters. A similar topology it waspublished by [28] with an unusual type of clamping using oneinductor and one bidirectional switch.

This work presents another solution using Buck-Boost typeof active-clamp [29] with a more simplified switching logic.

II. THE PROPOSED BIDIRECTIONAL ZETA-SEPICISOLATED DC-DC CONVERTER WITH ACTIVE-CLAMPING

A. Circuit Description

The circuit of the proposed dc-dc converter is presented inFig. 1. The magnetic link is made by coupled inductors [30]which splits the converter in two sides named here as Zeta sideand SEPIC side. Zeta side holds the switches of an equivalentunidirectional Zeta isolated converter with active clamping.The same is true for SEPIC side.

An auxiliary inductance Lc can be added to achieve ZVSin a wider range of operation.

Active-clamping cell is considered to be formed by the mainswitch, clamping switch and clamping capacitor and is appliedto both sides to handle leakage inductance energy.

B. Non-Isolated Equivalent Circuit

The circuit is referred to SEPIC side because of the numberof components. Fig. 2 illustrates the non-isolated versionof the converter. Each variable when referred to Zeta sidereceives an apostrophe, but when referred to SEPIC sidetwo apostrophes are assigned. The conversion between sidesrespect the transformer turns ratio: nzs =

√La′′

La′ .

978-1-4799-0272-9/13/$31.00 ©2013 IEEE 123

Fig. 2. Non-Isolated simplified circuit for the Zeta-SEPIC dc-dc bidirectionalconverter.

C. Modulation and dead times

The PWM signal for each switch are shown in Fig. 3. SwitchSa is used as reference and for this reason its duty cycle namedD. Switch Sb operates complementary to Sa, with active dutycycle 1−D and dead time of td(Sa→Sb) between Sa and Sb.Switch Sc operates complementary to Sa with an dead time oftd(Sb→Sc). Switch Sd operates complementary to Sb with andead time of td(Sa→Sd). Dead time is defined as the inactivetime between turning on one switch and turning off another:td(off→on).

The simplicity resides in using just one PWM signal asreference, all others can be obtained with complementary logicand dead-time delay.

The highlighted area in Fig. 3 corresponds to the stage thatrepresents loss in the converter duty cycle, with duration thatdepends on the converter parameters and operation point.

Fig. 3. PWM Modulation signal logic.

III. MAIN THEORETICAL WAVEFORMS

The circuit behavior of the proposed converter during oneswitching cycle of operation is divided into three main oper-ating stages or in eight sub-stages.

When the power flows from source V a to source V b theconverter operation establish itself on Zeta mode, otherwiseon Sepic mode.

Observing the current in inductance Ld′′ over one switchingfrequency period, each gradient change defines one particularmain stage. On the top of each figure, duty cycle times areillustrated. On the bottom, each sub-stage is properly assigned.

The proposed converter operates similarly to the SEPIC con-verter with active-clamping when operating in SEPIC mode,the same is true when in Zeta mode.

Fig. 4 shows the waveforms in Zeta mode.

Fig. 4. Main waveforms for the isolated Zeta-SEPIC dc-dc converter operatingin Zeta Mode.

For the converter operating in SEPIC mode, the mainwaveforms are presented in Fig. 5.

Fig. 5. Main waveforms for the isolated Zeta-SEPIC dc-dc converter operatingin SEPIC Mode.

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IV. MAIN TOPOLOGICAL STAGES AND PRINCIPLE OFOPERATION

The Zeta-SEPIC isolated converter have tree main topolog-ical states. Each stage is named according in what clampingcapacitor is active. When capacitor Cca is active, the converteris in stage Dz with duty cycle of Dz, otherwise when capacitorCcb is active, stage Ds takes place with duty cycle of Ds. Ifboth clamping capacitors are disabled, appears a third stageDp with duty cycle Dp.

A. Zeta-SEPIC main stagesMain equivalent circuit stages are shown in Fig. 6.1) Stage Dp: Clamping capacitors are disabled. The dura-

tion of this stage depends on the value of leakage inductance,load current, source voltage and switching frequency.

2) Stage Ds: SEPIC clamping capacitor is enabled. Theduration depends only on the converter duty cycle.

3) Stage Dz: Zeta clamping capacitor is enabled. Durationdepends on the complementary converter duty cycle.

Fig. 6. Stage Dp (a), Stage Ds (b) and Stage Dz (c) for the Zeta-SEPICBidirectional dc-dc converter.

B. Zeta-SEPIC sub-stages in Zeta modeThe sub-stages related to operation in Zeta mode are pre-

sented in Fig. 7. Sub-stages transition points are presented inTable I and them transition sequence respects Fig. 4.

Fig. 7. Sub-stage 1 Stage Dp (a), Sub-stage 2 Stage Dp (b), Sub-stage 3Stage Dp (c), Sub-stage 1 Stage Ds (d), Sub-stage 2 Stage Ds (e), Sub-stage1 Stage Dz (f), Sub-stage 2 Stage Dz (g) and Sub-stage 3 Stage Dz (h) for theisolated Zeta-SEPIC bidirectional dc-dc converter operating in Zeta mode.

TABLE ISUB-STAGES INTERVALS IN ZETA MODE

Name Begin End Restrictions

Sub1Dp Turn off Sc iLd′′ = 0 td(Sa→Sb) > tthis

Sub2Dp iLd′′ ≥ 0 iLd′′ = iLa′′ —Sub3Dp iLd′′ ≥ iLa iLd

′′ = iLa′′ + iLb —Sub1Ds iSb = 0 iCcb → 0 td(Sa→Sd) < tthisSub2Ds iCcb ≤ 0 Turn off Sa —Sub1Dz Turn off Sa iLd

′′ → iLa —Sub2Dz iLd

′′ ≤ iLa iLd′′ → 0 —

Sub3Dz iLd′′ = 0 Turn off Sc —

1) Sub-stage 1 stage Dp (Sub1Dp): Begins when switchSc turns off. Zeta clamping capacitor is disabled and stopssupplying energy. Ends when current iLd′′ reaches zero. Deadtime between main switches must be shorter than the durationof this sub-stage in order to maintain current through switchSa.

2) Sub-stage 2 stage Dp (Sub2Dp): Begins when currentiLd′′ reaches zero. Source V a supplies power. Ends whencurrent iLd′′ matches current iLa or when iCab reaches zeroand stops charging capacitor Cab.

3) Sub-stage 3 stage Dp (Sub3Dp): Begins when currentiLd′′ becomes greater than current iLa′′ or when iCab becomesnegative. Capacitor Cab delivers energy. Ends when currentiLd′′ becomes equal to current iLa′′ + iLb.

4) Sub-stage 1 stage Ds (Sub1Ds): Begins when currentiLd′′ becomes equal to current iLa′′ + iLb. Current iSb reacheszero, diode Dd conducts and SEPIC clamping capacitor startscharging. Ends when current iSd reaches zero.

5) Sub-stage 2 stage Ds (Sub2Ds): Begins when currentiSd becomes positive blocking diode Dd. SEPIC clampingcapacitor starts discharging. Ends when switch Sa is turnedoff.

6) Sub-stage 1 stage Dz (Sub1Dz): Begins when diodeDc is forward polarized by turning off Sa. Zeta clampingcapacitor starts charging. Ends when current iLd′′ becomesequal to current iLa′′ .

7) Sub-stage 2 stage Dz (Sub2Dz): Begins when currentiLd′′ becomes equal to current iLa′′ . Capacitor Cab startscharging. Ends when current iLd′′ equals to zero.

8) Sub-stage 3 stage Dz (Sub3Dz): Begins when currentiLd′′ reaches zero. Zeta clamping capacitor starts discharging.Ends when switch Sc turns off.

C. Zeta-SEPIC sub-stages in SEPIC mode

The sub-stages related to operation in SEPIC mode arepresented in Fig. 8. Sub-stages transition points are presentedin Table II and them transition sequence respects Fig. 5.

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Fig. 8. Sub-stage 1 Stage Ds (a), Sub-stage 2 Stage Ds (b), Sub-stage 3Stage Ds (c), Sub-stage 1 Stage Dp (d), Sub-stage 2 Stage Dp (e), Sub-stage3 Stage Dp (f), Sub-stage 1 Stage Dz (g) and Sub-stage 2 Stage Dz (h) for theisolated Zeta-SEPIC bidirectional dc-dc converter operating in SEPIC mode.

TABLE IISUB-STAGES INTERVALS IN SEPIC MODE

Name Begin End Restrictions

Sub1Ds Turn off Sb iCab → 0 —Sub2Ds iCab ≥ 0 iCcb → 0 —Sub3Ds iCcb ≤ 0 Turns off Sd —Sub1Dp Turn off Sd iSb → 0 td(Sa→Sb) < tthisSub2Dp iSb ≥ 0 iCab → 0 —Sub3Dp iCab ≤ 0 iLd′′ → 0 td(Sb→Sc) ≥ tthisSub1Dz iLd′′ = 0 iCca′′ → 0 —Sub2Dz iCca′′ ≤ 0 Turn off Sb —

1) Sub-stage 1 stage Ds (Sub1Ds): Begins when switchSb turns off commuting current through diode Dd chargingthe SEPIC clamping capacitor Ccb. Ends when current iCab

reaches zero.2) Sub-stage 2 stage Ds (Sub2Ds): Begins when current

iCab becomes positive setting capacitor Cab to store energy.Ends when current iCcb reaches zero.

3) Sub-stage 3 stage Ds (Sub3Ds): Begins when currentiLd′′ equals to current iLa′′ + iLb value. Diode Dd starts con-ducting and the previous stored energy from SEPIC clampingcapacitor is recovered. Ends when switch Sd is turned off.

4) Sub-stage 1 stage Dp (Sub1Dp): Begins when switch Sdis turned off. SEPIC clamping capacitor Ccb stops supplyingenergy. Ends when current iSb reaches zero.

5) Sub-stage 2 stage Dp (Sub2Dp): Begins when currentiSb becomes positive. Anti parallel diode from switch Sb isblocked. Ends when current iLd′′ equals to current iLa′′ .

6) Sub-stage 3 stage Dp (Sub3Dp): Begins when currentiLd′′ reaches iLa′′ setting Cab to deliver energy. Ends whencurrent iLd′′ equals to zero.

7) Sub-stage 1 stage Dz (Sub1Dz): Begins when currentiLd′′ changes direction loading energy in Zeta clamp. Endswhen current iCca′′ equals to zero. If td(Sb→Sc) is shorter

than the duration of this sub-stage, turning on Sc ends thissub-stage.

8) Sub-stage 2 stage Dz (Sub2Dz): Begins when current iSc

becomes positive delivering Zeta clamp stored energy. Endswhen switch Sc turns off.

V. STEADY STATE ANALYSIS

The affective duty cycle is defined in (1) regarding the Zetaand SEPIC static gain.

V b

V a′′=

Def

1−Def(1)

The relation between duty cycle of each stage can be definedas:

Dp+Ds+Dz = 1 (2)

The auxiliary commutation inductance is unconsidered inthis analysis, to consider, Ld′′ must be replaced with Ld′′ +Lc′′.

A. Operating in Zeta ModeFor the converter operating in Zeta mode the stage Dp duty

cycle can be evaluated in eq. (3).

Dp =2ILbLd

′′

V a′′Ts(3)

Stage Ds as duty cycle Ds evaluated by eq. (4).

Ds = Def

(1 + Ld′′(La′′+Lb)

La′′Lb

1 +DefLd′′(La′′+Lb)

La′′Lb

)(4)

Considering (5) the duty cycle Ds for stage Ds results inDs ∼= Def .

Ld′′(La′′ + Lb)

La′′Lb∼= 0 (5)

The effective duty cycle can be related to the converter dutycycle in eq. (6) and eq. (7).

Def = D − 2ILbLd′′

V a′′Ts(6)

D = Def +2ILbLd

′′

V a′′Ts(7)

B. Operating in SEPIC ModeFor the converter operating in SEPIC mode, the duty cycle

of stage Dp can be evaluated in eq. (8).

Dp =−2Ld′′ILa′′

V bTs(8)

The duty cycle for stage Ds is equal to the converter dutycycle.

Ds = D (9)

The duty cycle Dz can be evaluated in terms of the effectiveduty cycle.

Dz = 1−Def (10)

Table III summarizes all duty cycles for the converteroperating in Zeta and SEPIC modes.

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TABLE IIIDUTY CYCLE TIMES PER OPERATION MODE

Duty Cycle Zeta Mode SEPIC Mode

Dp 2Ld′′ILbV a′′Ts

− 2Ld′′ILa′′V bTs

Ds Def DDz 1−D 1−Def

D Def + 2Ld′′ILbV a′′Ts

Def +2Ld′′ILa′′

VbTs

VI. PROTOTYPE IMPLEMENTATION AND EXPERIMENTALRESULTS

A prototype was built in order to validate the analysis. Themain components specifications are shown in Table IV.

TABLE IVCOMPONENTS SPECIFICATION

Parameter Value Voltage Stress

LaVbVa′′Ts

(Va′′+Vb)∆iLa′′–

LbVbVa′′Ts

(Va′′+Vb)∆iLb–

Cab ILbDTs∆vCab

V b

Cca′′ILa′′DzTs

∆vCca′′V a′′

Dz

CcbILbDefTs

∆vCcb

V bDs

The voltage stress over switches are critical for a betterefficiency. Zeta clamping voltage in Zeta mode V a

1−D or inSEPIC mode V a

1−Defdepends on the converter complementary

duty cycle, higher converter duty cycle implies in highervoltage clamping. SEPIC clamping voltage in Zeta mode V b

Def

or in SEPIC mode V bD depends on the converter duty cycle,

lower converter duty cycle implies in higher voltage clamping.Prototype parameters are shown in Table V.

TABLE VPROTOTYPE PARAMETERS

Parameter Value Description

Po 1000 W Rated Powerfs 50 kHz Switching FrequencyV a 100 V Source Voltage (Zeta side)V b 133.3 V Source Voltage (SEPIC side)Ra 11.6 Ω Load Resistance (Zeta side)Rb 17.7 Ω Load Resistance (SEPIC side)Lm′ 284 µH Magnetization Inductance (Zeta side)Lm′′ 76.8 µH Magnetization Inductance (SEPIC side)Lb 233 µH Zeta InductanceLd′ 2.12 µH Leakage Inductance (Zeta side)Ld′′ 8.17 µH Leakage Inductance (SEPIC side)Lc 6.68 µH Commutation InductanceCab 28.6 µF Link CapacitanceCca 10 µF Clamping Capacitance (Zeta side)Ccb 10 µF Clamping Capacitance (SEPIC side)

Theoretical operation points can be found in Table VI.Fig. 9 shows the current in the active clamping cell and

clamping capacitor. Zeta clamping cell in Zeta mode andSEPIC clamping cell for SEPIC mode. The duality betweenthe operation modes can be verified.

TABLE VITHEORETICAL OPERATING POINTS VALUES

Parameter Zeta Mode SEPIC Mode

ILa′′ 5.634 A -5.001 AILb 7.50 A -8.18 AVCab 135.00 V 131.51 VVCca′′ 475.43 V 331.18 VVCcb 291.84 V 511.18 VD 0.5891 0.2568

Fig. 9. a) Current in commutation inductance and switching commands forinterrupters Sa and Sc in Zeta Mode. b) Current in commutation inductanceand switching commands for interrupters Sb and Sd in SEPIC Mode.

Fig. 10. a) Current in SEPIC clamping cell and capacitor Cab withswitching commands for interrupters Sa and Sc in Zeta Mode. b) Currentin Zeta clamping cell and current in Zeta clamping capacitor with switchingcommands for interrupters Sa and Sd for converter in SEPIC Mode.

Fig. 11. a) Current in Zeta clamping cell, current in Zeta clamp capacitor, Zetaand SEPIC clamping voltages in Zeta Mode. b) Current in SEPIC clampingcell, current and voltage in Zeta clamp capacitor in SEPIC Mode.

Fig. 10 shows the current in the active clamping cell andseries capacitor Cab current. SEPIC clamping cell in Zetamode and Zeta clamping cell for SEPIC mode. The RMScurrent value in capacitor Cab is high, a usual issue in Zetaand SEPIC based topologies.

Clamping voltages are shown in Fig. 11. As equations intable VI predicts, the clamping voltage is higher than sourcesvoltages leading to high switch voltage stresses.

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VII. CONCLUSION

From the theoretical analysis and the experimental data, wecan draw the following conclusions.

1) The measured performance of an example 1 kW dc-dcconverter agreed with theoretical predictions;

2) The features of the Zeta and SEPIC converters allowtheir employ in the design of isolated bidirectional dc-dc converters with performance similar or better than theprevious techniques;

3) The proposed topology is well adapted to active clamp-ing techniques, for the efficiency improvement;

4) The proposed converter is a possible solution for lowvoltage isolated dc-dc converters in many applications,such electric vehicles, UPS, energy storage systems,renewable power systems, etc.

ACKNOWLEDGMENT

The authors would like to thank the Brazilian agencyCAPES for the financial support, and Power Electronics Insti-tute (INEP), by the technical support.

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