ip core design - lecture 7 - introduction to...

IP Core Design

Lecture 7Introduction to SystemC

Juinn-Dar Huang, Ph.D.Assistant Professor

[email protected]

September 2004

Courtecy: Cadence Design, Inc.

Introduction to SystemC

Juinn-Dar H

uang jdhuang@m

ail.nctu.edu.tw

1copyright © 2004

Outlines

– SystemC applications– SystemC language– SystemC data types– SystemC processes– Simulation control

SystemC Applications


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uang jdhuang@m

ail.nctu.edu.tw

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Nature of SystemC

• SystemC is actually a C++ class library– enable H/W models at different levels of abstraction– support various development processes– focus on system-level design, modeling and verification

• Goal– provide a unified environment for architects, verification

engineers and implementation engineers


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Different Levels of Abstraction (1/3)Concept

Abstraction

Algorithm Selection/Performance Analysis

Architecture Selection/Finite Wordlength

Effects Analysis

Architecture MappingHW/SW Mapping

HW/RTL SW/C

SystemCSPW,

COSSAP

Matlab

HDL

C/C++

Not Easy


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uang jdhuang@m

ail.nctu.edu.tw

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Different Levels of Abstraction (2/3)


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Different Levels of Abstraction (3/3)

To be available in v3.x

Available in v2.x

Available in v1.x


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uang jdhuang@m

ail.nctu.edu.tw

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Heterogeneous Environment

Functional System Specification(HW, SW, environment) in C/C++

DigitalHW Block

DesignSW Block Design

AMSHW Block

Design

System Architecture

Het

erog

eneo

usM

ultil

evel

Ver

ifica

tion


Juinn-Dar H

uang jdhuang@m

ail.nctu.edu.tw

8copyright © 2004

What is SystemC?•Open source C++ class library and event-driven simulator

SystemC 1.0

RTL level of abstraction

Separates function from communication with concepts of ports, signals, data types

SystemC 3.0

Focus on software and scheduler modeling

SystemC 2.0

System Level modeling on top of 1.0

Addition of communication and synchronization in the form of channels, interfaces, and events

Oct 2001

SystemCVerificationStandard (SCV)

Transaction-based verification

Randomization

Constraint solver

Oct 2002Mar 2000


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uang jdhuang@m

ail.nctu.edu.tw

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SystemC 2.0 Language Architecture (1/2)

C++ Language Standard

Core LanguageModulesPortsProcessesEventsInterfacesChannelsEvent-driven Simulation Kernel

Data-Types

4-valued logic types (01zx)4-valued logic vectorsBits and bit-vectorsArbitrary-precision integersFixed-point numbersC++ user-defined types

Elementary ChannelsSignal, Timer, Mutex, Semaphore, FIFO, etc.

Standard Channels for Various Models of Computation (MOCs)Kahn Process NetworksStatic Dataflow, etc.

Methodology Specific Channels

Master/Slave Library, etc.


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uang jdhuang@m

ail.nctu.edu.tw

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SystemC 2.0 Language Architecture (2/2)

1.0

2.0

3.0


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SystemC’s Target


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SystemC Cannot Cover All


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SystemC’s Target Applications


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SystemC Does Not Try …

• SystemC is NOT– replacement of HDL and associated simulation tools

• especially gate-level modeling

– replacement of domain-specific tools• such as Matlab, COSSAP, SPW, …

– next generation HDL• SystemVerilog, Verilog-200X


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uang jdhuang@m

ail.nctu.edu.tw

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SystemC Simulation Environment


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SystemC Resources (1/2)– WWW resources

• The Open SystemC Initiative (OSCI)http://www.systemc.org/

– Books• System Design with SystemC

Kluwer Academic Publisher ISBN 1-402070721• SystemC: Methodologies and Applications

Kluwer Academic Publisher ISBN 1-402074794• A SystemC Primer

Star Galaxy Publishing ISBN 0-965039188

http://www.systemc.org/


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uang jdhuang@m

ail.nctu.edu.tw

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SystemC Resources (2/2)

• Documentations• SystemC Version 2.0 User’s Guide (update for 2.0.1)

UserGuide20.pdf• Functional Specification for SystemC 2.0 (update for SystemC 2.0.1)

FuncSpec20.pdf

• Examples• examples/systemc/ directory

simple_fifo, simple_perf, simple_bus, rsa, risc_cpu, pkt_switch, pipe, forkjoin, fir, fft…

SystemC Language


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uang jdhuang@m

ail.nctu.edu.tw

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Modules and HierarchyPort


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Processes


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Ports and Channels


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Example – Adder with Register (1/3)

+a

b

clk

Adder Register

temp c


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uang jdhuang@m

ail.nctu.edu.tw

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#include “systemc.h”

SC_MODULE(adder_reg) {// input portsc_in<sc_int<8> > a; sc_in<sc_int<8> > b; // output port sc_out<sc_int<9> > c; // clocksc_in<bool> clk;

// Internal signalsc_signal<sc_int<9> > temp;

// Adder processvoid prc_add();

// Register update processvoid prc_reg();

// ConstructorSC_CTOR(adder_reg) {SC_METHOD(prc_add);sensitive << a << b;SC_METHOD(prc_reg);sensitive_pos << clk;

}};

adder_reg.h


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uang jdhuang@m

ail.nctu.edu.tw

24copyright © 2004


#include “adder_reg.h”

// Adder processvoid adder_reg::prc_add() {temp = a + b;

}

// Register update processvoid adder_reg::prc_reg() {c = temp;

}

adder_reg.cpp


Juinn-Dar H

uang jdhuang@m

ail.nctu.edu.tw

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Hierarchical Coding (1/3)

// adder.h#include “systemc.h”

SC_MODULE(adder) {// input portsc_in<sc_int<8> > a; sc_in<sc_int<8> > b; // output port sc_out<sc_int<9> > c;

// Adder processvoid prc_add();

// ConstructorSC_CTOR(adder) {SC_METHOD(prc_add);sensitive << a << b;

}};

// adder.cpp#include “adder.h”// Adder processvoid adder::prc_add() {c = a + b;

}

Return to SC_METHOD


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uang jdhuang@m

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// reg.h#include “systemc.h”

SC_MODULE(reg) {// input portsc_in<sc_int<9> > in; // output port sc_out<sc_int<9> > out; // clocksc_in<bool> clk;

// Register update processvoid prc_reg();

// ConstructorSC_CTOR(reg) {SC_METHOD(prc_reg);sensitive_pos << clk;

}};

// reg.cpp#include “reg.h”// Register update processvoid reg::prc_reg() {out = in;

}


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uang jdhuang@m

ail.nctu.edu.tw

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#include “systemc.h”#include “adder.h”#include “reg.h”

SC_MODULE(adder_reg) {sc_in<sc_int<8> > a; sc_in<sc_int<8> > b; sc_out<sc_int<9> > c; sc_in<bool> clk;

// Instantiated objectsadder add1;reg reg1;

// Internal signalsc_signal<sc_int<9> > temp;// sc_signal is a SystemC// built-in channel

// ConstructorSC_CTOR(adder_reg): add1(“add1”), reg1(“reg1”){

// port bindingadd1(a, b, temp); // pos

reg1.in(temp); // namereg1.out(c); // namereg1.clk(clk); // name

}};

adder_reg.h

SystemC Data Types


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uang jdhuang@m

ail.nctu.edu.tw

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SystemC Data Types


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Bit Types


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Integer Types


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Impact on Simulation Performance

Faster

Native (built-in) C++ data typeNative (built-in) C++ data type

Fixed precision integer data typeFixed precision integer data type

Arbitrary precision integer data typeArbitrary precision integer data typesc_big(u)int<n>sc_big(u)int<n>

sc_bv<n>sc_bv<n>Slower

sc_lv<n>sc_lv<n>


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uang jdhuang@m

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SystemC Data Types

Type Description Remarkssc_bit 2 value single bitsc_logic 4 value single bitsc_int<n> n bit signed integersc_uint<n> n bit unsigned integersc_bigint<n> arbitrary sized signed integersc_biguint<n> arbitrary sized unsigned integersc__bv<n> arbitrary sized 2 value vectorsc_lv<n> arbitrary sized 4 value vectorsc_fixed<> templated signed fixed pointsc_ufixed<> templated unsigned fixed pointsc_fix untemplated signed fixed pointsc_ufix untemplated unsigned fixed point

O < n <= 512

0 < n <= 64

More com

plex

Faster

Processes


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uang jdhuang@m

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SystemC Processes

• Processes describe the functionality and allow concurrency

• Processes are not hierarchical– it’s illegal to call another process within a process

• Two kinds of processes– Method process: SC_METHOD– Thread process: SC_THREAD


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uang jdhuang@m

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SC_METHOD

• Execute from the head to the end at every activation of sensitized signals

• Return the control to the simulation kernel once the execution is completed

• Cannot call wait() in a SC_METHOD process

Example


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uang jdhuang@m

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SC_THREAD

• Similar to SC_METHOD– registration way, sensitivity list specification, …

• It usually call wait()• When the execution encounters a wait()

statement, the process is suspended• It resumes from the suspend only if the process

detects activations of sensitized signals• SC_THREAD simulates much slower than

SC_METHOD


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uang jdhuang@m

ail.nctu.edu.tw

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SC_THREAD ExampleSC_MODULE(tb) {// ...bool clk; // 50% duty cyclebool biased_clk;// H-H-L, 67% duty cuclevoid prc_clk_gen();// ...SC_CTOR(tb) {// ...SC_THREAD(prc_clk_gen);sensitive_pos << clk;

// ...}// ...

};

void tb::prc_clk_gen() {while(true){ // infinite loopbiased_clk = true;wait();biased_clk = true;wait();biasd_clk = false; wait();

}}

Simulation Control


Juinn-Dar H

uang jdhuang@m

ail.nctu.edu.tw

46copyright © 2004

Simulation Topmonitor u_mon(“u_mon”);u_mon(in1, in2, in3, out1);

sc_trace_file * tf =sc_create_vcd_trace_file(“a”);sc_trace(tf, out1, “out1”);

sc_start(100, SC_NS);// sc_start(-1); forever// sc_stop(); terminate

sc_close_vcd_trace_file(tf);

return 0;}

#include “systemc.h”#include “duv.h”#include “driver.h”#include “monitor.h”

int sc_main(int argc,char *argv[]) {

sc_signal<bool> in1, in2, in3,out1;

duv u_duv(“u_duv”);u_duv(in1, in2, in3, out1);

driver u_driver(“u_driver”);u_driver(in1, in2, in3);

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