ip core design - lecture 04 - reusable rtl coding...
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IP Core Design
Lecture 4Reusable RTL Coding Guidelines
Juinn-Dar Huang, Ph.D.Assistant Professor
September 2004
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
1copyright © 2004
Reusable RTL Coding Guidelines
• Readability• Simplicity• Locality• Portability• Reusability• Reconfigurability
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
2copyright © 2004
Naming Conventions
• Lowercase letters for signal names• Uppercase letters for constants• clk sub-string for clocks• rst sub-string for resets• Suffix
– _n for active-low, _z for tri-state, _a for async , …• [name]_cs for current state, [name]_ns for next
state• Identical(similar) names for connected signals and
ports• Consistency within group, division and corporation
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
3copyright © 2004
File Header (1/2)
• Should be included for all source files• Contents
– author information– revision history– purpose description– available parameters– reset scheme and clock domain– critical timing and asynchronous interface– test structures
• A corporation-wide standard template
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
4copyright © 2004
File Header (2/2)// +FHDR--------------------------------------------------------------------// Copyright (c) 2003, ABC Corporation.// ABC's Proprietary/Confidential// -------------------------------------------------------------------------// FILE NAME :// AUTHOR :// -------------------------------------------------------------------------// Revision History// VERSION Date AUTHOR DESCRIPTION// 1.0 6 Jan 2003 name// -------------------------------------------------------------------------// KEYWORDS : General file searching keywords, leave blank if none.// -------------------------------------------------------------------------// PURPOSE : Short description of functionality// -------------------------------------------------------------------------// PARAMETERS// PARAM_NAME RANGE : DESCRIPTION : DEFAULT// e.g., DATA_WIDTH_PP [32,16] : width of the data : 32// -------------------------------------------------------------------------// REUSE ISSUES// Reset Strategy :// Clock Domains :// Critical Timing :// Test Features :// Asynchronous I/F :// Scan Methodology :// Instantiations :// Other :// -FHDR--------------------------------------------------------------------
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
5copyright © 2004
Comments and Formats
• Appropriate comments– process (always block), function, …
• Comment end statements• A separate command per line• Coding in a tabular manner• Line length restriction
– a fixed number between 72-78• Indentation
– 2 spaces– avoid using tabs
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
6copyright © 2004
Ports
• Port ordering– one port per line with appropriate comments– inputs first then outputs– clocks, resets, enables, other controls, address bus,
then data bus– use comments
• Port mapping– Use named mapping instead of positional mapping
• foo u_foo1(4’h2, 4’h5, 4’h8); X• foo u_foo2(.a(4’h2), .b(4’h5), .c(4’h8)); O
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
7copyright © 2004
Coding Practices (1/2)
• Little-endian for multi-bit bus– [31:0] instead [0:31]
• Operand sizes should match– X reg[32:0] a; a = ’bz; // a is 33’b0zz…z in Verilog-1995
• Expression in condition must be a 1-bit value– if(abc != 16’h0) instead of if(abc)
• Use parentheses in complex statements• Do not assign signals don’t-care values
– avoid don’t-care propagation• Reset all storage elements
– avoid don’t-care propagation
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
8copyright © 2004
Coding Practices (2/2)
• Use function to model combo logic– do not repeat the same code
• Use local variables• Use loop judiciously
– improve readability– increase simulation and synthesis compilation time– use array equivalent whenever possible
• Use labels– help debugging always @(a or b or c)
begin: p_demo…end
foo u_foo(…); // single
foo u_foo1(…); // multiplefoo u_foo2(…);
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
9copyright © 2004
Coding for Portability
• Do not use HDL reserved words for naming– designs should be bilingual for automatic translation
• Do not use hard-coded numbers• Avoid embedded synthesis commands• Use technology-independent libraries
– avoid instantiating logic gates– DesignWare components
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
10copyright © 2004
Clocks and Resets
• Simple clocking is easier to understand, analyze, and maintain
• Avoid using both edges of the clock– duty-cycle sensitive– difficult DFT process
• Do not use clocks and resets as data• Avoid clock buffers (before APR)• Avoid gated clock (in RTL)
– see “Clock Gating” for low-power design• Avoid internally generated clocks and resets
– limited testability
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
11copyright © 2004
Clock Gating During Scan Shift
• Use SE as control point get better Fault Coverage• Latch GN stuck-at-0 fault is untestable
GN
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
12copyright © 2004
Coding for Synchronicity
• Infer technology-independent registers• Avoid using latches intentionally
– exception, “Half-Cycle Latch” in low-power design• Avoid using latches unintentionally
– incomplete assignment in case statement– incomplete if-then-else chain
• Avoid combinational feedback– STA and ATPG problem
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
13copyright © 2004
Combinational Blocks
• Combinational block– use blocking assignments– specify complete but no redundant sensitivity lists– assignment should be applied in topological order
always@(a or b or c)begin
x = a & b;y = x | c | d;
end// simulation-synthesis mismatch
always@(a or b or c or d or e)begin
x = a & b;y = x | c | d;
end// performance loss
always@(a or b or c or d)begin
y = x | c | d;x = a & b;
end // not in topological order// simulation-synthesis mismatch
always@(a or b or c or d)begin
x = a & b;y = x | c | d;
end// best final
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
14copyright © 2004
Sequential Blocks
• Sequential block– use non-blocking assignments– avoid race problems in simulation
• Comb./Seq. logic should be separated
always@(posedge clk)begin
b = a;a = b;
end // wrong style
always@(posedge clk)begin
b <= a;a <= b;
end // right style
reg rega b reg rega b
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
15copyright © 2004
if-then-else vs. case
• If-then-else often infers a cascaded encoder– inputs signals with different arrival time
• case infers a single-level mux– case is better if priority encoding is not required– case is generally simulated faster than if-then-else
• conditional assignment (? :)– infers a mux with slower simulation performance– better avoided
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
16copyright © 2004
casex vs. casez (1/2)
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
17copyright © 2004
casex vs. casez (2/2)
Without internal tri-state devices,casez is better than casex
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
18copyright © 2004
Coding for FSM
• Coding FSM– keep FSM and non-FSM logic separate– partition combinational part and sequential part
• two-always style (Mealy style)• three-always style (Moore style)
– use parameter to define names of the state vector– assign a default (reset) state
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
19copyright © 2004
Coding for Synthesis
• No # delay statements• Avoid full_case and parallel_case
– evil twin– pre-synthesis and post-synthesis simulation mismatch
• Avoid expressions in port connections– bad trace/debug capability– foo U_foo(.a(x&y^z), .b(m|n^p)); X
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
20copyright © 2004
Partition for Synthesis (1/3)
• Register all outputs– make output drive strengths and input delay predictable– ease time budgeting and constraints
• Group related combinational logic together– improve synthesis quality
• Separate modules with different synthesis goal• Avoid asynchronous logic
– technology dependent– more difficult to ensure correct functionality and timing– as small as possible and isolation
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
21copyright © 2004
Partition for Synthesis (2/3)
• Resource sharing– keep sharable resources in the same always block
• Partition for shorter synthesis runtime• Avoid timing exception
– point-to-point, false path, multi-cycle path• Eliminate glue logic at the top level
– better synthesis result and shorter synthesis timemodule top (...);...abc U_abc(.in(in), .out(out1));assign out1_n = ~out;def U_def(.in(out1_n), .out(out2));...endmodule // bad timing impact
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
22copyright © 2004
Partition for Synthesis (3/3)
• Chip-level partitioning– level 1 : I/O pad ring only– level 2 : clock generation, analog, RF, memory, JTAG– level 3 : digital core
ClockGeneration
TOP
JTAG
MIDDLE
CoreLogic
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
23copyright © 2004
Design with Memories
ComboLogic
WEDin
AddrDout
Sync.Memory
WEDin
AddrDoutCombo
Logic
Core Module I/F Module
Async.Memory
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
24copyright © 2004
Linter
• Fast static RTL code checker– preprocessor of the synthesizer– RTL purification
• syntax, semantics, simulation
– timing checks– testability checks– reusability checks
• Shorten design cycle by avoiding lengthy iterations
Reusable R
TL
Coding
Juinn-Dar H
uang jdhuang@m
ail.nctu.edu.tw
25copyright © 2004
More Guidelines
• RTL Coding Guidelines - RMM• Verilog HDL Coding - Motorola’s SRS
– http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=SRSSTANDARDS&nodeId=01
• IP Qualification Guidelines - Taiwan• Design Style Guide - STARC• Actel HDL Coding - Actel• FPGA Reuse Field Guide - Xilinx