ECE 485/585Microprocessor System Design

Lecture 3: Polling and InterruptsProgrammed I/O and DMA Interrupts Memory Hierarchy

Zeshan Chishti

Electrical and Computer Engineering Dept

Maseeh College of Engineering and Computer Science

Source: Lecture based on materials provided by Mark F.

ECE 485/585

I/O Subsystems – Things to Think About

What instructions does the processor use to communicate with I/O devices?

◼ Direct (Isolated) I/O

◼ Memory Mapped I/O

How do we know if an I/O device is ready or an I/O operation is complete

◼ Polling

◼ Interrupts

How do we transfer data between the I/O device and memory?

◼ Programmed I/O (PIO)

◼ Direct memory access (DMA)

Bus Mastering

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I/O Completion or Ready Notification

Two methods:

◼ Polled I/O

◼ Interrupt driven I/O

Polled I/O:

◼ Peripheral make status (ex: busy/ready for new I/O request) available through an I/O port or memory mapped register

◼ CPU executes a busy-wait loop reading the status from the peripheral and looping until peripheral is ready to accept a new I/O request (and/or has completed the current I/O request)

Interrupt driven I/O:

◼ Peripheral signals the CPU when it is ready for a new I/O request (and/or has completed the current I/O request)

◼ Program running on the CPU is “interrupted” and starts executing the code that handles the peripheral

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Simplified Polling Code Fragment

Microprocessor

Memory

I/O DeviceAddre

ss, D

ata

, Contro

l

READB: IN AL, BUSY ; get BUSY flag

TEST AL, BUSY_BIT ; test BUSY bit

JNE READB ; still busy -- loop

IN AL, DATAP ; read data

Polling

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Interrupt Driven I/O

Permits the processor to execute useful instructions instead of polling an I/O device

The I/O device interrupts the processor when it needs attention (e.g. has data) or an I/O operation has completed

◼ Keyboard character typed, mouse button clicked, etc.

◼ Requested disk block has actually been read (this takes eons in CPU cycle time)

◼ Timer “tick” expired

◼ Analog/Digital conversion complete…new measurement available

◼ System “wake-up” (power saving architectures)

…

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The Interrupt Mechanism

Hardware Interrupts (Asynchronous)

◼ Non-Maskable Interrupt(s) (NMI)

◼ Priority Maskable Interrupt(s) (INTR)

Software Interrupts (Synchronous)

◼ Nomenclature varies

Intel calls these “exceptions” to distinguish them fromH/W “interrupts”

Often called “traps” or “faults”

RISC architectures (ARM, MIPS, …) tend to name both hardware and software interrupts “exceptions” and handle them the same way

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Interrupt Hardware: Vectors

Intel8086

NMIINTR

INTA#

AD0-AD15

Non-maskable InterruptInterruptInterrupt Acknowledge

Type vector

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Interrupt Mechanism: Hardware Interrupts

Occur under external control (asynchronous)

◼ Can occur any time during instruction/program execution but may only be recognized at instruction boundaries

Non-Maskable Interrupts

◼ Ex: Power Failure

Enough time to save state and shutdown gracefully

Priority Maskable Interrupts

◼ I/O Devices Assigned Different Priorities

Relative importance of servicing request

◼ (e.g. keyboard or disk)

Ability of device to buffer data

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Interrupt Mechanism: Software Interrupts

Occur under CPU control (synchronous)

◼ Can occur when the CPU wants it to occur

May be the result of instruction execution

◼ Divide-by-Zero

◼ Page fault or segmentation violation

May be the result of instruction(s) inserted into the program that’s running

◼ Debugging (breakpoints and single step)

◼ Operating System Calls

User program makes O.S. request

INT # instruction

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x86 Interrupt Processing Sequence

Interrupt occurs

Push current processor state onto stack

◼ Flags (zero, carry, negative, …)

◼ CS:IP

Clear IF and TF (Interrupt and Trap Flags)

◼ Prevents further interrupts

Retrieve Instruction Pointer (CS:IP)

◼ Uses Interrupt Vector as index into Interrupt Descriptor Table (IDT)

Begin executing with new CS:IP of ISR

Service the interrupt (Interrupt Service Routine)

ISR ends by executing IRET instruction (explicit)

◼ Pops CS:IP and Flags from Stack

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START: MOV AX, CX ; comment

MOV CX, ICOUNT ; comment

.

Executing Code

Interrupt occurs

0

1

255

Interrupt Descriptor Table

CS:IP (PC) of ISRs

ISR: PUSH AX ; comment

PUSH BX

IN …

IRET

Interrupt Service Routine

CS:IP

Flags

Stack

Push Flags and CS:IP (PC) Clear IF and TF (interrupt/trap flag)

IDT[Vector x 4] to get new CS:IP

IRET pops stack and execution resumes where interrupted

Entry number, not address

1

2

3

4

x86 Interrupt Processing Sequence

ECE 485/585

I/O Subsystems – Things to Think About

What instructions does the processor use to communicate with I/O devices?

◼ Direct (Isolated) I/O

◼ Memory Mapped I/O

How do we know if an I/O device is ready or an I/O operation is complete

◼ Polling

◼ Interrupts

How do we transfer data between the I/O device and memory?

◼ Programmed I/O (PIO)

◼ Direct memory access (DMA)

Bus Mastering

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Data Transfer

Two methods:

◼ Programmed I/O

◼ DMA (Direct Memory Access)

Programmed I/O:

◼ All I/O operations go through the CPU

◼ Program running on CPU accesses device registers and moves data to/from peripheral and memory (and/or internal registers)

DMA:

◼ CPU sets up DMA hardware, tells the DMA hardware to start and then goes merrily on its way

◼ DMA hardware accesses peripherals and moves the data to/from memory w/o CPU interaction

◼ DMA hardware generates an interrupt when the I/O transaction is complete

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Programmed I/O

Microprocessor

Memory

I/O DeviceAddre

ss, D

ata

, Contro

l

CPU fetches/execute instructions to be executed to do the I/OCPU moves data from I/O device to processor and then to memory

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START: MOV BX, OFFSET BUFFER

MOV DX, FFF8H ; set up I/O port

MOV CX, COUNT ; set up byte count

READB: IN AL, DX ; read byte

MOV [BX], AL ; copy to buffer

INC BX ; increment pointer

LOOP READB ; decrement/test CX

Simplified I/O Read Code Fragment

Ex: Buffer transfer using Programmed I/O

Microprocessor

Memory

I/O DeviceAddre

ss, D

ata

, Contro

l

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Direct Memory Access (DMA)

Microprocessor

Memory

I/O DeviceAddre

ss, D

ata

, Contro

l

DMA Controller

Microprocessor

Memory

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DMA (Detail)

mP “floats” its bus interface pins

AEN

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Tying It All Together: Disk Read Example

Communicate w/ the Floppy Disk Controller (FDC)

◼ Write “Read Data” command to FDC

◼ Tell the FDC to start

Determine when operation is complete and/or has data ready

◼ Polling: Read the Status Register to find out when data is available and/or operation is complete

◼ Interrupt: Handle interrupt(s) from the FDC

Transfer data from FDC to memory

◼ Programmed I/O: CPU reads each byte of data and writes the byte to memory

◼ DMA: DMA controller moves data from FDC to memory w/o involving the CPU

Operation: Read a block of 512 bytes from a floppy disk

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Memory Hierarchy

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Memory Taxonomy

Read/Write Memory

Non-VolatileVolatile

Read Only

Random AccessNon-Random Access

SRAM

DRAM

Shift Register

FIFO

CAM

EPROME2PROMFlash

NANDNOR

NVRAM

Mask ROM

PROM

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Computer Memory Hierarchy

Control

Datapath

SecondaryStorage(Disk)

Processor

Reg

iste

rs

MainMemory(DRAM)

SecondLevelCache

(SRAM)

On

-Ch

ipC

ach

e

TertiaryStorage(Tape)

ThirdLevelCache

(SRAM)

ArchiveBackup

File SystemPaging

InstructionsData[Cached Files]

Cached DRAM

Intermediate results

From Hennessy & Patterson, Computer Architecture: A Quantitative Approach (4th edition)

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Register Files

General Purpose Registers

Usually have multiple ports◼ Support CPU architecture’s datapaths

◼ Ability to read two operands, write one

Operate at CPU speed

selaselbselc

dataa

datab datac

Register File

• For read operations, the register file is equivalent to a 2-D array of flip-flops with tri-state outputs

• For write operations, we add some additional circuitry to the basic cell

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Address Decoding

• Address decoder generates a one-hot

code (1-of-n code) from the address

• binary to unary

• The output is used for row selection

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Accessing Register Files

Read

◼ “Address following”

Change address

◼ Data from new address appears on output

Asynchronous

Write is synchronous

◼ If WE, input data is written to selected word on the clock edge

RegID

Dout

Din

WE

RegID X

R[X]

RegID Y

R[Y]

val

Clock

val

Clock

RegID

WE

Din

Dout

Register File

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A memory unit with two output ports is said to be dual ported

Two ways to implement a dual-ported register file

True ports: Single set of registers with duplicate data paths and access circuitry that enables two registers to be read at a time

Two copies: Use 2 memory blocks each containing one copy of the register file

◼ To read two registers, one register can be accessed from each file

◼ To write a register, data needs to be written to both the copies of that register

Multi-ported Register File

Input Data

Address A

Address B

Address C

Output Data

Register File

Register File

C C

A B