introduction to asic design - eng.auburn.edu
TRANSCRIPT
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Victor P. Nelson
ELEC 5250/6250 – CAD of Digital ICs
Introduction to ASIC Design
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Design & implementation of ASICs
Oops – Not these!
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Application-Specific Integrated Circuit (ASIC)• Developed for a specific application• Not “general purpose”
Cadence“Virtuoso”
Tool
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Progress of State of the ArtYear Integration Level # devices Function1938-46 Electromagnetic relays 11943-54 Vacuum tubes 11947-50 Transistor invented 11950-61 Discrete components 11961-66 SSI 10’s Flip-flop1966-71 MSI 100’s Counter1971-80 LSI 1,000’s uP1980-85 VLSI 100,000’s uC1985-90 ULSI* 1M uC*1990 GSI** 10M SoC2011 Intel Ten-Core Xeon 2.6G CPU2017 Nvidia GV100 Volta 21.1G GPU
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Moore’s Law (Gordon Moore – 1965)“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year … over the short term this rate can be expected to continue, if not to increase. … over the longer term, the rate of increase is a bit more uncertain … no reason to believe it will not remain nearly constant for at least 10 years … by 1975, #components per integrated circuit for minimum cost will be 65,000 I believe that such a large circuit can be built on a single wafer.”
Moore’s originalgraph
Cost
\co
mpo
nent
#components
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Moore’s Law Updated
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System-on-Chip (SoC) An ASIC that packages basic computing components into a single chip.
A SoC has most of the components to power a computer.
Picture source: http://thecustomizewindows.com/, http://www.adafruit.com/
Mother board of a PC System on a Chip
ARM cores
AMBA buses
Physical IPs
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Advantages of SoC Higher performance benefiting from:
Less propagation delay since internal wires are shorter; Less gate delay as internal transistors have lower electrical impedance;
Power efficiency benefiting from: Lower voltage required (typically < 2.0 volts) compared with external chip voltage
(typically >3.0 volts); Less capacitance;
Lighter footprint: Device size and weight is reduced;
Higher reliability: All encapsulated in a single chip package, less interference from the external world;
Low cost: Cost per unit is reduced since a single chip design can be fabricated in a large volumes.
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Limitations of SoC Less flexibility
Unlike a PC or a laptop, which allows you to upgrade a single component, such as RAM or graphic card, a SoC cannot be easily upgraded after manufacture;
Application Specific
Most SoCs are specified to particular applications thus they are not easily adapted to other applications.
Complexity
A SoC design usually requires advanced skills compared with board-level development.
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ARM-based SoC An basic ARM-based SoC usually consists of
An ARM processor, such as Cortex-M0;
Advanced Microcontroller Bus Architecture (AMBA), e.g. AMBA3 or AMBA4;
Physical IPs (or peripherals) from ARM or third parties;
Additionally, some SoCs may have a more advanced architecture, such as multi-bus system with bus bridge, DMA engine, clock and power management, etc…
SystemControl ROM Boot
ROM RAM ROMTable
AHBPeripheral
APBPeripheral
UART
Timers
Watchdog
APB
Bus
DMA
Mux
Low latency AHB IOP
ARM AMBA 3 AHB-Lite System Bus AHB to APBBus bridge
ClockGenerator
PowerManagement Unit
JTAG/ Serial wire
RAM UART VGA GPIO Timer 7-segmentDisplay
ARM Cortex-M0Microprocessor
ARM AMBA 3 AHB-Lite System Bus
An example of ARM-based SoC
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Apple “A8” SoC (System on Chip) Used in iPhone6 & iPhone6 Plus Manufactured by TSMC
20nm, 89mm2, 2B transistors Elements (unofficial):
2 x ARM Cyclone ARMv8 64-bit cores running at 1.4GHz
IMG PowerVR 4-core GX6450 GPU L1/L2/L3 SRAM caches
Other devices 1 GB LPDDR3 SDRAM 16 to 128GB flash Qualcomm MDM9625M LTE modem M8 motion coprocessor (ARM Cortex M3 uC) iSight camera Near field communications chip (for Apple Pay) User interface and sensors, accelerometers, gyro Wi-Fi and Bluetooth
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SoC Example: Apple SoC Families
Source:http://en.wikipedia.org/wiki/Apple_(system_on_chip), as of 6/2017
SoC Model No. CPU CPU ISA Technology Die size Date Devices
N/A APL0098 ARM11 ARMv6 90 nm N/A 6/2007 iPhoneiPod Touch (1st gen.)
A4 APL0398 ARM Cortex-A8 ARMv7 45 nm 53.29 mm2 3/2010 iPad, iPhone 4, Apple TV (2nd gen.)
A5 APL0498 ARM Cortex-A9 ARMv7 45 nm 122.6 mm2 3/2011 iPad 2, iPhone 4S
APL2498 ARM Cortex-A9 ARMv7 32 nm 71.1 mm2 3/2012 Apple TV (3rd gen.)
APL7498 ARM Cortex-A9 ARMv7 32 nm 37.8 mm2 3/2013 AppleTV 3
A5X APL5498 ARM Cortex-A9 ARMv7 45 nm 162.94 mm2 3/2012 iPad (3rd gen.)
A6 APL0598 Swift ARMv7s 32 nm 96.71 mm2 9/2012 iPhone 5
A6X APL5598 Swift ARMv7s 32 nm 123 mm2 10/2012 iPad (4th gen)
A7 APL0698 Cyclone ARMv8-A(64-bit)
28 nm 102 mm2 9/2013 iPhone 5S, iPad mini (2nd gen)
APL5698 Cyclone ARMv8-A 28 nm 102 mm2 10/2013 iPad Air
A8 APL1011 Typhoon (dual-core) ARMv8-A 20 nm 89 mm2 9/2014 iPhone 6, iPhone 6 plus
A8X APL1012 Typhoon (triple-core) ARMv8-A 20nm 128 mm2 10/2014 iPad Air 2
A9 APL0898APL1022
Twister (dual-core) ARMv8-A 14nm FinFET16nm FinFET
96 mm2
104.5 mm29/2015 iPhone 6S, 6S Plus
iPad (2017)
A9X APL1021 Twister (dual-core) ARMv8-A 16nm FinFET 143.9 mm2 11/2015 iPad Pro (12.9”. 9.7”)
A10 APL1W24 Hurricane (quad-core) ARMv8-A 16nm FinFET 125 mm2 9/2016 iPhone 7, 7 Plus
A10X APL1071 Hurricane (hex-core) ARMv8-A 10nm FinFET 96.4 mm2 6/2017 iPad Pro (10.5”, 12.9”)
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T.I .smartphone reference design
MainSoC
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SoC Example: NVIDIA Tegra 2
Designer NVIDIA
Year 2010
Processor ARM Cortex-A9 (dual-core)
Frequency Up to 1.2 GHz
Memory 1 GB 667 MHz LP-DDR2
Graphics ULP GeForce
Process 40 nm
Package 12 x12 mm (Package on Package)
Used in tablets Acer Iconia Tab A500Asus Eee Pad TransformerMotorola XoomMotorola Xoom Family EditionSamsung Galaxy Tab 10.1Toshiba Thrive
Picture source: http://www.anandtech.com/, http://www.nvidia.com/
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Automotive
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Mobility
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SoCs/ASICs for Internet of Things (IoT)Why Now? ASICs are becoming:
Cheaper (<50c) Smaller (<1mm2) Lower power (µW) Commoditised HW & SW
Communication is growing faster (broadband)
Socio-economic benefits Globalisation Automation & control Mobility Smart monitoring Wide range of applications
Fitness / Healthcare
Portable andWearable
Electronics
SmartLighting
Safer/Smarter Automotive
Industrial InternetMachine to Machine
Smart Appliances
Smart Home
ResourceManagement
Smart Farming
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“IoT Things”Basic Building Functional Blocks
Sense ControlCompute CommunicateStore
M
Integrate into one ASIC/SoC
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Concentric Circles Represent Abstraction LevelsLarger Circles Greater Abstraction
The three axes represents the three domains
The taxonomy of VLSI design spaceWe model and simulate at each level of abstraction and/or mixtures of elements at different abstraction.
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DesignHierarchy/Abstraction
Design abstraction:• System (CPUs, I/O, memory)• Behavior/algorithm (HDL)• Register transfer• Logic Gate (net list)• Circuit (transistor)• Mask/layout (physical design)
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ASIC Design FlowSource: CMOS IC Layout, Dan Clein
Std Cell ASIC Full Custom IC
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ASIC/SoC Technologies
Full custom IC design Cell-based IC (our course)Mask-programmable gate array Platform/structured ASIC Field-programmable gate array (FPGA) Complex programmable logic device (CPLD) Software-programmable device Commercial off the shelf (COTS) device
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Cell-Based IC
(including IP)
8-week lead time(must fabricate all layers)
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Cell-Based Block Build design with predesigned & characterized “cells” Customize placement and interconnect (cells placed into fixed-height rows)
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Standard Cell
Fixed pitch:VDD-to-GND
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Masked Gate ArrayMap design onto gates in the arrayGates designed, characterized, pre-fabricatedCustomize placement and interconnect Fabricate only top-most interconnects
Cell library may contain “macros”/IPPatterns of gates/functionsSoft vs. hard macros
Lead time = few days to 2 weeks
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Gate array structures
Route in spaces between rows of gates
Channeled gate array
Route over gates
Sea of gates (channel-less)
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Structured/Embedded Gate Array• Market position between gate array and cell-based ASIC• Embedded blocks (CPU, memory) + programmable
gate arrays• Fab creates masks for top metal layers only
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Structured ASIC Approach(NEC Electronics America)
(Electronic Design Supplement – July 20, 2006)
Metal layers customized for the design
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Faraday - Profile of 1P7M Structured ASIC (www.faraday-tech.com)
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Faraday platform ASIC exampleswww.faraday-tech.com
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Faraday TEMPLATE platform ASICwww.faraday-tech.com
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Faraday TEMPLATE structured ASICswww.faraday-tech.com
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LSI Logic “CoreWare” IP Solution(www.RapidChip.com)
Designing with pre-integrated systems of IP(Electronic Design Supplement – Sep. 6, 2004)
Customer’s logic
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Programmable Logic Devices FPGA: array of gates & interconnects CPLD: based on AND/OR array
No custom circuitry to be fabricatedUser programs logic/interconnects ROM-EPROM-EEROM-RAM basedDesign turnaround time in hours
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Field-Programmable Gate ArrayProgram logic cells, I/O pads & interconnects
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Programmable Logic Device Die
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Xilinx Zynq SoC devices
FPGAs39
Zynq-7000 SoC: Dual-core ARM Cortex-A9 MPCore (up to 1GHz)Zynq UltraScale+ MPSoC:
• Quad-core ARM Cortex-A53 MP (up to 1.5 GHz)• Dual-core ARM Cortex-R5 MPCore (up to 600MHz)• GPY ARM Mali-400 MP2 (up to 667MHz)
PL =ProgrammableLogic
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FPGA Evolution FPGA Transistor count Date Manufacturer Virtex ~70,000,000 1997 Xilinx Virtex-E ~200,000,000 1998 Xilinx Virtex-II ~350,000,000 2000 Xilinx Virtex-II PRO ~430,000,000 2002 Xilinx Virtex-4 1,000,000,000 2004 Xilinx Virtex-5 1,100,000,000 2006 Xilinx Stratix IV 2,500,000,000 2008 Altera Virtex-7 6,800,000,000 2012 Xilinx Virtex-Ultrascale 21,000,000,000 2015 Xilinx
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Comparing Implementation Styles
SystemDesign
Auto Masks &Prototyping
SystemDesign Layout Masks &
Prototyping
routing
Testprogram
processing
Testprogram
processing
SystemDesign
Auto Masks &Proto...routing
Testprogram
processing
SystemDesign
Auto Prod.Quantityrouting
2-50 wks 8-10 wks 8-10 wks
8-10 wks8-10 wks1-2 wks
1-2 wks 1-2 wks 2-3 wks
1-2 wks
Interface tofoundary house.
FullCustom
Std. Cell
Gate Array
Field Programmable Gate Array.
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VLSI Implementations
Custom Standard cell Gate array FPGA
Density Highest Medium Low Lowest
Performance Highest Medium Low Lowest
Design time Long Medium Short Shortest
Chip Dev cost High Medium Low Lowest
Testability Difficult Less difficult Easy Easy
High Volume? High Medium Low Lowest