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ASIC 120: Digital Systems and Standard-Cell ASIC Design

Tutorial 2: Introduction to VHDL

February 1, 2006

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Outline

• State Machines

• HDL design flow

• Format of a VHDL file

• Combinational statements– assignments, conditionals, when … else

• Sequential statements– processes, if … then … else

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Summary of Previous Tutorial

• Digital Systems

• Combinational Logic– NOT, AND, OR, XOR, NAND, etc.– mux, half-adder, full-adder

• Sequential Logic– flip-flop/register, shift register, counter

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Recall: Sequential Circuits

• Sequential– computation involves a

feedback loop (memory)

• Example: ring counter

In Out

Combinational

Input Output

Feedback

Clk

DFF

D Q

S C

Init

DFF

D Q

S C

DFF

D Q

S C

DFF

D Q

S C

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State Machines

• We actually mean a Finite State Machine (FSM)– models behaviour

• Components relevant to digital design– states– transitions– inputs– outputs

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State Machines

• Represented as a state diagram

S0

S1

S3

1/0

S2

0/0

1/1

0/1

1/1

1/00/1

0/0

State

Transition

Output

Input

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State Machines• Or as a state table Present

StateInput

A

Next State

Output

X

S0 0 S0 0

S0 1 S1 0

S1 0 S3 1

S1 1 S2 1

S2 0 S3 1

S2 1 S2 1

S3 0 S1 0

S3 1 S0 0

Input AOutput X

S0

S1

S3

1/0

S2

0/0

1/1

0/1

1/1

1/00/1

0/0

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State Machines• Encode states into

binary Present State

Input

A

Next State

Output

X

00 0 00 0

00 1 01 0

01 0 11 1

01 1 10 1

10 0 11 1

10 1 10 1

11 0 01 0

11 1 00 0

Input AOutput X

00

01

11

1/0

10

0/0

1/1

0/1

1/1

1/00/1

0/0

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State Machines

• Some things to note– we assigned S0 = 00, S1 = 01, etc., but

state/bit mapping can be completely arbitrary– output is occurring on the transitions, this is

called a Mealy state machine– where the output is dependent only on the

current state, it is called a Moore machine

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State Machines• Remodelled as a Moore

state machine Present State

Input

A

Next State

Output

X

00 0 00 0

00 1 01 0

01 0 11 1

01 1 10 1

10 0 11 1

10 1 10 1

11 0 01 0

11 1 00 0

Input A

Output X

00(0)

01(0)

11(1)

1

10(1)

0

1

10

0

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State Machines

• This example is rather contrived– only dealing with abstract “states”, but

imagine application to automatic door, traffic lights, etc.

– Moore and Mealy machine looked the same• but they won’t always

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State Machines

00(0)

01(0)

11(1)

1

10(1)

0

1

10

000

01

11

1/0

10

0/0

1/1

0/1

1/1

1/00/1

0/0

Moore Mealy

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State Machines: Moore vs. Mealy

• Mealy can often be represented using less states– transitions can produce different output

• Even with more states, Moore often creates less hardware– less combinational logic– on an FPGA, registers (D flip-flops) are “free”

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State Machines in Digital Hardware

• This state machine requires two registers (D flip-flops), since there are four states

• Basic procedure:1) create state table2) derive FF input equations (and output

equations) from next state column with respect to present state and inputs

3) simplify equations4) draw hardware

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State Machines in Digital HardwareLet the two state bits (registers) be G and H

– we also have input A

G = GHA + GHA + GHA + GHA

H = GHA + GHA + GHA + GHA

X = G H

Present State

A Next State

X

G H G H

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 1 1

0 1 1 1 0 1

1 0 0 1 1 1

1 0 1 1 0 1

1 1 0 0 1 0

1 1 1 0 0 0

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State Machines in Digital HardwareSimplify the equations

G = G H

H = GHA + A

X = G H

Present State

A Next State

X

G H G H

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 1 1

0 1 1 1 0 1

1 0 0 1 1 1

1 0 1 1 0 1

1 1 0 0 1 0

1 1 1 0 0 0

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State Machines in Digital HardwareDraw the hardware

G = G H

H = GHA + A

X = G H

DFF

D Q

DFF

D Q

G H

A

A

X

Clk

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State Machines in Digital Hardware

• I’ve skipped many details and nuances– see ECE 223 course notes

• State machines can get very complicated– often don’t work out states in this detail– let synthesis tools do it

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Optimization of State Machines

• Outside the scope of this tutorial

• Summary– reduce number of states by combining states,

while preserving equivalent functionality– bit encoding can affect the size of the circuitry

generated to implement it

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Ring Counter

• Is this a state machine?Yes: every sequential circuit is a state machine

Clk

DFF

D Q

S C

Init

DFF

D Q

S C

DFF

D Q

S C

DFF

D Q

S C

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Back to Register Transfer Level (RTL) Logic

Register Register

Clock

Cloudof Logic

RegisterCloudof Logic

DataIn

DataOut

Feedback

Combinational

Sequential

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Hardware Description Languages (HDLs)

• HDLs describes in text a digital circuit

• Examples– VHDL (we will look at this next time)– Verilog– AHDL– JHDL

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Hardware Description Languages (HDLs)

• schematics are useful for…– drawing high level diagrams– manually working out simple pieces of logic

• HDLs are useful for…– describing complex digital systems

• HDLs are not...– software programming languages (C, Java,

assembly, etc.)

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Think Digital

• When designing a digital system in VHDL, it is important to remember the relation between code constructs and actual hardware

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HDL Design Flow1. Concept, requirements analysis2. High level design3. Functional implementation (need not be synthesizable)4. Functional simulation (3 -> 4 until functionality is good)5. Synthesizable implementation6. Synthesizable simulation (6 -> 5 until functionality is good)7. Timing simulation (7 -> 5 until timing is good; this step I often

bypassed in practice)8. Synthesis

• design is compiled to hardware• we will cover this in more detail later• 8 -> 5 if design doesn’t compile or doesn’t fit

9. Testing in hardware (9 -> 5 if something is wrong)

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What does “synthesizable” mean?

• Synthesizable means that a given design can be compiled into hardware– FPGA (reprogrammable ASIC)– ASIC

• A non-synthesizable design can be simulated in software and is useful for– working out functionality– testing out concepts– test benches (covered in detail later)

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Levels of Abstraction

• Behavioural

• Dataflow

• Structural

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Components of a VHDL File

• library– ieee, etc.

• use• entity

– defines the interface

• architecture– defines the functionality

• component– reusable functionality

• multiple entity/architectures in one file

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Why do we use IEEE libraries?

• standard VHDL libraries are limited to two values: 0 and 1

• this is fine for theory, but in practice a physical wire can have other values

• more on this in later tutorials

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Inputs and Outputs

• declared in the entity

• the “pins” of the hardware block

• can only be input, output, or I/O

• output pins cannot be read from– for example, if I assign a value to an output

pin I cannot “read” that value back in another place

– output pins are like black holes in this way

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Signals

• Signals are the internal “wires” of your design

• Can be assigned a value, or have their value read

• Signals can be read in multiple places, but assigned in only one place– “cannot have multiple output pins driving a

wire”

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Buses

• Provide an easy way to group multiple signals or ports

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Combinational Logic

• In VHDL: “Concurrent Statements”

• Remember: all functionality is defined within architecture block

• Order doesn’t matter

• Types of concurrent statements– assignments– conditional assignments– processes

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Combinational Assignments

destination <= source_logic;

examples:

X <= A AND B;

Y <= NOT (A AND B);

Z <= A XOR B AND C NOT B;

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Conditional Assignments

destination <= source_logic_1 when condition_1

else source_logic_2 when condition_2

else source_logic_3;

example:

X <= A AND B when Sel = “00”

else NOT (A AND B) when Sel = “01”

else A XOR B when Sel(0) & Sel(1) = “10”

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Conditional Assignment: A MUX

• Conditional assignments are modelled physically as a multiplexer

00

01

10

11

X <= A AND B when Sel = “00”else NOT (A AND B) when Sel = “01”else A XOR B when Sel(0) & Sel(1) = “10”

Sel(0) Sel(1)

Sel

AB

AB

X

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Brackets and The & Operator

• Brackets– used to reference parts of buses

• & Operator– signal concatenation operator– used for constructing buses out of single wire

signals, or parts of other buses

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Processes

• Contain chunks of VHDL code

• Can be purely combinational

• Most useful for sequential logic– controlled by a clock

• processes are executed in parallel, in any order

• Processes can optionally be named

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Process Statement

[process_name:] process (sensitivity_list)

    declarations

begin

    sequential_statements

end process;

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Sequential Logic

• In VHDL: “Sequential Statements”

• Within a process, statements execute sequentially– important to remember that logic is tied back

to underlying hardware

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If … Then …Else Statement

• Like the concurrent “when … else” statement, modelled as a multiplexer

    if first_condition then        statements    elsif second_condition then       statements    else       statements    end if;

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MUX with an If Statement

    process(Sel, A, B, C, D)    begin        if Sel = "00" then            Y <= A;        elsif Sel = "01" then            Y <= B;        elsif Sel = "10" then            Y <= C;        elsif Sel = "11" then            Y <= D;        end if;    end process;

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MUX with an If Statement

• Note that this mux is a combinational mux– i.e., not governed by a clock

A

B

C

D

00

01

10

11

Sel(0) Sel(1)

Y

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Clocked Processes• Or: “Sequential Processes”• Consider a “clocked mux”:    process    begin wait until rising_edge(Clk);        if Sel = "00" then            Y <= A;        elsif Sel = "01" then            Y <= B;        elsif Sel = "10" then            Y <= C;        elsif then            Y <= D;        end if;    end process;

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Clocked Processes• Or: “Sequential Processes”• Consider a “clocked mux”:    process    begin wait until rising_edge(Clk);        if Sel = "00" then            Y <= A;        elsif Sel = "01" then            Y <= B;        elsif Sel = "10" then            Y <= C;        elsif then            Y <= D;        end if;    end process;

A

B

C

D

00

01

10

11

Sel(0) Sel(1)

Y

DFF

D Q

Clk

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Clocked Processes

• Statements are essentially executed in series

• Important to always keep in mind underlying hardware

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Clocked Processes• Consider:    process    begin wait until rising_edge(Clk);

        if Sel = ‘0’ then            Y <= A; else            Y <= B;        end if;

        if Sel = ‘0’ then            Z <= B; else            Z <= A;        end if;    end process;

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Clocked Processes• Consider:    process    begin wait until rising_edge(Clk);

        if Sel = ‘0’ then            Y <= A; else            Y <= B;        end if;

        if Sel = ‘0’ then            Z <= B; else            Z <= A;        end if;    end process;

A

B

0

1

Sel

Y

DFF

D Q

Clk

B

A

0

1

Sel

Z

DFF

D Q

Clk

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Clocked Processes• This code produces the same hardware:    process    begin wait until rising_edge(Clk);

        if Sel = ‘0’ then            Y <= A; Z <= B; else            Y <= B;            Z <= A;        end if;    end process;

A

B

0

1

Sel

Y

DFF

D Q

Clk

B

A

0

1

Sel

Z

DFF

D Q

Clk

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Remember

• Always consider the underlying hardware!– ask yourself: what does the VHDL code I’m

writing actually represent?

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Preview of Next Tutorial

• Intermediate VHDL– sequential statements continued

• more on registers, case, loops

– latch inference– loops– other signal values besides ‘0’ and ‘1’– more VHDL data types– attributes, type definitions

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Summary

• State Machines

• HDL design flow

• Format of a VHDL file

• Combinational statements– assignments, conditionals, when … else

• Sequential statements– processes, if … then … else

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UW ASIC Design Team

• www.asic.uwaterloo.ca• reference material

– Prof. Hamel’s Winter 2005 ECE 223 course noteshttp://www.ece.uwaterloo.ca/~ece223/jhamel/

– Accolade VHDL reference (excellent!):http://www.acc-eda.com/vhdlref/

– Bryce Leung’s tutorials (UW ASIC website)– Mike Goldsmith’s tutorials (UW ASIC website)– your course notes

• my contact info:Jeff Wentworth, j.wentworth@gmail.com