Introducing theIntroducing the

Nexys 2Nexys 2BoardBoard

CS 332 – Operating SystemsCS 332 – Operating Systems 12/04/201112/04/2011 by Otto Castell-Rby Otto Castell-R

FPGAFPGA

FPGA – Field Programmable Gate ArrayFPGA – Field Programmable Gate Array Integrated Circuit which can be configured by the userIntegrated Circuit which can be configured by the user

Configuration is done using HDL (Hardware Configuration is done using HDL (Hardware Description Language)Description Language)

FPGA's can be programmed to implement any logic FPGA's can be programmed to implement any logic functionfunction

User designs the logic circuits using AND , OR and User designs the logic circuits using AND , OR and NOT Logic Gates, which the circuit board translates NOT Logic Gates, which the circuit board translates into universal gates (NAND, NOR)into universal gates (NAND, NOR)

FPGAFPGA > > Nexys 2Nexys 2

Logic GatesLogic Gates

A logic gate is a physical model of a Boolean function and A logic gate is a physical model of a Boolean function and exists as:exists as:

Elementary GateElementary Gate Universal GateUniversal Gate

Logic Gates – Half AdderLogic Gates – Half Adder

Logic Gates – Half Adder > SHDLLogic Gates – Half Adder > SHDL

module half_adder (a, b : s, r)module half_adder (a, b : s, r)s = /a*b+a*/b ;s = /a*b+a*/b ;r = a*b ;r = a*b ;

end moduleend module

Logic Gates – Half Adder > SHDLLogic Gates – Half Adder > SHDL

library IEEE;library IEEE;library UNISIM;library UNISIM;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_adder isentity half_adder isport (port (

a : in std_logic ;a : in std_logic ;b : in std_logic ;b : in std_logic ;s : out std_logic ;s : out std_logic ;r : out std_logicr : out std_logic

););end half_adder;end half_adder;

architecture synthesis of half_adder isarchitecture synthesis of half_adder is

beginbegin

-- concurrent statements-- concurrent statementss <= ((not a) and b) or (a and (not b)) ;s <= ((not a) and b) or (a and (not b)) ;r <= a and b ;r <= a and b ;

end synthesis;end synthesis;

Logic Gates – Full AdderLogic Gates – Full Adder