international journal of applied engineering research issn ......the delay time in the comparator is...

ANALYSIS AND COMPARISION OF HIGH PERFORMANCE

COMPARATOR USING DIFFERENT TECHNOLOGIES FOR ADC

APPLICATIONS

S.Kiruthiga

Assistant professor, ECE Sri Krishna College of Technology,

Coimbatore

A.Shobana

Student, ECE Sri Krishna College of Technology

Coimbatore

A.S.Sneha


Coimbatore

R.Sukesh


Coimbatore

Abstract— Growing demand for portable device with light

weight and small size leads to low voltage circuits. This

provides us to design a system with small battery and light

weight. So the use of comparator with high performance and

low power consumption in ADC’s is necessary. This is

pushing towards the use of dynamic regenerative comparator

to maximize speed and power efficiency. It is getting difficult

to design high speed comparator with smaller supply voltage

due to large transistor usage that results in increasing delay

and power consumption. In this paper delay and power

analysis of double tail comparator will be presented.

Conventional two stage comparator is modified into double

tail design for consuming low power and high speed even

when supply voltage is small. Without complicating the design

few switching transistors are added to reduce power

dissipation. Regeneration is strengthened during positive

feedback that reduces the delay time remarkably. Comparision

of parameter on different technologies are analyzed with the

results and the one with better performance were suggested.

Keywords— ADC’s , double tail comparator, two stage comparator, tanner EDA.

INTRODUCTION

Now a days there exists a growing demand for portable

devices with light weight and small size. This leads to low

voltage circuits in which the circuits has design system with

small batteries and light weight. Comparator is the basic

building block in analog to digital converters. Such

comparators needs to be faster and less power should be

consumed.

A two stage dynamic comparator is proposed in [1], a pre

amplifier and latch stage are controlled by clock generators. A

delay is given to the latch at evaluation stage to attain pre

amplification gain and the abundance power consumption is

avoided. A cross coupled transistor raises the pre amplification

gain and the input mode of the latch is lessen, this reduces the

delay. In this system the power is reduced to half and the

speed is increased .A single phase dynamic comparator is

designed in [2]. This comparator is used in the applications,

which has a vast input common mode range. The pre

amplification and latch phase are combined and is used. The

dynamic comparator attains huge speed with less power

dissipation compared to [7]. In [7] increased power is used due

to the static current in amplification phase. The comparator

presented in [3] increases the voltage differences between the

nodes, which decreases the latch regenerative time. Study on

the delay time in the comparator is also done. The kickback

noise is raised as the pre amplifier suffers a fast rail to rail

voltage swing. In [3] the comparator is optimized to reach low

power consumption and low delay. In [4] a dynamic double

tail comparator is designed. The double tail architecture gives

more desirable execution in low voltage applications. This

comparator increases the latch regeneration speed. In [4], the

delay and energy per modification is minimized to a greater

extent. In [5], a dynamic comparator is proposed. The reset

phase is as twin as conventional circuit. At evaluation phase,

the pre amplifier stage magnifies the input differential signal.

The latch stage amplifies the input differential signal. The

PMOS latch gains a little amount of offset and raises power.

In [6], the proposed comparator is composed of two phases,

the amplification phase and the regenerative phase. The

proposed system has an average of thirty one percent superior

speed than the other circuits .In [7] the input common mode

variation effects are analyzed and the common mode voltage

variation is reduced by using an energy. A dynamic

comparator with offset calibration is proposed in [8] and it

uses contrasting clock delays between the first and second

stages in order to obtain reconfigurable capability. Large

amplification of input difference is made at the input stage to

conceal the comparator noise. A dynamic comparator with less

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 11, 2019 (Special Issue) © Research India Publications. http://www.ripublication.com

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power and small offset is proposed in [9] to reduce the

mismatch caused by the conventional system.

CONVENTIONAL SYSTEM

PMOS transistors are used at the input of the

preamplifier and latch stage of the comparator. The

conventional arrangement let us establish the peerless delay

for pre-amplification and keep out abundance power usage.

The comparator gives a lateral input Vcm range in

fclk=500micro Hertz. CMOS amplifiers were used as passive

comparator, despite they undergo very high power

consumption. In two-stage dynamic comparators the kick back

noise is enhanced by fading the capacitive path. A special

controller for the comparator and PMOS latch with PMOS

preamplifier are used to achieve low power and high speed. It

works at high input common-mode voltages close to VDD. The

pre-amplification delay can be set to its flawless value to have

better speed and power.A PMOS latch is used in the latch

which is activated with a predetermined delay during

evaluation phase (tamp). At the reset phase, the clk, clkb1,

clkb2 hold a logic “1” to discharge output voltages of both

preamplifier and latch to GND.

Fig.1 Prevailing dynamic comparator

At the evaluation, first the clk and clkb1 are toggled

to logic “0” to start pre-amplification. During this phase, the

cross coupled circuit increases differential voltage (Vid1 =

[V01+-V01-1]) slowly and reduces the common mode voltage

(Vcm1=0.5*[V01+V01-]). Finally clkb2 is toggled to logic “0” to

activate. The latch and clkb1 is changed to logic “1” to turn

off the current source. The inverter is designed carefully to

adjust the delay. The delay of the evaluation phase is long

enough to attain minimum required pre-amplification gain for

a given speed and latch offset elimination. Transition of clkb1

to “1” limits the power consumption of the preamplifier. The

delay time from beginning of stage 1 to stage 2 is controllable

and can be tuned to its optimum value. A low power small

area delay line based controller is designed to make the

comparator robust against PVT variations. The cross-coupled

circuit is used to reduce the input common-mode voltage of

the PMOS latch which increases the speed.

PROPOSED SYSTEM

Fig [2] demonstrates the proposed dynamic double tail

comparator. For low voltage applications, double tail structure

has better performance when compared with other

architectures. In [1] power changes significantly, due to

current variations in the first stage (pre-amplification) is

pushing towards this structure. Adding transistors in parallel to

the circuit, results in lowering the offset and delay. The load in

first stage is a parallely connected dynamic latch, which is

used to increase the voltage difference. Due to cascade

connection delay will be more when compared to parallel. The

latch of the first stage start regenerating depends on the input

difference voltage thus provides a large voltage difference.

This is sensed at second stage latch regeneration output

voltage.

Fig.2 Intended dynamic double tail comparator

It consumes less power when compared to prevailing

comparator and the delay is diminished. The idea of this

structure is based on a separate input and cross coupled latch.

This latch enables fast operation. The notion of the comparator

is to abate its power consumption and to boost the latch

regeneration speed. Based on this intent, in cross coupled

manner two control transistors are added to the first stage. The

operation of the intented comparator, during reset phase

(CLK=0, NMOS_5 and PMOS_3 are off, avoiding static

power), PMOS_4 and NMOS_3 pulls both, fn and fp nodes to

VDD. Intermediate stage transistors, NMOS_6and NMOS_7,


Page 105 of 107

reset both latch outputs to ground. During decision-making

phase (CLK=VDD, NMOS_5, PMOS_3 are on), transistors

PMOS_4 and NMOS_3 turned off. Furthermore, at the

commence of this phase, the control transistors are still off

(since fn and fp are about VDD). Positive feedback during

regeneration is intencified which results in lowering the delay

time.

SIMULATION RESULTS

Fig.3 Output of the intented comparator in 180nm

Fig.4 Output of the intented comparator in 90nm

Fig.5 Output of the intended comparator in 45nm

Fig.6 Calculated power in 180nm



TABLE І

TECHNOLOGY

(nm)

POWER

(uW)

DELAY

(ps)

TRANSISTOR

COUNT

[1] 180 230 263 16

[4] 180 329 69 16

[8] 180 61 16 15

Existing 180 1.43 - 16

proposed 180 0.0759 252 12

90 0.0512 804 12

45 0.0201 265 12


Page 106 of 107

TABLE ІІ TECHNOLOGY

(nm)

TEMPERATURE

(degree)

POWER

(uW)

DELAY

(ps)

PROPOSED 180 25

30

35

40

0.0759

0.07613

0.07635

0.07657

252

262

269

275

PROPOSED 90 25

30

35

40

0.05127

0.05117

0.05105

0.05090

804

806

809

810

PROPOSED 45 25

30

35

40

0.02015

0.02023

0.02029

0.02038

128

138

144

152

CONCLUSION

In this paper power is calculated for double tail dynamic

comparator. Based on analysis a new comparator with low

power capability was proposed, simulation in different CMOS

technology shows that power of comparator is reduced to

greater extent in comparison with conventional comparator

and double tail comparator.

REFERENCES

[1]Ata Khorami and Mohammad Sharifkhani,“A Low-Power

High-Speed Comparator for Precise Applications”.

[2]Junfeng Gao,Guangjun Li and Qiang Li,” High speed low

power common mode insensitive dynamic comparator ” ieee

2015 electronics letter.

[3]A. Rabiei, A. Najafizadeh, A. Khalafi, and S. M. Ahmadi,

“A new ultra low power high speed dynamic comparator,” in

Proc. IEEE 23rd Iranian Conf. Elect. Eng. (ICEE), May 2015,

pp. 1266–1270.

[4]S. Babayan-Mashhadi and R. Lotfi, “Analysis and design of

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[5]A. Khorami, M. B. Dastjerdi, and A. F. Ahmadi, “A

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[6]Abbas, Mohamed, et al.”Clocked comparator for high-

speed applications in 65nm technology.” Solid State Circuits

Conference (A-SSCC), 2010 IEEE Asian. IEEE, 2010

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[8]A Khorami,M.Sharifkhani,”excess power elimination in

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52,jun.2017

[9]M.Ahmadi,W.Namgoong,”Comparator power

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comparators”,IEEE Trans.circuits syst.1 Fundam. Theory

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[10]A Khorami,M.Sharifkhani,”Low power technique for

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[11]B.Razavi,B.A.Wooley, “Design techniques for high-speed

high-resolution comparators:,IEEE J.Solid-State Circuits,

vol.27,no.12,pp.1916-1926,Dec.

[12]M.Miyahara,Y.Asada,D.Paik,A.Matsuzawa,”A low-noise

self-callibrating dynamic comparator for high-speed

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