eindhoven university of technology master design of an 8 ...noise analysis of the analog...

Eindhoven University of Technology

MASTER

Design of an 8-bit high-speed CMOS analog-to-digital converter

Venes, A.G.W.

Award date:1993

Link to publication

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Eindhoven University of TechnologyFaculty of Electrical Engineering

Digital Systems Group (EB)

Design of an 8-bit high-speedCMOS analog-to-digital converter

A.G.W. Venes,June 199:3

Report of the graduation projectfrom September 1992 - ,June 199:3performed at the Philips Research Laboratories,Eindhoven

Professor: Prof.dr.ir. R.,J. van de Plassche

Supervisor: Dr.ir. B. Nauta

@Philips Electronics N. V. 1998

Abstract

In this report the design of an 8 bit CMOS AD-converter for video applications is described. The system has been based on a folding and interpolation architecture. The mainadvantage of the folding principle is the multiple use of comparators, resulting in a compact and low power AD-converter realization. Because of the error averaging capability ofthe interpolation network, the AD-converter does not need offset compensation for devicemismatches. Due to the omission of offset compensation, the circuit is able to operate atvery high sampling frequencies. Simulations have shown an 80 MHz sampling frequency isexpected to be possible.Besides, the circuit has a low power dissipation of 45 mW on a supply voltage of 3.3 V.The effective resolution bandwidth of the system equals 9 MHz; this is sufficient for theactual video standards. Effective resolution bandwidth can be increased at the expense ofan increased power dissipation of the circuit.The circuit has been realized in the Philips C15QDM 0.8 pm CMOS process. Active chiparea accounts 0.6 mm2

. This report is based on simulation results. Additionally, the layout of the AD-converter has been extracted and simulated including interconnect and crosscapacitances to obtain a realistic overview of the real circuit behaviour.The presented AD-converter implementation offers several possibilities for further researchand video signal processing enhancement.

Contents

1 Introduction

2 Folding and interpolation system architecture2.1 Introduction: the basic folding architecture.2.2 8x folding versus a 4x folding system.2.3 Parallel operation of folding blocks ....2.4 Two stage interpolation network . . . . . .2.5 Fine encoding and digital error correction

2.5.1 Digital error correction ....2.6 Coarse encoding and synchronization .2.7 System architecture overview .

2.7.1 Characteristics of the folding and interpolation architecture.

3 CMOS folding and interpolation implementation3.1 Low power implementation of the folding block

3.1.1 The NMOS differential pair .3.1.2 A cascoded current source .3.1.3 Cross-coupling of differential pairs . . .3.1.4 Dynamic operation of the folding block3.1.5 Generation of the reference voltages ..3.1.6 Mismateh in a folding block .

3.2 Implementation of the two stage interpolation network3.2.1 The I --t V converter .3.2.2 Two times interpolation with the interpol-1 neLwork .3.2.3 Error reduction in the interpol-1 circuit .3.2.4 Amplifier implementation .3.2.5 Final interpolation with the interpol-2 circuit3.2.6 Resistor implementation . . . . . . . . . . . .3.2.7 Mismatch error correction in the analog preprocessing.

3.3 Dynamic performance of the analog preprocessing . . . . . . .3.3.1 Operation of the analog preprocessing at low frequencies3.3.2 High frequency operation of the analog preprocessing3.3.3 Step response of the analog preprocessing. . . . . . .

3

5

11111515161922232525

2727273031353839404143444647505053545660

4

3.43.5

3.6

3.73.83.93.103.11

Noise analysis of the analog preprocessingA folded cascode comparator. . . . . . .3.5.1 Kickback noise in the comparator .3.5.2 Mismatch in the comparator . . . .Digital error correction and 5-bit fine encoding.3.6.1 Implementation of the basic digital building blocks3.6.2 Digital error correction implementation3.6.3 5-bit fine encoding .Coarse encoding implementation .A positive edge triggered output flipflopClock buffering, output buffers and DA-collverterTiming diagram of the AD-converter . . . . .Simulation of the AD-converter using MILES.

CONTENTS

61616668686970717576787980

4 Layout design4.1 Floorplan of the integrated circuit4.2 Power supply distribution strategy4.3 Local45 layout extractions .....

5 Conclusions

6 Acknowledgement

Bibliography

A Transistor dimensions in the digital encoders

B Test setup of the chip

83

838586

89

91

93

95

97

Chapter 1

Introduction

From the introduction of the video technology up to the present, there has been a continuous improvement in video signal processing. From the purely analog signal processing,the trend of digitalization of the video signal processing still continues. This digital signal processing already has greatly improved features and quality of consumer appliancesand professional products. Some examples of the application of digital signal processingin video products are Teletext, Picture in Picture (PIP), Enhanced Definition Television(EDTV), the interactive compact disc (CDI) and digital video recording (DVCR).

The main architecture of a system incorporating digital video processing is shown in figure 1.1. A sensor and additional electronics generate an analog video signal. Obviously,the first step in digital video processing has to be the conversion of the analog signal toits digital representative. This function is performed hy the analog-to-digital converter(AD-converter). With the memory and digital signal processing parts of the system, manipulation of the input video signal hecomes possible. This manipulation can have manyfunctions, for instance extraction of information (teletext) or improvement of the videosignal. Finally, the manipulated video signal has to he converted to an analog signal. Thissignal can he used to drive the display and its additional electronics. The conversion ofthe digital signal to an analog signal is performed by the digital-to-analog converter (DAconverter). The whole circuitry from AD-converter to DA-converter will be controlled by avideo controller. To reduce printed circuit board sizes and device count, it is advantageousto integrate the whole digital signal processing, including AD- and DA-converters, on onechip. The overall result is cost reduction and miniaturization.

If integration of the whole digital signal processing on one chip is desired, easily power dissipation and clip size can exceed values to be able to realize in practice. Because of the lowpower operation of digital circuitry and the high device density required, implementationof the digital signal processor in an advanced CMOS process is favourable. Examples arethe Philips C200 1 Jim CMOS and the C150 0.8 Jim CMOS processes. With these processesincreasing device density becomes possible. Power dissipation is one of the properties ofthe circuit limiting the amount of circuitry to be integrated on a single chip.

5

6 CHAPTER 1. INTRODUCTION

ADConverter

Memol)'

: VideoSignalProcessor

DAConverter

AnalogVideoSignal

VideoControUer

AnalogVideoSignal

Figure 1.1: Basic architecture of a system incorporating digital video processing

An important property of an AD-converter is its resolution. The resolution is defined bythe number of output bits of the AD-converter. An AD-converter with a resolution of, forexample, eight bit quantizes the input signal to an 28 = 256 level binary code. For a digital video processing system high speed operation of the AD-converter is more importantthan a very high accuracy. This is in contrast with, for instance, digital audio systems inwhich resolutions of at least 16 bits are desired but at low conversion speed compared tovideo. Clearly, antagonism in the operation speed and accuracy of an AD-converter can beobserved. An eight bit resolution is just sufficient for implementation in the current digitalvideo processing circuits. This report deals with the design of an eight bit CMOS videoAD-converter. In the next future 10 bit AD-converters will be required for the enhancedvideo standards.

Many AD-converter architectures can be distinguished. The most straight forward ADconverter design has a full flash architecture. Figure 1.2 (a) shows a simplified blockdiagram of the full flash architecture. In an eight bit converter, 256 comparators detectthe level of the input signal. Although full flash is a very simple architecture, it inheres anumber of drawbacks. Most important of these are the large chip area and the incompatibility with a low power operation of the chip.Another AD-converter principle is the multi step architecture (figure 1.2 (b)). The conversion of the input signal to the output bits is divided in a coarse and a fine conversion} .Multi step conversion requires a sample and hold operation to precede the actual ADconverter. The coarse converter is implemented with, for instance, a full flash converter.The digital output code of this coarse converter will be converted to an analog signal by a

1A division in coarse and fine conversion results in a so called two step architecture. Obviously, in amulti step architecture additional conversion stages can be implemented.

7

: (a)PDigitai

"""""""',' Outputcode~. _ •••••••••• _. _. - - _ ••• _ ••••• _. _ ••••• _ •••••• _ ••• _. _. _. - ~ .....~ ~ ••• :~ ~ ~ ~•••_. - '"0"'" ~~ • _. _. _ •••••••••••• _. _ •• _ •• _. _. _. _ ••••••• _ •• _.:

ComeAnalog Sample

video --~ andsignal Hold

~conversion Cl

Fine+->--~ conversion

(b)

Coarse Outputcode Fme Outputcode~ .-.. --.- - -..- -.- --.. _ -.-.-.-.- -.-.- - - -.-.- - -- '

: Comer--1Iiil conversion

ComeOutputcode

Analog AnalogVideo -...I...illiil PreprocessingSignal

FineOutputcode

i (c)

~. _ ••••••• _. _. _ ••• _. _ •••••• _. _ ••••• _. _ •• __ • _. _. _ •• _ ••••• _ ••• _ •• _ •• _ ••••• _. 0_' __ •••••• _. _. _. _ •••• __ • _. _. _. _ •••••••• _." - ••••••'

Figure 1.2: Three AD-converter architectures: (a) Full flash; (b) Multi step; (c) Folding

DA-converter. Subtraction of tIris signal from the input signal results in a residue which isconverted to a digital code by the fine converter. The fine converter can be iniplemented asa second full flash converter. Comparator count in this architecture reduces significantlycompared to a single full flash converter. Drawbacks of the multi step architecture aredifficulties in implementation of the subtractor and the demand of an integrated sampleand hold circuit.A different approach is the folding AD-converter architecture (figure 1.2 (c)). Folding architectures are successfully implemented in very high speed bipolar AD-converters [2, 3, 4, 5].The conversion of the input signal to the digital output code is preceded by an analogpreprocessing circuit: the input signal preprocessing simplifies the actual analog to digitalconversion. Although a distinction can be made in coarse and fine conversion in a foldingAD-converter, a sample and hold circuit can be omitted. The AD-converter presented inthis report will be based on a folding architecture. As far as we know, this is the first timea folding architecture is implemented in a CMOS AD-converter.

In contrast with the conventional AD-converter architectures like full flash and multi step,in the presented folding architecture offset compensation is no longer necessary to compensate device mismatches. In a system architecture incorporating offset compensation,regularly device mismatches are registered in so called calibration dock stages. During theactual conversion dock stages, the registered device mismatches are taken into accountwith the signal conversion. It is dear the time needed for offset calibration is at the expense of signal conversion speed. Therefore, the conversion speed in the presented foldingAD-converter will excel compared to system architectures requiring offset compensation.

8 CHAPTER 1. INTRODUCTION

Table 1.1: Initial design constraints of the CMOS folding AD-converter

Property ValueResolution 8 bitInput signal bandwidth ~ 10 MHzPower dissipation ~ 50 mW @ VDD = 3 VClock frequency > 30 MHzActive chip area ~1 mm2

The proposed folding architecture competes with the fastest CMOS AD-converters at thismoment, but at a low power dissipation.

When this project was initiated, the design constraints in table 1.1 have been stated forthe AD-converter in research. Remember, the definitions in this table are merely designconstraints and much effort has been spent in stepping across these constraints. Accordingto simulations, successfully.In figure 1.3 a comparison of actual CMOS AD-converters is presented. In this figure,power dissipation and clock frequency of the AD-converters are compared. The resolutionof the converters is also mentioned. For additional conditions, for instance supply voltagerequirements, articles [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 21, 22] can be consulted. Inthis figure it can be observed, the presented folding AD-converter implementation has leadto very promising results. However, it has to be emphasized up to now only simulationresults can be presented.

Chapter 2 presents the CMOS folding and interpolation AD-converter on system level. Inchapter 3 the implementation of the system into CMOS circuitry will be described. Somelayout topics will be presented in chapter 4. Finally, in chapter 5 conclusions about thisproject will be stated.

P[mW]

1200

1100

1000

900

260

240

220

200

180

160

140

120

100

80

60

40

20

o

-13

-14 1. AT&T; lOb2. Philips,8b

0121 Texas lnst., 8b4. Hitachi,8b5. Sony,8b6. Hitachi,9b

01 7. Philips,8b

010 8. Toshiba,8b_ 2

9. Matsushita, 1Db04 10. Song, B. et ai., lOb

11. Dingwall, A. et ai., 8b-3 -11 12. NEC, lOb

II Steyaert, M. et ai., 8b14. Conroy, C. et ai., 8b15. Philips folding ADC

06 05 - flash-like architectureo Multi-Step-like architecture

07 ofolding architecture

080

15- According to simulations

09

([;;;,~©~

10 20 30 40 50 60 70 80 90 100 F [MHz]

9

Figure 1.3: Comparison of power dissipation and clock frequency of actual CMOS ADconverters

Chapter 2

Folding and interpolation systemarchitecture

In this chapter the main CMOS folding and interpolation system architecture will bedescribed. The system presented will consist of - for this moment - merely black boxes.However, this architecture is one-on-one matched with the circuit implementation presentedin chapter 3.

2.1 Introduction: the basic folding architecture

The function of an 8 bit analog-to-digital converter is to convert an input signal to a 256level digital (binary) code. With a flash converter, this 256 level output code is generatedby comparison of the input signal with 256 reference levels. So, 256 comparators are neededin a flash converter architecture.Consider the curves in figure 2.1. As mentioned, conversion to the digital code in a flasharchitecture is performed by comparing the drawn CUi ve in 256 comparators with a reference level. A folding architecture generates the 256 level output code with a quite differentapproach. The dashed line in figure 2.1 shows a derived folded version of the input signal.The folded input signal incorporates four up going edges and four down going edges andthe amplitude of this signal is reduced to one eighth of the original input signal. Thisfoldpd signal will be C?ll~d an eight times foldi!'g signal. 01'~'iously, the folding rate ofthe folding signal could be for example two, four or sixteen as well. However, the systempresented implements an eight times folding architecture. Folding rate trade-off will becovered in section 2.2.Assume it is registered which of the folding edges corresponds with the input signal. Thisinformation can be converted to an 8 level, 3 bit coarse output code. Now, in the foldingsignal a 32 level output code has to be distinguished. This can be performed by only 32comparators.The main advantage of the folding architecture compared to a flash architecture so far isa reduction in comparator count, from 256 comparators in a flash AD-converter to 32 in

11

12 CHAPTER 2. FOLDING AND INTERPOLATION SYSTEM ARCHITECTURE

-yl-axis- 1.0

FlASH

FOLDING

Signal to be

converted

conversion with 256 comparators

conversion with 32 comparators

0.00.0

........•......... ///// / / ../ // .

1.0

VinNmax

Figure 2.1: Input signal conversion in a flash and a folding architecture

the folding architecture. A drawback of this folding system is the frequency of the foldingsignal will be a multiple of the input signal. For the eight times folding signal in figure 2.1signal frequency might be eight times the input frequency. At the desired high speed videooperation this will lead to rounding of the tops in the triangle shaped folding signal.A double folding system could solve this high frequency rounding problem. Consider thedouble folding system in figure 2.2. The information around the tops of the folding signalscan be discarded. For any input signal, one of the two folding signals will be in its linearregion. Assuming selection logic selects the right folding signal, in the linear region of afolding signal only 16 levels need to be distinguished. This plUcess of adding folding signals to reduce the number of levels to be distinguished in a folding signal can be repeated.Finally, a system can be constructed with 32 folding signals. With 32 folding signals onlyone level has to he derived from a folding signal. In a differential or balanced foldingsignal, the only information to be gathered is whether it is positive or negative, so onlythe zerocrossings in the folding signal are of main importance.Consider the folding signal Fo in figure 2.3. One folding signal contains eight zerocrossings1

.

I Actually, the drawn Fo curve in figure 2.3 incorporates nine zerocrossings, this exception is a result ofthe Fo signal both marking the minimum input signal and the maximum input signal.

2.1. INTRODUCTION: THE BASIC FOLDING ARCHITECTURE

Coarse bitinfonnation

13

~_...~TO digitalencoder

Figure 2.2: Twin folding signal generation in a double folding system

:~'Cd/1dL1L1L1z=d./J-1 0.5 1 VinVrnax

A

t

o

---Fo

Figure 2.3: The 32 eight times folding signals


Yoill

Yoill

Coarse bit generationand encoding

1Analog foldingpreprocessing ..........

and fine encoding....

MSB

MSB-1 a>'"~0u

:E~

MSB-2

B4B3 a>

B2 J§

B1 :SV")

BO (LSB)

Figure 2.4: Generation of output bits in a folding architecture

With a number of 32 folding signals 8 x 32 = 256 zerocrossings are incorporated. Figure 2.4shows how the eight desired output bits are obtained in this way: a coarse block constructsthe MSB and MSB-1 bits and a folding circuit generates the third coarse bit MSB-2. Another five fine bits are derived from the 32 folding signals. For simplicity, an input voltagerange is assumed from 0 to 1. The zerocrossings of the folding signal Fo mark the transitions of the MSB-2 output bit. To link this folding system with 32 folding signals to thefolding principle in figure 2.1: the zerocrossings of the Fo folding signal correspond to thebottom and topmost points in the triangle folding signal in this figure. The 32 level codein one edge will be derived from the 31 equidistant zerocrossings from the other 31 foldingsignals. Each zerocrossing defines a one LSB step in the input voltage. The contribution ofthe five fine bits derived from the folding preprocessing to the digital output code (0-255)is shown by signal DF in figure 2.3.As stated before, the actual shape of the folding signals does not matter at all; the information in a folding signal is merely its absolute value. As long as a folding signal is notaffected in a region around the zerocrossings2 the performance of the AD-converter will notbe influenced. As a result, rounding in the folding signals at high speed operation will notdeteriorate system performance: the folding operation claims a large system bandwidthcompared to a flash converter. However, quality demands of the folding signals are low.

One folding signal incorporates eight zerocrossings and as a result only 32 comparatorsare needed to convert the folding signals to their digital representatives. This could beconsidered one of the most important advantages of the folding architecture. Compared toa full flash-like architecture, the number of comparators is reduced to about one eighth bythe analog preprocessing in a folding AD-converter. Generation of the 32 folding signalswill be possible with little hardware and a low power dissipation. This is a result of interpolation of folding signals, which will be explained in section 2.4. The encoding of the 32folding signals to a five bit binary code will he treated in section 2.5. First, the generation

2This constraint is related with the desired folding signal interpolation, section 2.4.

2.2. 8x FOLDING VERSUS A 4x FOLDING SYSTEM

of the folding signals will be described on system level.

2.2 8x folding versus a 4x folding system

15

The system presented will be based on a folding rate of eight. In this case, 32 foldingsignals each generate 8 zerocrossings. However, by generation of 16, 64 or 128 foldingsignals an architecture based on folding rates of 16, 4 or 2 would be possible. The prosand cons of a four and an eight times folding system will be compared below:

• Internal frequency: In the analog part of a folding AD converter the maximuminternal frequency (Fint,max) equals

1rF int max = - X Fin max X F R,, 2 ' (2.1)

with Fin,max the maximum input frequency and F R the folding rate of the system.The actual internal frequency is related both with the input frequency and the amplitude of the input signal. The eight times folding system requires a 125 MHzbandwidth at Fin,max= 10 MHz, twice the bandwidth of a four times folding system.

• The number of comparators (NC) depends directly on the folding rate:

NC = 256.FR

(2.2)

A number of 64 comparators is needed in case of a four times folding system andonly half that number with eight times folding. Clearly, in case of eight times foldingthis yields a considerable reduction in power dissipation and chip die size. The area(and power dissipation) of the digital part will be reduced comparable.

Considering two of the main design goals, low power operation and a compact chip size,an eight times folding system is favourable. Folding rates 2 or 16 are not feasible. Atwo times folding system would require 128 comparators, this is incompatible with thelow power demand. A sixteen times folding system would be even more interesting withrespect to power dissipation and chip size than the eight times folding system, but internalfrequencies involved with a folding rate 16 are not to be dealt with in the actual CMOSprocess. Chapter 3 makes clear that the bandwidth required f0r a folding rate 8 will beavailable with the proposed CMOS implementation.

2.3 Parallel operation of folding blocks

In the previous section the role of folding signal Fo was determined. Assume the blackbox in figure 2.5 to generate the Fo folding signal. The folding signal is represented by thedifferential output currents Fao and FbO :

(2.3)


~------------,

1 \inFB-OZi =_......."r Refs

\~~~~~~

Figure 2.5: A folding block generating the Fo folding signal

For a high speed AD-converter, generation of differential signals is necessary. Since theAD-converter will be embedded in, for example, a digital signal processor differential operation greatly improves the reliability and robustness of the circuit operating under noiseconditions corresponding to a digital environment. Fo has its zerocrossings Zi at Yin values

Z. ~ange

;=zx--8

(i=O ... 8) (2.4)

with ~ange the input voltage range. The triangle shaped folding signal from figure 2.1 hasthe shape of a sine wave in the actual folding block realization. But as stated before, thetops of the folding signal do not contain any important information. Parallel operationof four identical folding blocks results in the additional folding signals FI , F2 and F3 (figure 2.6). The zerocrossings of the FIsignal have been shifted along the Yin axis - ;2 ~angewith respect to the Fo zerocIOssings. Analogous, the F2 zerocrossings have been shifted- 3

22 ~ange and the F3 zerocrossings - 33

2~ange' Generation of the desired 28 other folding

signals will be performed by resistive interpolation as shown in the next section.

2.4 Two stage interpolation network

The number of 32 folding signals could be generated by using 32 folding blocks in paralleLIn this case however, the complexity of the folding system would not be less than thecomplexity of a full flash converter. Interpolation is a convenient way to generate themissing 28 folding signals. In this context, interpolation means that from the folding signalsavailable the missing folding signals are derived. This is shown in figure 2.7. Interpolationcan be performed by a number of methods:

• Capacitive interpolation,

• Current interpolation,

• Resistive interpolation.

A major drawback of capacitive interpolation is the large on-chip capacitance dimensionscompared to resistor dimensions. However, capacitive interpolation is compatible with atime-discrete interpolation system and offset compensation [16, 21]. The second interpolation method, current interpolation, is incompatible with the low power design constraint

2.4. TWO STAGE INTERPOLATION NETWORK 17

Yo :k I :FaOill

FB-Oz· Fw1

...........:.:.;.;.: .;.:.:.:. ;.:.:.:.:.:.:.:.:.:.:.

Yo

:,R,f,I

Fal

z,-:: FB-lFbI

........

z~ :IRd' I

Fa2

FB-21 32 Fb2

....

Y.

~~, IFa3ill

FB-3Zd2 Fb3

.......

Figure 2.6: Parallel Operation of four folding blocks generating Fo, F1 , F2 and F3

A

Folding signals

Interpolated folding signal

Figure 2.7: Generation of the missing folding signals hy interpolation


S.2lI

Sa4

.::::.:.:.;

:j AMP-O I SbIJ

:i:l AMP-I I Sb4

:\1 AMP-2 I SbS i: N

SalZ :,~:):J AMP-3 I SblZ ::: 0 . SO- S3I

:::::"'.~.,.,.,.:'.,.,.':"""':"'.,.,.::'... :~S:aI6::: ~

;"::::: !~

VaO

VbIJVaO

Val

VbIJ Vbl

I::VaZ

VaZ l""l vbZ

iii~ VaJvbZ 0

iii

AcVb3

~Va4

Va4

III

Vb4

Vb4 VaS

~: ~ VbS

Va6 Va6

Vb6Vb6

Va7

Vb7

""""""

IVCONV-3

IVCONV-2

IVCONV-l

IVCONV-O

F.z=-1IIiiI

FaO=_1IiiI

Figure 2.8: The two stage interpolation network

of the system [17] and offers no additional advantages. Resistive interpolation is the mostsuitable way to generate the missing 28 folding signals [5, 3]. It will not result in additionalpower dissipation and the area occupied by the resistors will be negligible.Besides the generation of the required additional folding signals, the interpolation networkplays an important role in reducing errors in the zerocrossings of the folding signals. Theseerrors can be due to mismatch in devices. A derivation of error reduction will be presentedin chapter 3.

In figure 2.8 a block diagram of the interpolation network is shown. The individual blocksin this figure will not be treated in detail in this chapter; the main concern in this chapteris that the two stage interpolation network generates the final 32 folding signals and nothow these folding signals are generated. The building blocks in the two stage interpolationnetwork can be described briefly as follows:

• The I -t V converters perform the transformation of the differential folding currents from the folding blocks to differential voltages.

• The interpol-l block performs a two times interpolation on the I -t V convertersoutput voltages. This results in a number of eight folding signals.

• The amplifier building blocks increase the amplitude of the eight folding signals.This gain stage is necessary for the comparators to he able to make a reliable 1-0decision of the folding signals.

2.5. FINE ENCODING AND DIGITAL ERROR CORRECTION

A....;

19

--- From folding block- - - . From rust interpolation.. -- .. ------ From second interpolation

Figure 2.9: Two stage interpolation of folding signals

• The final 32 folding signals are generated by the four times interpolating interpol-2block.

The distributed interpolation of folding signals in two cascaded interpolators is convenientfor both error reduction in the folding signals and use of system bandwidth. Next chapterdescribes the distribution of gain in the folding signal path and a calculation of the errorreduction. Figure 2.9 shows the interpolation of folding signals. Only a part of the inputsignal range has been drawn. Final folding signals are So to S3I in figure 2.8. Foldingsignals So, S8, SI6 and S24 are the folding signals generated by the four folding blocks. S4,

S12, S20 and S28 are the folding signals obtained from the interpolation in the interpol1 network. The other folding signals Si are generated by interpolation in the interpol-2block3

.

.2.5 Fine encoding and digital error correction

This section deals with the processing and encoding of the 32 digital folding signals. Forthe moment it is assumed that the transformation from the analog folding signal in itsdigital representative to be performed hy ideal comparators. The 32 digital folding signals(xo ... X31) will generate the circular thermometer-like output code in figure 2.10. A firstencoding step is to isolate the 0 ---+ 1 transition in this 32 hit circular code. This canhe performed by application of an EXOR operation on the adjacent circular output hits.The symhol and truth tahle of the EXOR gate are shown in figure 2.11. The result ofthis operation is a 31 hits code Cl ... C31 containing only one '1' or existing of only zeroes

:lIn the tops of the folding signals interpolation will fail. However, the shape of the tops of the foldingsignals do not affect the AD-converters performance.


v·ill

t

o><

1111111111111111111111111111111011111111111111111111111111111100111111111111111111111111111110001111111111111111111111111111000011111111111111111111111111100000

1111000000000000000000000000000011100000000000000000000000000000oo0סס110000000000000000000000000

oo0000000000000000סס100000000000

oo0000000000000000סס000000000000

Figure 2.10: Circular output code of the 32 folding signals

2.5. FINE ENCODING AND DIGITAL ERROR CORRECTION 21

a b Q

0 0 00 1 11 0 11 1 0

EXOR (±)

:)))QFigure 2.11: Truth table and symbol of the EXOR gate

Thennometer ...code

x o O........ G) ~ 0 C31XI O<G) ~ 0 c 30X2 O<G) ~ 0 C29X3 0<(0~1 C28x 4 1< +X s

1<(0~ 0 C27

x 61<G)~ 0 C26

x 7I/Q~O e21

~ One high code

Figure 2.12: EXOR-operation on circular output bits

(figure 2.12), a so called one high code. This one high code can be encoded to a five bithinary code. By inspection of a five hit hinary tahle, it becomes clear that the encodingof an output hit can he performed by only one 16-input OR gate. 4 The LSB output bitBo yields (with '+' the digital OR operation):

Bo Cl + C3 + C5 + C7 + C9 +Cll + C13 + C15 + C17 +C19+

C21 + C23 + C25 + C27 + C29 + C31·

This means the LSB output bit has to he '1' (true) if an odd Ci is true. Similarly, nextfour hits B1 ,B2 ,B3 and B4 should satisfy:

B 1 C2 + C3 + C6 + C7 + ClO + Cll + C14 + C15 + C18 + C19+

C22 + C23 + C26 + C27 + C30 + C31,

B 2 C4 + (;5 + C6 + C7 + Cn + C13 + C14 + C15 + C20 + C21 +

C22 + C23 + C28 + C29 + C30 + C31,

B3 C8 + C9 + ClO + Cll + C12 + C13 + C14 + C15 +C24+

C25 + C26 + C27 + C28 + C29 + C30 + C31,

4 Clearly, the on-chip implementation will not be a single 16-input OR gate, but an equivalent circuitcontaining 2/3-input. NAND and NOR gates and inverters.


Erroneousthennometer -code

X o O,(±)~OC3l

Xl o<(±) ~ 0 C30X 2 o<(±) ~ 1 C29

,"~X3 1<(±)~1 C28

Ix 4 O<G~1 C27X s I<G~O C26x 6 I<G~O C25x 7 I<G~1 C24"""r--x 8 O<G~l C23x 9 I<G~O C22x lO

1/

" Erroneous~ 'One high code'

Figure 2.13: EXOR-operation on erroneous x code resulting in errors in the c bits

B 4 CI6 + CI7 + CI8 + CI9 + C20 + C21 + C22 + C23 + C24+

C25 + C26 + C27 + C28 + C29 + C30 + C31·

2.5.1 Digital error correction

The encoding of the five fine bits has been hased on the principle, that only one Ci equals atrue status at a time. Now, consider one comparator to have made an erroneous decision,so a spurious '1' or '0' disturbs the circular code x. Figure 2.13 shows the results of theEXOR-operation on a code x containing two different errors. It is clear a spurious '1' or'0' in x might cause more than just one Ci to be true, resulting in an unacceptable error inthe five bit fine eode.

For example: Assume Cll only to be true. Using the described encoding this results in a digitalB4B3B2BIBo fine code 01011. Now, as a result of an error in the x code, ClO and C12 are trueadditionally. This results in a digital fine code 01111. The difference (error) in these codes is 4LSB.

To prevent these glitches in the output code a digital error correction should be implemented. The error correction circuit removes isolated '0' or '1' bits in the circular x eode.Assume l:/ being the corrected version of Xi, then

(i = 1 ... 30) (2.5)

defines the relation between .Ti and x/. This error correction logic generates a '1' if andonly if at least two of the input signals are true. Table 2.1 shows the effect of the errorcorrection function on the eight inputs possible. In two cases x/ will differ from Xi. Thisdigital error correction can not be performed on the Xo and X3I signals in the same way.First, these bits have only one adjacent bit, while two are necessary and secondly, only Xo

or X31 being different from the rest of the folding signals are legal conditions! However,because of the circular structure of the x code, correction of the Xo and X31 bits would

2.6. COARSE ENCODING AND SYNCHRONIZATION

Table 2.1: Digital error correction logic

Xi-l Xi Xi+l X;'

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

23

DigitalErrorCorrection

5-bitbinaryfineencoder

F= ~ B4F= ~ B3F= ~ B2F= ~ B1F= ~ Bo

Figure 2.14: Digital error correction implemented ill the fine encoder

be possible by using Xo and X31 bits. Figure 2.14 shows the location of the digital errorcorrection in the fine encoder.

2.6 Coarse encoding and synchronization

In the previous sections the generation and encoding of the five fiJ 1 e bits of the AD-converterhas been described. In section 2.1 it has been mentioned that the MSB-2 bit will begenerated by the analog folding preprocessing. So, the MSB-2 bit is implemented by theXo signal. This Xo signal represents the absolute value of the folding signal So. The coarsebits MSB and MSB-1 cannot be generated directly in a flash-like structure; as a result ofdelay in the analog preprocessing, especially around the MSB-2 transitions this could leadto wrong output codes. Instead, the MSB and MSB-1 coarse bits are generated indirectlyby a set of eight intermediate digital signals together with the MSB-2 signal. Digital logic

- -

extracts and synchronizes the desired coarse bits. Besides, overflow (OYF) and underflow(UNF) signals are extracted. These OYF and UNF signals will he used to drive the set and


Ll

~ ] I I I \ I I I IL2

~ ] I I I I \ I I IL3

~ ] I \ I I I I I IIA

~ ] I I \ I I I I IL5

~ ] I I I I I \ I IL6

~ ] I I I I I I \ I

L7

~ ] \ I I I I I I I

L8

~ ] I I I I I I I \XO(M<;B-2)

~ ] I 1 I 1 I 1 I0 250m 500m 750m

125m 375m 625m 875m

(VINNMAX)

Figure 2.15: Intermediate digital signals (L1...8) and MSB-2 bit Xo

reset inputs of the AD-converters output flipflops. In figure 2.15 the intermediate signals(L1...8) are shown together with the MSB-2 bit xo. By inspection of figure 2.15 it becomesclear that the following digital logic will generate the MSB and MSB-1 bits:

MSB

MSB-1

xo' L1 + Xo • L2, (2.6)

Xo' L 3 • MSB + Xo' L 4 • MSB + Xo' L 5 • MSB + Xo' L6 • MSB.(2.7)

Since the MSB and MSB-1 expressions contain Xo or Xo in all product terms, synchronization between the coar.;:p bits MSB, MSB-1 ano the MSB-2 hit will be accomplished.Additionally OVF and UNF conditions yield:

UNF

OVF

(2.8)

(2.9)

Equations 2.8 and 2.9 require the additional conditions:

Vin < 1I."in =} :1:0 true,

Vin > 1I."ax =} Xo false,

(2.10)

(2.11)

2.7. SYSTEM ARCHITECTURE OVERVIEW 25

with lI,nin the lower hound of the input voltage and lI,nax the upper bound of the inputvoltage.The signals L1...8 are each generated by a comparator. To prevent an erroneous digitalcoarse encoding as a result of a timing difference in the Xo folding signal and the sampledLi signals, from figure 2.15 and equations 2.6 to 2.9 it is clear that during the delay ofthe analog preprocessing \lin may maximally change {6 lI,.ange at maximum. Assume a fullrange sine wave input signal

(2.12)

During the maximal gradient of \lin, L 1 and L 2 are the most critical signals to be generatedwith respect to timing. Now, assume f = 10 MHz. At t = 0 the Xo signal has a 1 -+ 0transition. L2 will reach its transition at t ~ 2 ns and Xo will reach its next transitionat t ~ 4 ns. From this a general rule defining the coarse and fine sampling times can beformulated:

ts,fine = is,coarse +D.tap ± 2 ns (2.13)

with t s the sampling time and D.tap the analog preprocessing delay. From this formula it isdear that the clock signals of the fine comparators will have to he delayed with the delayof the analog preprocessing. This delay can be estimated by simulations, but a deviationof maximal 2 ns is allowable.

2.7 System architecture overview

A block diagram of the entire folding and interpolation AD-converter is shown in figure 2.16.Most blocks in figure 2.16 have been treated in the preceding sections. The eight bits areeach docked into a positive edge triggered output flipflop. This prevents glitches in theoutput signal due to different delays in the digital signal paths. The implementation ofthis architecture into CMOS circuitry will be treated in detail in the next chapter.

2.7.1 Characteristics of the folding and interpolation architecture

Ch erviewing the folding and interpolation system architecture presented in this chapter,next headlines can be summarized:

• Analog preprocessing in the folding and interpolation architecture reduces the num-·ber of comparators significantly compared to a full flash architecture. The architecture presented needs 32 comparators to encode the MSB-2 hit and the five fine bits.Besides, another eight comparators are necessary for generation of the intermediatesignals L, necessary for encoding the MSB and MSB-l bits and overflow and underflow conditions. The reduction in comparator count is beneficial for both reductionin power dissipation and chip area.


" N~~==-1~

~J

'--------------------~l Coarse encoding"=============""",,0j and synchronization

EXOR&5-bit BinaryFine Encoder

Figure 2.16: Block diagram of the folding and interpolation AD-converter

• The bandwidth of the system will have to be ~ X 8 times the maximal input signalfrequency. However, the shape and distorsion of folding signals will not affect theTHD of the output of the AD-converter as long as the zerocrossings of the foldingsignals are not affected. This means a very low demand on the linearity of thebuilding blocks in the analog preprocessing.

• The two stage resistive interpolation network is a reliable way to generate 32 foldingsignals out of the initial four. An important property of the interpolation networkis its capacity to reduce errors in the folding signals; this will be explained in detailin the next chapter. Offset compensation is no longer necessary to compensate formismatch of transistors in the analog circuitry. This makes it possible to acceleratethe AD-converters clock frequency compared to system architectures requiring offsetcompensation.

Chapter 3

CMOS folding and interpolationimplementation

This chapter will describe the implementation of the folding and interpolation architecturein CMOS. The AD-converter will be realized in the Philips 0.8 micron C150DM process.Because low power operation of the AD-converter is one of the major design goals, thesupply voltage VDD should be as low as possible. The circuits described will operate ata minimum VDD of about 3.3 V. However, realization of the AD-converter in the lowthreshold C150LP process makes operation possible at VDD = 3 V.

3.1 Low power implementation of the folding block

This section will deal with the implementation of the folding block in figure 2.5. The inputof this circuit is a single-ended input voltage. In the proposed system implementation, theoutput signal of a folding block will be a differential current. First the generation of oneedge of a folding signal will be described: a NMOS differential pair will be the basic circuit.

3.1.1 The NMOS differential pair

Consider the NMOS differential pair in figure 3.1. If both transistors nml and nm2 operatein saturation and strong inversion operation is assumed,

If) ~ (Vc;s - VT)2, with (3.1)

]{W

(3.2)r;JLCox .

Consider nmt and nm2 to have identical W, Land M 1 parameters and equal thresholdvoltages. It can be derived [1] that the differential current I a - h in this case satisfies next

lIn the forthc.oming, Wand L parameters are assumed to be in [pm]. M defines the MULT factor ofthe transistor.

27

-Is

~I«Vin - ~efh11! - (Vin - ~ef)2Is

28 CHAPTER 3. CMOS FOLDING AND INTERPOLATION IMPLEMENTATION

LlIs

Figure 3.1: The NMOS differential pair

formula:

if (Vin - ~ef) < -J¥i-if - J¥i- :::; (Vin - ~ef) :::; J¥iif (Vin - ~ef) > J¥i-

(3.3)The differential output current I a- h of the differential pair as a function of Vin is shown

in figure 3.2 with W = 10. ~Vin = J¥i- is defined as the input voltage increase necessaryto change the differential output current Ia - h from 0 to Is. From figure 3.2 it is clearthat ~Vin,W=lO ~ 375 mV; this equals the VGS - VT = VGT voltage of transistors mnl andnm2 if Vin = 0 V. However, in the folding signal eight -Is f-+ Is transfer curves are desired.

First, the range of the input signal Vin will be discussed. For this moment, assume theimplementation of current source il needs a voltage of at least 0.45 V at the commonsource node C8 of the differential pair, this will be made clear in section 3.1.2. A minimuminput voltage Vin of 1.425 V is proposed. With this minimal Vin, a normal operation of ilis safeguarded with VG.'i'l,2 < 0.975 V. The circuit should operate at VDD = 3 V. With thispower supply voltage, an input voltage range ~ange = 1.4 V is desirable:

1.425 :::; Vin :::; 2.825. (3.4)

If it is desired that the differential output current reaches -I" and Is values, ~Vin shouldyield:

1.4~Vin < -- = 87.5 mY.

8 x 2(3.5)

Obviously, implementing ~Vin,W=lO will result in a small amplitude of the folding signal.Increasing the i ratio of the transistors nml,2 will decrease ~Vin. Besides, the operationmode of the transistors will change from strong inversion to weak inversion. Accordingto [1], in weak inversion the drain current of 1W!1 satisfies

VGS-VT

ID1 = Ioe n1>t (3.6)

3.1. LOW POWER IMPLEMENTATION OF THE FOLDING BLOCK 29

1/ I.

- yl-axis

IA-lB

- Subvar-w,TO:O-2W:lOO.O3W: 1.251<

Vref=2.125

1..=1

M=l

Is=4OU

4O.OU (LIN)

30.OU

2O.OU

10.OU

0.0

-lO.OU

-20.OU

-30.OU

-40.0u1.775

/

,'1, :, :, :, :

1.95 2.125

/: /.: I

1/'/:-/,'

2.3 2.4751.862 2.037 2.212 2.387

(LIN) V(lN)

Figure 3.2: Differential output current I a - h of the NMOS differential pair as a functionof Yin

with n ~ 2, <Pt the thermal voltage, VDS at least several <Pt and

10 = CK<pt2 (3.7)

with C the fiddle factor to connect strong inversion and weak inversion models. Thedifferential output current I a - h in weak inversion operation yields [1.]:

(3.8)

(3.9)

Consider the Ia - h weak inversion curve in figure 3.2 with W = 1250: ~Yin,W=1250 ~ 120mV. Further increase of the ~ ratio of the transistors would not result in a substantialreduction of 6.Yin. Besides, ~Vin is independent of current Is. The transistor dimensionsrequired for full weak inversion operation are not to be realized in practice for Is ~ 40 IlA.First, transistor ~ dimensions of about 12

150 are incompatible with a compact chip size.

Second, capacitances of a transistor are proportional to its dimensions. The bandwidthrequired for the desired high speed operation would never be achieved with such largetransistors.Since both strong inversion and weak inversion have their drawbacks, a compromise is to


Figure 3.3: Realization of a cascoded NMOS current source

have the differential pair transistors operating in moderate inversion. As will be seen insection 3.1.3, a ~Yin = 175 mV will satisfy the demands of the folding block. Assuming differential pair transistor channel lengths L = 1, the parameters Wand Is can bedetermined. With respect to the values of these parameters, consider the following:

• A large lV results in large transistors. This is favourable for the offset voltage of thedifferential pairs. However, a disadvantage is increase of the transistors capacitancesand layout size.

• A small current Is is favourable for the power dissipation of the differential pair andthus for the overall AD-converter power dissipation.

With the above trade-offs, a choice for the Wand Is parameters can be made. Withparameter values W = 100 and Is = 40 pA the ~Yin = 175 mV demand will be satisfied(figure 3.2). Implementation of the differential pairs with this ~ ratio in the folding blocksmakes both a high speed operation and a compact layout possible. Current source]1 willhave to supply a constant current of 40 ILA, independent of the voltage at the commonsource node of the differential pair (V::s).

3.1.2 A cascaded current source

Cllrrent source]1 in figure 3.1 must supply a 40lLA current in a wide range of V::s' With1.4 :S Yin :S 2.8 V, VT = 0.73 V and the body effect taken into account, V::s,min = 0.45 Vand V::s max = 1.65 V.,A single NMOS transistor as a current source will not be sufficient, as the large VDS swingof this transistor due to the V::s swing of the differential pair in this case would affect thecurrent I D considerably. A cascoded current source is a necessity. Consider the realizationin figure 3.3. Transistors nm1 and nm2 are expected to operate in saturation. This means:

> VGTl

> VGT2

(3.10)

(3.11)

3.1. LOW POWER IMPLEMENTATION OF THE FOLDING BLOCK

Table 3.1: Cascoded current source parameter and specification summary

Parameter Value

Ii 10 IlA10 ~ 40 IlAv: . 0.45 VCS,ffitn

~s,fnax 2: 1.65 VV GT1 210 mV

IVGT2 100 mV

and

~s 2: V GTl + V GT2.

31

(3.12)

Transistor nml is determining the current 10 , Considering V T mismatches, a large VGTl

is favourable for a reliable 10 current with respect to 1;. However, a large V GT1 conflictswith the required ~s voltage range. As a compromise, with the transistor dimensions offigure 3.3 V GTl equals 210 mV and V GT2 equals 100 mY. Transistor nms is eonnected as a'NMOS-diode' to generate the desired easeode bias voltage. Important parameters of thecascoded current source are summarized in table 3.1. Input current Ii will be generatedoff-chip, so external adjustment of the current 10 is possible. The output current 10 as afunction of ~s is shown in figure 3.4.

3.1.3 Cross-coupling of differential pairs

The NMOS differential pair will be the basic circuit of the folding block. The differentialoutput current of one differential pair in moderate inversion has been described. A singledifferential pair defines a zerocrossing at 1!,.ej. The differential output current of a foldingbloek should ineorporate several of these zeroerossings. Cross-eoupling of differential pairsrealizes the upward and downward edges in a folding signal. Consider the cross-coupleddifferential pairs in figure 3.5. Zeroerossings are defined at both 1!,.ef1 and 1!,.ej2. The signof the differential output current I a - I b is positive if 1!,.efl < Vin < 1!,.e f2' I a - I b as afunction of Vin is shown in figure 3.6. The tail currents Is of the differential pairs are 40 ILA.The output voltages Va and Vb are fixed at 2 V with voltage supplies ea and eb. Currentsthrough these voltage supplies define the output currents I a and lb. Current sources j3and j4 inject eurrents into nodes a and b necessary to have no common output eurrents2

.

The overlap in the transfer curves of both differential pairs prevents the differential outputcurrent Ia - h to reach the maximum value of Is = 40 ILA.

2In the folding block, because of the odd number of differential pairs the common mode current injectedinto both output nodes a and b will be equal. This makes an easy self-biased implementation of thesecurrent sources possible.


- yl-axis- 45.Ou (UN)

10

4O.Ou /'

I35.0u

I30.Ou

I25.Ou

2O.Ou

15.Ou

10.Ou

5.0u

0.00.0 500.Om 1.0 1.5 2.0

250.0m 750.Om 1.25 1.75

(UN) Yes

Figure 3.4: 10 as a function of'Vc:s of the cascoded current source

Cross-coupling of differential pairs can be extended to generate the eight times folding signal. One folding signal is generated by eleven differential pairs and an additional dummystructure for improving performance in high speed operation. Consider generation of thefolding signal Fa. Including Vin,max and Vin,min, nine differential pairs generate the zerocrossings Zi from equation 2.4. The other two differential pairs define void zerocrossingsi y;'ange outside the Vin region. By this extension of the folding structure outside the inputvoltage range, all valid differential pair transfer curves are equally influenced by the transfer curves of their adjacent differential pairs. The dummy structure has a function onlyfor high frequency operation and might be discarded in a functional analysis of the foldingblock.

,---...,----<::::JvDD

I....-.+---------~.........-------+------+------<:::::::Jv:,~c~

Figure 3.5: Cross-coupling of two NMOS differential pairs


- yl-axis

IA-IB

REF1=2.125

REF2=2.3

30.00

20.00

10.00

0.0

-10.0u

-20.00

-30.00

-40.00

(LIN)

1\II \

I 1\

I \/ \

lJ \1.425

1.61.775

1.952.125

2.32.475

(LIN)

2.652.825

VIN

Figure 3.6: Differential output current fa - f b of cross-coupled differential pairs as a functionof Vin

Figure 3.7 shows the folding block implementation. The differential output current fa - has a function of Vi" is shown in figure 3.8. From this figure it is clear that the amplitudeof the folding signal increases with an increase of Vin. This is a result of the body effect.In strong inversion the transconductance gm of a transistor in saturation yields:

2fDgm = TT'

vaT(3.13)

The body effect can be modeled in the expression of the VaT voltage of a transistor asfollows:

VaT =2fD A(Vs )

J{(3.14)

Parametf'r A(VS') will decrease slightly with an increasing transistor source voltage. So, theVC;T voltage will decrease and gm will increase. This results in a steeper transfer curve of thedifferential pair. Although the differential pair transistors operate in moderate inversion,the given interpretation still explains the increasing trend in the amplitude of the foldingsignal. The zerocrossings will not be affected clue to this effect.

o 0

The voltages at the output nodes of the folding block -v.z and Vb will be determined by theVas of the PMOS transistors in the cross-coupled mirror structure (pm}, pm2 , pm3 andpm4 ). This circuit is able to provide the common currents for the differential pair outputnodes, so the common mode output current equals zero. Define gmp the transconductance


L ~dummy structur"?

Figure 3.7: CMOS folding block implementation

- yl-axis

lA-IB

40.00

30.00

20.011

10.Ou

0.0

-10.0u

-20.00

-30.00

-40.00

(LIN)

IA A /\ I

f\ /\ /\ II \ I \ IIII \ \ I \ II \

I 1\ I 1\ J I

I \/ 1\ / !\ / \ / \ II

v v v

V1.075

1.251.425

1.61.775

1.952.125

2.32.475

2.65

(LIN)

2.8253.0

3.175

VIN

Figure 3.8: Differential output current fa - f b of the folding block as a function of Yin


of the PMOS transistors pml...4. It can he derived that the impedance of the PMOSstructure R fb yields

for common signals and

1Rfb,com = -2

gmp

Rfb,diff ~ 00

(3.15)

(3.16)

for differential signals. An advantage of this circuit is, as mentioned before, the selfbiasing capability of this circuit. As already mentioned, the Vas voltages of the PMOStransistors pml...4 determine the DC hiasing of the output node voltages Va and v;,. WithIs = 40 ILA and a ~ ratio of pml...4 of \0 x 12, Vas of these transistors equals 1.3 V. So,the output voltages ~ and v;, are hiased at 2 V with VDD = 3.3 V. These output nodevoltages guarantee all differential pair transistors to operate in saturation. A disadvantageof the cross-coupled mirror structure is an additional VTp voltage drop required, althoughonly a VaT voltage drop would be necessary, if simple PMOS current sources would haveheen implemented. Because of the demand for low supply voltage operation of the ADconverter, this cross-coupled PMOS circuit will be a suhject offurther research. The PMOStransistors shown have a M factor of 12, this is convenient for layout technical reasons:every differential pair will have its own PMOS cross-coupled mirror circuit.

The folding blocks satisfy the demand for low power operation of the chip in a convincingway. From figure 3.7 it becomes clear that the total current flowing through a folding blockaccounts 13 x 40 + 2 x 10 = 540 ILA including the biasing of the NMOS current sources.This means the power dissipation PF in a folding block accounts

PF = 1.62 mW @ VDD = 3 V.

3.1.4 Dynamic operation of the folding block

(3.17)

High speed excitation of the folding block will introduce a few hard effects ill the circuit.A full swing sinw wave input signal of Fin = 10 MHz will lead to a maximal internalfrequency of Fint = 125 MHz of the folding blocks output currents I a and lb. Capacitancesof the transistors in the folding block could deteriorate the output currents: comparedto the 45 ILA (differential) current swing of the output signals, Clluents through parasiticcapacitances should results in only a fraction of this in the differential output signal toachieve an 8-bit performance. The large capacitances are a drawback of the large transistorsrequired for the moderate inversion operation of the differential pairs. With respect to thecapacitances in the folding block consider the following:

• The large number of transistors attached to the output nodes a and b of the foldingblock involve large junction capacitances of totally 0.65 pF at these nodes. Besides, there will he additional interconnect capacitance and input capacitance of theI ~ V converters connected to the folding block outputs. The voltage swing at


the folding blocks output nodes should be as small as possible to prevent unacceptable capacitive currents through these junction capacitances. Consider the followingcommon-differential current split in the folding currents:

Common currents from the folding blocks differential pairs will be handled inthe PMOS cross-coupled mirror structure. So, for common currents the foldinghlock has a low impedance of Rjb,com = 475 n.Most important is the affection of the differential folding currents by the foldingblocks output capacitance. Errors in the differential current directly influencethe AD-converters performance due to the shift of zerocrossings. Therefore alow input impedance of the I ---+ V converters for differential currents will beabsolutely required. As will be seen in the forthcoming, the input impedanceRi,dij j of the I ---+ V converters equals 250 n.

• The differential pairs in the folding block have three regions of operation:

1. Yin < v:.ej and the differential pair is not in its decision region: The commonsource voltage will be constant.

2. Yin ~ v:.ej: The differential pair is in its decision region.

3. Yin > v:.ej and the differential pair is not in its decision region: The commonsource voltage will follow the input voltage.

Two types of capacitances will be considered: Cgs of the differential pair transistorsand the total junction capacitance at the common source node of the differentialpairs. The Cgs capacitance of the transistors with the gate connected to Yin willintroduce an error current in the folding current mainly if Yin < v:.ej. The commonsource node junction capacitance will introduce an error current if Yin > v:.ef' Asa result of the cross-coupled differential pair construction of the folding block, errorcurrents due to these Cgs capacitances will compensate the error current due to thecommon source node junction capacitance partially. The Cgs capacitances of thedifferential pair transistors with a gate connected to a reference voltage and withYin > v:.ej can be added to the common source node junction capacitance. The errorcurrent due to the mentioned capacitances will be modeled as a single error current1" in the tail current Is of the differential pair. Currents 18 and (Is - 18 ) representthe contribution of the differential pair in its decision regioll to the folding currentsl a and lb.Discarding the dummy structure, the folding currents fa and I b satisfy next expresSIOns:

lcommon + al" +18

lcommon + (31" + (Is - 18 ),

the differential output current (Ia - h) of the folding block satisfies:

(3.18)

(3.19)

(3.20)


The (2I{, - Is) component in this expression defines the ideal differential foldingcurrent. The (0: - (3)1'1 component defines the additional capacitive error current. Inthese equations 0: defines the number of diffential pairs for which Vin > 1!,.ef yieldsand which tail current Is contributes to the I a folding current. Analogous, this yieldsfor (3 with respect to h. For simplicity, the differential pair in its decision region willnot be regarded in this analysis. Considering the construction of the folding block,the following relations between 0: and (3 can be stated:

whether (3

or (3

According to equation 3.21 (fa - h) yields:

0:+1.

(3.21)

(3.22)

(3.23)

this means a full cancellation of the error currents. However, the second relationbetween 0: and (3 in equation 3.22 results in the next expression for the differentialfolding current:

(3.24)

An absolute differential error current 1ry may result in shifted zerocrossings in thefolding signal. Full elimination of this error is hardly to be implemented. Thedummy structure in the folding block realizes a 50% reduction of the absolute errorcurrent. It consists of two source followers which in DC operation both contribute acommon -Is current to the folding currents. Capacitances involved with the nmdl

and nm25 transistors result in ~ ~ 1'1 error current in the drain current of transistornmdl. In the case equation 3.21 yields, the differential output current of the foldingblock including dummy structure satisfies:

(3.25)

In the case from equation 3.22 the differential output current (fa - 1b) of the foldingblock including dummy structure yields:

(3.26)

From equations 3.25 and 3.26 it can be observed that the absolute maximum differential error current in the folding signal decreases to tIt)'Simulations have confirmed the implementation of the dummy structure in the foldingblock results in an AD-converter distortion improvement of 6 dB.

• Gate-drain capacitances Cgd in the transistors of the differential pairs have no effecton the differential output current of the folding block. Six transistors have a gateconnected to Vin and their drain connected to the a node, but another six transistors


" " " " " " " ~I: " ~ "

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';.141~

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"'"I,,';;:

"'"I};;: ~ ",I;;; ",I';, ~ ~

Figure 3.9: Dual intertwined 44 tap reference ladder

are similarly connected to node b. This implies currents through the Cgd will resultin a common current injection into the output nodes a and b. Node voltages v;. andVb will have a common mode swing due to this current injection. However, it shouldbe emphasized that capacitance mismatch at the output nodes a and b may result inan error in the differential output current of the folding block.

3.1.5 Generation of the reference voltages

Each folding block requires eleven reference voltages. With a number of four folding blocksthis results in a total number of 44 reference voltages to be generated (n1r ... n44r). Adual intertwined resistor ladder will be implemented for this purpose. This reference ladderis shown in figure 3.9. The circuit consists of two identical parallel resistor ladders. Eachresistor has a value of R[ = 30 O. One of the ladders is used as reference ladder for thefolding blocks. The main reason for implementing the reference ladder as a dual ladderis for layout technical reasons. The reference resistors will be implemented by polysiliconresistors. Because of the non-uniform polysilicon sheet resistance Ro due to processinggradients, errors due to these gradients are prevented by anti parallel placement of the twolallders in the layout.Both reference ladders have been linked at five internal nodes: n4 Or) n32r) n24r) n16r andn8r, In the first silicon implementation of the AD-converter, it is desirable to be able tofix reference voltages by decoupling some reference voltages with an external capacitance.For this purpose, reference taps n36r, n24r and n14r have been assigned to a chip pin3

,

The reference ladder has one dummy resistor at the bottom side and four dummy resistors

.3Reference voltages n36r and n12r correspond to the V;n,max and V;n,min voltages. With respect todistortion of the AD-converter, these reference voltages are desired to be fixed at most. However, for layouttechnical reasons, the n14r reference tap instead of the n12r reference tap will be assigned to a pin.

3.1. LOW POWER IMPLEMENTATION OF THE FOLDING BLOCK

IN first metal interconnectwith contact holes

Figure 3.10: Profile of the reference ladders bottom side

39

at its top most side. These dummy resistors guarantee all used reference taps to be implemented with the same conditions, so all reference tap voltages are equidistant. Figure 3.10shows a profile of the bottom side of the reference ladder. The ladder current [lad flowsthrough the refiow metal-polysilicon contact holes, so the impedance between nodes refiowand n1r will be determined by the polysilicon resistance P S res in series with the metalpolysilicon contact hole resistance. No DC current flows through the contact holes of thereference taps, so the voltage difference (refiow-n1r) will differ from (n1r-n2r). Howeverall reference tap voltages are equidistant. Assume the n1r voltage would be connectedto an external reference voltage. In this case the ladder current would flow through then1r metal-polysilicon contact holes, resulting in a different (n1r-n2r). The reference tapvoltages will no longer be equidistant, so this could result in distortion of the analog preprocessing. The extension of the reference ladder prevents this to occur.With a total number of 48 resistors of 30 n each, the (single) ladder impedance equals1440 n, so the dual ladder has an impedance of 720 n. To satisfy the input voltage of thefolding blocks 1.425 S Vin S 2.825 V, Y,.efhigh and Y,.eflow have to yield:

Y,.eflow

y"efhigh

1.075 V,

3.175 V.

(3.27)

(3.28)

The total current 2Ilad equals 2.67 mA, so the power dissipation of the reference ladder PHequals:

PH = 8 mW @ VDD = 3 V.

3.1.6 Mismatch in a folding block

(3.29)

In this section the effects of mismatch in the differential pair transistors and NMOS currentsources in the folding block will be discussed. The matched pair spread of VT and ]{ willbe estimated with next matching models from the C150DM Blue Book:

A(VT )(3.30)


(3.31)A(K)

JWeff x Leff

with A(VT ) = 14.7 mVIl,m and A(K) = 3.7 % [JLm]. For the differential pair transistorsthis means:

0"(t1VT )

0"( t1K)K

1.57 mV

0.4 %

(3.32)

(3.33)

Mismatch in the differential pair transistors results in an offset of the zerocrossing definedby the differential pair. If this zerocrossing offset is called v;,ffset, ac~ording to [1]

[L t1Kv;,ffset ~ t1VT - VK x 2K (3.34)

yields if strong inversion operation is assumed. Considering the large K factor and thesmall Is current implemented, offset voltage due to 0"( 6..:) will be negligible, so the offsetvoltage can be approximated by

v;,ffset ~ t1VT . (3.35)

To satisfy a 40"( t1VT ) design, the offset voltage of a differential pair in the folding blockcan be modeled as a random 1!,.ef difference of at most ±40"(t1VT ) = 6.28 mY. This means,zerocrossings could have a deviation of ±6.28 mV from 1!,.ef' This corresponds to a 1.15LSB step of the input voltage. Section 3.2.7 deals with the influence of this deviation onthe performance of the AD-converter.Mismatch O"s(t1VT ) in the NMOS current sources in the folding block will be of less importance. The folding block contains 13 cascoded current sources. With respect to mismatch,6.5 of these current sources in parallel generate a mismatch error in the output current ofthe folding block. This means, matching properties can be modeled with one large transistor with dimensions 6.5~40. This results in a O"s(t1VT ) = 0.64 mY. The effective errorin the tail current of the differential pairs counts 0.9 ItA for a 40"s(t1VT ) current sourcemismatch; this means a 2% current error. As will be shown in section 3.2.3 the errorsin the zerocrossings of the folding signals due to this device mismatch will reduce in theinterpolation network significantly. Therefore, the performance of the AD-converter willbe able to maintain a level corresponding to the expected eight bit performance.

3.2 Implementation of the two stage interpolationnetwork

From the previous chapter, it has become clear that the two stage interpolation networkconsists of a cascade of (tll I ---+ V converter stage, a first two times interpolation networkinterpol-1, an internal amplification stage and an additional four times interpolation network interpol-2. The major function of the interpolation network is the generation of 32

3.2. IMPLEMENTATION OF THE TWO STAGE INTERPOLATION NETWORK 41

VDD

Iar 1RV

pbias

Voar 2RV Ib

b

f------~<Jnbia snTIL3

33,2,6

pbias

VDD

Biasing

LlInbias I

Figure 3.11: CMOS I ~ V converter implementation

folding signals out of the initial four folding currents from the folding blocks. Besides, theinterpolation network shows a great error reduction capability. Next sections will deal withthe generation of the additional folding signals and the error reduction will be calculated.

3.2.1 The I -4 V converter

In this section the I ~ V converter building block will be described. This I ~ V converterconverts the output currents of the folding blocks to a differential voltage. This differentialvoltage will be joined with the first interpolation stage.The circuit diagram of the I ~ V converter is shown in figure 3.11. Consider a differentialinput current Ia - h. The differential output voltage Voa - ~b satisfies:

(3.36)

The input impedance R i can be determined for common and differential input currents. Itcan be derived that Ri,com satisfies:

R icom ~ 00.,

For differential signals the impedance seen at nodes a and b equals:

1R d -!! =-t, t ,

gmi

(3.37)

(3.38)

in which gmi the transconductance of the transistors nml and nm2 in the I ~ V converter.Similarly, the output impedance Ro can be determined for common signals:

Ro,com = R v + R!b,com'

The impedance at nodes oa and ob for differential signals equals:

1Ro,di!! = -.

gmi

(3.39)

(3.40)


Table 3.2: I -+ V converter parameter summary

Parameter ValueIv 600 pA

9mi 4 mAV

R v 3.75 knR· 00t,COfn

Ri,diff 250 n

ROtcom 4225 nRo,diff 250 nInbias 30 pAIpbias 30 ILAPlV 1.8 mW (CiJ VDD = 3 V

Rfb,com defines the output impedance of the folding block for common signals. Table 3.2summarizes the important I -+ V converter parameters. Parameter PlV in table 3.2 definesthe power dissipation of the I -+ V converter.The drain current I D3 is related to the bias current Inbias:

I D3 ~ 20 x Inbias. (3.41)

This means, with a desired 1m = 600 pA Inbias should equal 30 pA. PMOS current sourcespm'4 and pm5 are biased with transistor pm6 and drain currents I D4 and I D5 yield:

I D4 = I D5 ~ 10 X Ipbias. (3.42)

The biasing transistors are implemented just once and will be used for all four I -+ Vconverters in the circuit. Matching between current I D3 and currents I D4,5 is not of greatimportance with respect to the functionality of the I -+ V converter. Normally,

I D4 + I D5 = 1m (3.43)

should yield, so Ipbias will be 30 ILA. However, if equation 3.43 is not valid, a (common) DCcurrent will flow through resistors R1 and R2 • This will not result in differential errors.Considering the combination of the folding block and the I -+ V converter, the followingcan be concluded:

• The PMOS cross-coupled mirror structure in the folding block will handle the common mode currents in the folding signals .

• Differential folding currents will be the input signals of the I -+ V converters.


VaO ~ VbO

I r_l~~~IRill

Val VLlr_' r_23Ri/2 Ri/2

Va2 Vb2

h'2 ~I~~I

Val Vbl

h~2 h~~1

Va4 vb4

~T~2 ~T~~

VaS VbSr_' ._19Ri/2 Ri/2

vd6 Vb6

I r_' ,_18Rill Rill

Va? Vb?

hj2 h}i

Figure 3.12: Implementation of the interpol-1network

3.2.2 Two times interpolation with the interpol-l network

The interpol-1 network implements a doubling of the number of folding signals by a twotimes resistive interpolation network. The implementation of the interpol-1 network isshown in figure 3.12. The folding signals VI = Val - Vbl, 1;3 = Va3 - Vb3, Vs = ~s - Vbsand V7 = ~7 - Vb7 are generated by resistive interpolation:

Vao +~2

2VbO +Vb2

2

(3.44)

(3.45)

Folding signals 1;3, Vs and V7 can be calculated analogous. Remark folding signal V7 isfound by interpolation of signal V6 cross-linked with signal 110. This means the interpolationladder is a closed ring: each folding signal has two adjacent folding signals.

Inherently, interpolation will be favourable to the differential non-linearity (DNL) of theAD-converter. According to [2] DNL is defined as:

(3.46)

with J{m+l and J{m two adjacent digital codes. SOlJ.t is the output signal of the converter.Assume an error c in a zerocrossing of, for example, folding signal 112. Eight times interpolation of this folding signal with its adjacent folding signals results in an error of ~c

between two of the generated folding signals. So, this yields a substantial DNL reduction.Due to the interpolation network and the large transistors in the folding blocks it willnot be necessary to compensate for mismatch in the analog preprocessing with an offsetcompensation circuit.


VbO

Va4

VaO

0 (]<>: <>:

CaO VaD CL~DD--

'"Ri

<>:0

<>:

Cal Va2 Cal

Ri0 0

<>: <>:

Ca2 Va4 Ca2

'"Ri<>:

0<>:

Ca3 VaG Ca3

Ri0 0

<>: <>:

CbD VbO CbO

Figure 3.13: (a) Simplified interpolation circuit (b) Equivalent circuit with star-delta transformation

It is clear, as long as the output impedance of the I ---t V converter Ro -=I 0 the foldingsignals vo = ~o -lio, V2 = ~2 -li2' V4 = ~4 -li4 and V6 = Va6 - Vb6 which are (mainly)determined by the output voltages of the four I ---t V converters will not necessarily beequal to the output signals of the I ---t V converters without any interpolation circuitryattached. Folding signal Vo will be influenced by its adjacent folding signals V2 and V6and this counts for all output signals of the I ---t V converters. This results in an errorcorrection capability of the interpolation circuit [20]; an error in one of the output foldingsignals of the I ---t V converters will be smoothed out in several folding signals V. Nextsection derives the error reduction because of the interpol-1 block.

3.2.3 Error reduction in the interpol-l circuit

In this section the folding signals VO, V2 , V4 and V6 are to be calculated as a function ofCo = CaO - CbO , CI = Cal - Cbl , C2 = Ca2 - Cb2 and C3 = Ca3 - Cb34

• Co, CI , C2 andC3 are to be considered output signals of the I ---t V converters without any interpolationcircuitry cOllllected5

• Consider the circuit of figure 3.13 (a). For simplicity only half of thedifferential circuit is drawn here. Folding signal ~4 is calculated as a function of the inputsignals, Ro and R i . Ro is the output impedance of the I ---t V converters for differentialsignals. Because of the circular structure of the interpolation cirCUIt in figure 3.12 nextderivation is applicable for all output folding signals. The interpolated signals are notincluded, because these signals do not contribute to any error correction themselves.First, voltages ~2 and ~6 should be eliminated. This is performed by a star-delta transformation (figure 3.13 (b)). Resistor values Rs and Rp yield:

(3.47)

4Gbl is related with Vb2, Gb2 with Vi,4 and Gb3 with Vi,6.

5This could also be modeled with an output impedance of the I --+ V converters of 0 f1.


Using Kirchhoff's current law at node ~4 it can be derived:

Ca2 - ~4 Ca3 - ~4 Cal - ~4 ~O - ~4 VbO - ~4 _ 0~ + ~ + ~ + ~ + ~ -.

(3.48)

(3.49)

Without loss of generality the assumption is made that the common mode voltage of thesignals in the circuit equals zero. This means

(3.50)

In this case equation 3.49 can he rewritten as:

(3.51)

An interesting conclusion from this equation is: ~4 is not dependent of CaD and CbO , butonly the adjacent folding signals have a certain impact on ~4' This could be derived fromthe circular structure of the interpolation circuit as well: assume CaD to have a contrihution0: to ~4' Clearly, in this case Cba would contribute -0: to ~4' resulting in a net contributionof zero.From equation 3.51 ~4 can be derived as a function of Call C a2 , CaS, Ro and Ri :

(3.52)

with

(3.53)

Ro is assumed to be fixed. Now the DNL error correction factor ECFl of the interpol-1circuit can be defined as a function of ~. ECF 1 is defined as:

D N L conected = E CFIX D N L uTlcorrected .

From equations 3.52 and 3.53 it can be derived ECF 1 yields:

ECF1

= Ro + R.Q

(3.54)

(3.55)

Figure 3.14 shows ECFl as a fUllction of ~:. This figure has heen obtained by simulationand it confirms the preceding derivation of ECFl.

The interpolation resistors (~Rj) have a value of 1200 n . The DNL correction factor ECF 1

can now be determined from figure 3.14 with ~ = 22~OO = 9.6. This means ECF1 :::::: 0.77,an error reduction of 23 %.


ECF2 SOO.Om

-yl-axis

ECFI

900.Om

700.Om

600.Om

500.Om

400.Om

300.Om

200.Om

100.Om

0.0

(LIN)

---I-----

----------~

.//

//

/II

0.02.5

5.07.5

10.012.5

15.017.5

20.0

(LIN) RI/RO

Figure 3.14: ECF1 and ECF2 as a function of ~:

The impedance level of the interpol-1 network is different for the 'real' folding signalsand the interpolated signals. Together with the input capacitance of the amplifiers whichload the interpol-1 network, this could result in different signal delays for the interpolatedfolding signals.The maximum delay difference ~t,max allowed in this 8 bit system equals:

2-8

~t max = --7 = 124 ps,, 1r10(3.56)

for a maximum input frequency of Fin,max of 10 MHz. Simulations show that with thechosen resistor values and amplifier configuration, the difference in delay in the interpolatedfolding signals will be less than 60 ps. However, the interpol-2 network reduces this delayerror with the ECF2 factor. So, signal dependent delay due to the interpol-1 network willbe within Lile limits for an eight bit system.

3.2.4 Amplifier implementation

The amplifier mainly consists of two parts. First the actual amplification stage and next asource follower to bias the common mode voltage of the folding signals at their right value6

6The common mode voltage at the amplifiers outputs will have to satisfy the comparator input rangedemands. In section 3.5 it will become clear that a common mode voltage of about 1.65 V satisfies thecomparators demands.


V~)D >---~-------.-----~--------,

Sa

nrn 450~0.8,2ia +----------11

a~f--__-----1~b50,1,2 50,1,2

Biasing----I

I

I

Il-n-rn_--;-6------+-----*-nm-_---::3-----nrn--<_~7*-+--------l---~H:----;;----<:::::Jambicl::; I10,2,2 25,2,2 10,2,2 I

V ee'_'::::' _ J

Figure 3.15: Implementation of the folding signal amplifier

and to lower the output impedance. Consider the amplifier implementation in figure 3.15.The output impedance of this building block will be determined by the source followerstage. With gms the transconductance of the source follower transistors nm4 and nms, itcan be derived the (single-ended) output impedance Ro yields:

1Ro = -. (3.57)

gms

The DC gain ~: of the amplifier stage depends on both the transconductance gma of thetransistors nml and nm2 and resistors R1 and R2:

~a ( )~ = R 2g ma . 3.58

With R2 = 5.5 kD and gma = 1.5 ~ this results in a DC gain of 8.25. Table 3.3summarizes the amplifiers parameters. PA defines the power dissipation of the amplifierincluding the source follower stage. Biasing of current source transistors nm3, nm6 andnm7 is performed by transistor nrns and bias current Iambias'

3.2.5 Final interpolation with the interpol-2 circuit

Thp eight differential outputs S of the amplifiers are fed into a four times interpolationnetwork interpol-2 resulting in a final 32 folding signals.In [3] an improved interpolation network has been described. This improved interpolationnetwork decreases the number of interpolation resistors by a factor two compared to aconventional interpolation network like the interpol-1 circuit. Assume the folding signalsto be linear in a region around their zerocrossings. Figure 3.16 shows the four times interpolation network, modeled together with the output resistance of the amplifiers. Sixteenfolding signals Si with even i are generated according to next formula:

(i = 0,2,4, ... ,26,28,30). (3.59)


Table 3.3: Amplifier parameter summary

Parameter Value

9ma 1.5 rnAT

9ms 1.42 rnAV

R12 5.5 kn,Ri 00

Ro 700 nDC Gain 8.25Iambias 40 ILAI D3 ~ 200 ILAI D67 ~ 80 ILA,PA 1.08 mW @ VDD = 3 V

Si are output signals of the amplifiers for (i = 0,4,8, 12, 16,20,24,28). For (i = 2, 6, 10,14, 18, 22, 26, 30), Si are interpolated folding signals. Another 16 folding signals Si withodd i are derived from the interpol-2 network. This is shown in figure 3.17. These foldingsignals satisfy next expression:

Sa(i+l) - Sb(i-l)

SbO - Sb30.

(i = 1,3,5, ... ,27,29), (3.60)

(3.61)

The interpol-2 network has an error correction capability comparable to the interpol-1network. However, a derivation for interpol-2 like the derivation in section 3.2.3 would leadto results hardly to be interpreted. The DNL correction ECF 2 is obtained by simulationof the interpol-2 network. In figure 3.14 ECF2 is shown. For ECF2 the ~~ factor will bedetermined by the output resistance Ro of the amplifiers and the interpol-2 resistors R2.

The resistors in the interpol-2 network have a value of 450 n, so Ri2 equals 2 x 450 =

900 n. The ECF2 DNL error correction factor can be determined from figure 3.14 with~~ = ~gg = 1.3 with Ro the output impedance of the amplifier building block. In this caseECF 2 equals 0.4, a 60 % error reduction. However, this error reduction does not yieldto mismatch in the folding blocks. Obviously, 50 % of the errors in folding signals VO, 112,114 and V6 from interpol-1 is contributed to the interpolated folding signals Vi, V;, 1:5 andV7 . The correction of errors from the folding blocks will be only ~ ECF 2. Other errors,for example delay in the interpolated folding signals Vi, V;, 1:5 and V7 will be correctedwith the ECF 2 factor. The delay differences in the final folding signals result in shiftedzerocrossings. This will contribute to the distortion of the AD-converter.

Now the DNL error correction of the two stage interpolation network can be summarized.The DNL error correction capability consists of three parts:


0 ~ ro N ~ n n n

• • • • • '" '" '" '" '"

N ~ <0 N N M • • • '" '" '"

_ .. ... ""

,. ~ . -,.

H

""

Figure 3.16: Four times interpolation network interpol-2 generating the final 32 folding signals

s" s .. ....•......•. ....... . ... .... .

............... d ········ ... C

.....•....•.• 3.: 5,( - 51>'

- - ---····-·· .. "'.E---~--___:)I'_-----b: Sol-S~ C:S.o-SbO d:S >4 - Sbl=S 1 e: S.l-SW=S I

Figure 3.17: Derivation of the folding signals S; with odd ·i


Table 3.4: Survey of the resistors in the two stage interpolation network

Building block Resistor value [0] # Instances Width [/Lm] TypeI ---t V converter 3750 8 1.2 ODp+Interpol-1 1200 16 3.2 PS on LOCOSAmplifier 5500 16 1.2 ODp+Interpol-2 450 32 4 PS on LOCOS

1. Inherently, interpolation gives DNL improvement. A DNL error e in one of the foldingsignals reduces to ~E merely by the eight times interpolation operation.

2. ECFt of the two times interpolation network interpol-I. This results in a 23% DNLerror reduction.

3. EC F 2 of the four times interpolation network interpol-2. Folding block mismatcherrors are solved ~ECF2' this means about 30% DNL reduction.

Combining these three 'error reduction sources', DNL errors due to mismatch in the foldingblocks are reduced

100 x (1 - 0.125 x 2 x 0.4 x 0.77) = 93%. (3.62)

Because mismatch errors in the folding blocks are most important to be reduced, there is noneed for any additional offset compensation circuitry in the proposed system architecture.This can be regarded a very favourable condition with respect to reliable and high speedsystem performance. The maximum delay difference in the final folding signals is below30 ps, which is an allowable delay difference for this 8 bit system.

3.2.6 Resistor implementation

Table 3.4 summarizes the resistors necessary to be implemented in the two stage interpolation network. The resistor types have been chosen considering resistor dimensions,matching properties and linearity. The worse linearity (voltage dependence) of the 0 Dp+resistors cOll1pared to the P S resistors does not affect system performance: the zerocrossings in the folding signals will not be affected, but only the shape of the folding signalwill be distorted. Capacitances of both resistor types do not differ substantially. Resistorproperties are described in the C150DM Blue Book.

3.2.7 Mismatch error correction in the analog preprocessing

In section 3.1.6 it has been derived that mismatch oftransistors in the folding blocks can bemodeled with offsets in the reference voltages attached to the folding blocks. Zerocrossings


- yl-axis-

DNL

750m

500m

250m

-250m

(LIN)

dlv N'v u

-500m

-75Om

-1o

32 96128 192

160

(LIN)

255224

OU11'UTCODE

Figure 3.18: DNL of the AD-converter with mismatch in the folding blocks

in the folding signals will shift due to these reference voltage offsets. Differential nonlinearity (DNL) will deteriorate as a result of this mismatch. It is possible to derive theDNL error from the 32 folding signals in simulations. This is accomplished by excitationof the folding preprocessing circuit with a low frequency full range (50 kHz) ramp voltage.Timing differences from the average LSB step time can be interpreted as and convertedinto the DNL of the AD-converter.For simplicity, a single threshold voltage mismatch is assumed in folding block F B o, whichcan be modeled as an offset Vof327 in the V n32r reference voltage. Reference voltage V:t32r

will define a zerocrossing corresponding to a digital '192' output code. Consider

(3.63)

with 0"(~VT )diff the threshold voltage mismateh of the folding blocks differential pairs.This offset voltage corresponds to 1.15 LSB step of the input signal. If the output code'192' would be determined by this single zerocrossing n32r (a full fiash-like structure), thiswould mean a DNL error of 1.15 LSB. In section 3.2.5 it has been derived that a DNLcorrection of 93 % is achieved with the two stage interpolation network. This derivation isconfirmed in a conviucing way by simulation. Figure 3.18 shows the final DNL of the ADconverter with the n32r mismatch model of equation 3.63, constructed from the foldingsignals. From this figure it becomes clear that the DNL error reduces from 1.15 LSB intoa straight forward design to 0.12 LSB in the presented CMOS folding and interpolation

7The choice of reference voltage V,t32r is arbitrarily.


II \J I

) \ AA

'y V'0.0

1.0

1.25 (LIN)

250.Om

750.Om

SOO.Om

-250.Om

- y1-axis

INL

-500.Om

-750.Om

-1.0

-1.2564 128 192 256

32 96 160

(LIN)

224

OUTPUTCODB

Figure 3.19: Worst case INL of the AD-converter with mismatch in a folding block

design. This yields a DNL error reduction of 90 %. Worst case situation for the DNL isthe occurrence of a +4o-(~VT ) and a -4o-(~VT ) mismatch in two adjacent reference levels.This leads to a maximum 4o-(~VT ) DNL error of 0.24 LSB.

Mismatch in the folding blocks is the most critical offset source in the whole analog preprocessing. The folding signals change from small differential currents to differential voltageswith an amplitude of about 700 mV. Throughout the analog preprocessing, the influenceof mismatch will decrease. The effect of error reduction has been demonstrated withmismatches in the folding block, however, it applies to mismatch in the whole analog preprocessing. Besides, from figure 3.18 it becomes clear that DC errors in the interpolationnetwork are negligible.

The two stage interpolation network has an INL (integral non-linearity) error correctioncapability as well. The INL is defined by the maximum deviation of the output of theAD-converter from a straight line between zero and full scale. The INL correction factorwill be determined by the interpolation resistors and the output impedances of the I -+ Vconverters and the amplifiers.

From figure 3.19 it becomes clear that the INL error for the digital output code '192' reduces from 1.15 LSB without interpolation to 0.93 LSB with the proposed interpolationarchitecture, a decrease of 24 %. The INL in figure 3.19 can be considered as a theoretical4o-(~VT )dif f worst case situation. This figure has been constructed with a single offsetvoltage in the n32r' reference voltage. In the realized chip, mismatch in the folding pre-

3.3. DYNAMIC PERFORMANCE OF THE ANALOG PREPROCESSING 53

..ClIJI· ... •...

~~'!~

SaoSb<lSa'Sb'Sa'Sb4Sa6Sb6Sa8Sb8SaIOSbIOSal:'.Sb"S.l14Sb14Sa16Sb16SalSSb18Sa20Sb20Sa"Sb"Sa24Sb"Sa2650"Sa28Sb"SaJOSb30

ret: reterenca l«ddvr (tic). 3.10)fb: foldinq block (tiq. 3.81lV: I-V Converter (fiq. 3.12)interpol_l: (fiq. 3.13)

~~rpol_2:(ri~~t\e.~7)ti9' 3.16)

Sb"Vb7

'H vao refhioh e-{UHJUWWJwwmwwmwwmmm~ renow

ref_I.

Vb.

1'1_2-..QUJ·... ·...QUl.o.o:>;>,u:

"UVa6

VbO

iv_O..QUI·... ·...ClUl,Q,Q>:>0.1:;

lIllit

Va'

r3b Vb6

F3a

F2b

Flb

F2a

Fla

FOb

FOa

t4bias curnias

fcbias C',!llcbiai;

Figure 3.20: Schematic diagram of the analog folding and interpolation preprocessing usedfor simulation

processing should he modeled with offset voltages in all reference voltages attached to thefolding blocks. In this practical case INL will be improved, because these (random) offsetvoltages will average in all folding signals. However, in video signal processing the INL isof less importance than the DNL of the AD-converter.

3.3 Dynamic performance of the analog preproces~-•lUg

In this section the performance of the analog preprocessing will be discussed. The operationof the different building blocks of the analog preprocessing will be monitored by CGAPgraphs of internal signals in the preprocessing circuitry. The circuit which will be analyzedis shown in figure 3.20. First the low frequency hehaviour of the AD-converter will heanalyzed with an input signal frequency of 1 MHz. Second, high frequency operation willbe analyzed with an input signal frequency of 10 MHz.


VIN

I(FB OOUTA)

~<.!'!'~~~"':B)

IO

2.825

2.125

1.425

15.Ou

5.Ou

-7.5u

30.Ou

2O.Ou

1O.Ou

0.0

-10.Ou

-20.Ou

-30.0u

0.0200.Ou

400.Ou6oo.0n

8oo.0u

(LIN)

LOu

T

Figure 3.21: Differential and single output currents of the folding block F B o with inputsignal frequency 1 MHz

3.3.1 Operation of the analog preprocessing at low frequencies

In this section dynamic operation of the folding blocks will be treated. DC operation hasbeen dealt with in previous sections. Consider the PSTAR simulation results in figure 3.21.The input frequency of the signal Yin equals 1 MHz. For the presented system architecture1 MHz can be considered as 'low frequency'. For input signal frequencies fin > 1 MHz,an effect of the capacitances in the circuit on the system performance becomes inevitably.It can be observed from this figure that the frequency of the differential output current 10

of the folding block F B o has its maximum around 500 ns. Besides, a DC common modecurrent of 4 ILA flows out of the output terminals of the folding block; this common currentis supplied by the PMOS cross-coupled mirror structure in the folding block and is a resultof inaccurate matching between the NMOS current source (nbias) and the PMOS currentsources (pbias) in the 1 ----t V converter: equation 3.43 is not exactly satisfied. However,this does not result in a differential error, only DC common mode voltages of the foldingblocks output nodes a and b and the 1 ----t V converters output nodes will differ 15 mV8

.

The final folding signals So, S8, S16 and S24, related to the differential output eurrentsof the folding bloeks, are shown in figure 3.22. For simplicity, the 28 interpolated foldingsignals are omitted in this figure. It is important to know what folding signal amplitudearound the zeroerossing defines one LSB step. In other words: in a one LSB region around

80bviously, mismatch between the two PMOS current sources in the I ---t V converter can result in adifferential error.


YIN

SAO

SBO

SO

S8----------SI6-------------------S24

2.825

2.125

1.425

1.85

1.65

1.45

4OO.Om

2OO.Om

0.0

-200.Om

-400.Om

0.0200.00

400.00600.00

800.00

(LIN)

1.0u

T

Figure 3.22: PSTAR simulation of folding signals So, Ss, S16 and S24 with input signalfrequency 1 MHz

the zerocrossing the comparator may decide either '1' or '0' without losing the eight bitperformance. The requirement is, that only one folding signal is in this 'grey' region ata time. In case of linear folding signals in the whole amplitude range, the LSB regionwill be 116 of the peak-peak voltage of the differential folding signal. As a result of thesine wave-like shape of the folding signals, this reduces to about 2

10 of the folding signal

peak-peak voltage for the real implemented signals. This means in the presented systemimplementation, the decision region VL.'>B for the comparators is 7

2000 = 35 mV.

Harmonic distortion of the converter can be analyzed with the folding signals. For thispurpose a software tool has been used. The moments of zerocrossings in the folding signalscan he extracted from PSTAR simulation results. Since the zerocrossings correspond tothe level of the input signal, a reconstruction of this input signal can he made from thezerocrossings. This means: a graph is constructed with the non-equidistant moments ofzerocrossings on the x-axis and the equidistant reference levels on the y-axis. With CGAPspline and FFT options the distortion of the reconstructed signal can be analyzed.For the .hI = 1 MHz input signal, with this analysis figure 3.23 is ohtained (RECON).Distortion for this input frequency shows to satisfy required 8 hit performance convincingly.


1\ Iry-hI'-. I ~ ~

v~ I'-----.J1 V---J~ IAJI\ ",A I~ vv- ------v

-100.0

-90.0

-80.0

-70.0

-60.0

-40.0

-30.0

-20.0

-10:0

0.0DB(RECON)

-yl-axis- 10.0 (LIN)

-50.0

0.0 2.0M 4.0M 6.0M 8.0M 10.OMl.OM 3.0M 5.0M 7.0M

(LIN)

9.0M

Frequency

Figure 3.23: Distortion analysis with a full range input signal frequency of !in = 1 MHz

3.3.2 High frequency operation of the analog preprocessing

In the introduction one of the design goals summarized is the AD-converter to have ananalog input bandwidth of at least 10 MHz. Previous section has made clear that low frequency performance satisfies the design goals. The high frequency equivalent of figure 3.21is shown in figure 3.24. In the output voltages and currents of the folding hlock a commonmode swing can he ohserved. This does not affect the differential output current of thefolding hlock. Figure 3.25 shows folding signals So, S8, S16 and S24 for an input signalfrequency of 10 MHz. Comparing figure 3.22 and figure 3.25 the difference in the foldingsignals is a decrease in folding signal amplitude and folding signal delay. Because of thedecreased amplitude of the folding signals, the decision region for a comparator VUlB decreases to 25 mV.

Common mode voltages in tl: analog preprocessing a:::e shown ill fig;.;.re 3.26. F B com defines the common mode voltage at the output nodes of folding hlock F Bo. IVcom is thecommon mode voltage at the output nodes of I ----+ V converter IVa and finally, AMPcom

defines the common mode voltage of folding signal So. The common mode voltage swingdecreases from 8 mV at the folding hlocks output nodes to 2.5 mV in the final foldingsignals. The ratio ~diff increases from 1 at the outputs of the folding blocks to 140 in thefinal folding signals. com

Distortion of the AD-converter for an input signal frequency fin = 10 MHz is shown infigure 3.27. Analyzing this figure, it can he concluded that the AD-converter still satisfies


YIN

YN(FAO)

Y!'lJ!'~2) .

I(FB o\oUTA)

~(.!'!'~~t:~)

10

2.825

2.125

1.425

2.045

2.035

2.02

2O.On

5.0u

0.020.00

4O.On60.00

(LIN)

80.00100.On

T

Figure 3.24: Differential and single output currents of the folding block F B o with inputsignal frequency 10 MHz

YIN

SAO

SBO

SO

S8

Sl6

S24

2.825

2.125

1.425

\.85

\.65

\.45

400.Om

200.Om

0.0

-200.0m

-400.Om

~l::= ±:£ E?I

0.02O.0n

40.0060.On

(LIN)

80.On100.On

T

Figure 3.25: PSTAR simulation of folding signals 50, 58, 516 and 524 with input signalfrequency 10 MHz


FBCOM

IVCOM

AMPCOM

0.0 4O.On 80.On2O.0n 60.On

(LIN)

100.On

T

Figure 3.26: Common mode rejection in the analog preprocessing. fin = 10 MHz.

(\

'\ ~ I'\.... I \ 11\hi '-'

~ ~ VV \ J \fvVV

-90.0

-80.0

-70.0

-60.0

-50.0

-30.0

-10.0

0.0

-20.0

-40.0

-yl-axis- 10.0 (LIN)

DB(RECON)

-100.00.0 20.0M 40_0M 60.0M 80.0M

10.OM 30.0M 50.0M 70.0M

(LIN) Frequency

Figure 3.27: Distortion analysis with a full range input signal frequency of fin = 10 MHz


- yl-axis- 10.0 --T(""dB:L..)---,r----,---r---r---,---,---,----,----,r----,2nd

3rd 0.0--------_.4th

-10.0

-20.0

-30.0

v--.----.-----------------.----..~

---

I ~ .;~;~~~_.V.··/··~ I -=-=--

/ -- ./.~., ,,',.' ,

4.0M 8.0M l2.0M 16.0M 20.0M2.0M 6.0M 10.OM 14.0M 18.0M

(LI N) Frequency

-40.0

-50.0

-60.0

-70.0

·80.0

-90.00.0

Figure 3.28: 2nd , 3rd and 4th harmonic as a function of the input frequency

an 8 bit performance with respect to distortion. The bias rails in the folding blocks, Y:,urbias

and Y:,ascbias have been decoupled in this experimental design with an external capacitanceto eliminate distortion due to capacitive current injection into these bias rails. Simulationhas shown that this capacitive crosstalk causes about 2dB deerease in distortion of thepreprocessing9

. In figure 3.28 second, third and fourth harmonic distortion are shown as afunction of the input signal frequency. In this figure, 3rd harmonic shows to be absent atlow frequencies, hut for input frequencies !in > 5 MHz, this 3rd harmonic plays the dominant role in the harmonic distortion performance of the analog preprocessing. However,harmonic distortion will be below -50 dB for an input frequency up to 13 MHz. It must beemphasized that these simulation results will be deteriorated in the real chip implementation by, for instance, interconnect capacitances, cross capacitances, substrate bouncingand mismatch. In the next chapter Local45 layout extraction simulations will be described.These simulations include interconnect capacitanees and cross capaeitanees. As expected,overall system performance WIll decrease in this case. Third-order <.1Istortion will decrease10 dB. However, it will be shown that an increase of the AD-converters power dissipationcan greatly improve high frequency operation of the circuit. Besides, these Local45 layoutsimulations are the most realistie simulations to be performed and obviously result in areliable representation of the real chip performance.As might be expected and according to simulation results, the analog preprocessing cir-

9This is according to 'normal' PSTAR simulations and transistor models. It is clear that in the realchip or Local45 simulations capacitances will be increased.


Foldingsignals (32)

400.Om

300.Om

200.Om

IOO.Om

0.0

-100.Om

,200.0m

-300.Om

-4OO.0m

LIN)

t~-~- --_ - _- _~- _

~ J~--:---- -,--- '------~-==-='-==-'- t-cc.'=-='--=-,!=-:~:--=-cc.'-:=r-=-=,'-'-=-,-±-;j~~ , -- - - - -

, , ",. '- - - -

YIN

(LIN)2.8

2.1

1.4

0.0S.On

10.OnIS.On

II

20.On25.0n

30.On

(LIN)

35.0n40.On

Figure 3.29: Response of the analog preprocessing on a pulse shaped input voltage

cuit shows a low pass characteristic. This means that the influence of high frequencysignals (~ 10 MHz) on the reference ladder, for instance due to substrate bouncing, willbe decreased in the final folding signals and has less influence on the performance of theAD-converter.

3.3.3 Step response of the analog preprocessing

The step response of the analog preprocessing can be defined as the time necessary for all 32folding signals to have their exact absolute value with a step shaped input voltage. Considerfigure 3.29. The input signal is a full range step voltage with a 1 ns rise time. Foldingsignal settling should last at most one clock period. In this design the minimum clockperiod will count about 12.5 ns. The preprocessing satisfies this constraint convincingly.From figure 3.29 it becomes clear that the settling time of the 32 folding signals accountsonly 5 ns. This fast system response is a result of the straight forward implementation ofthe folding preprocessing, it is implemented without any feedback loops.A 1ns rise time of the input voltage will not appear in real operation of the AD-converter.This step response however is a valid test for the speed of the folding preprocessing. Besides,the fast settling of the folding preprocessing makes the AD-converter possible to obtain afull-N yquist performance together with a sample & hold circuit. In this case, the sample& hold will determine overall AD-converter performance: after settling, the AD-converterwill show a performance comparable to its DC behaviour.

3.4. NOISE ANALYSIS OF THE ANALOG PREPROCESSING 61

~

~fo-f0-

r-fo- V

...----=

===:: =

-

1.Orn

(LOG)3.Orn

100.00

. yl-axis·

VNOISE

10.00

100.01.01<

10.Ok100.Ok

1.0M loo.OM10.OM 1.0G

(LOG) F

Figure 3.30: PSTAR noise analysis of the analog preprocessing

3.4 Noise analysis of the analog preprocessing

In the preceding sections the decision region VU,B of the folding signals has been determined. Noise in the analog preprocessing (thermal noise, y-noise) will influence thezerocrossings of the folding signals. However, a deviation due to noise within the VLSB

region will not result in a decrease of AD-converter performance.Figure 3.30 shows the results of a PSTAR noise analysis of the analog preprocessing. Forthe frequency range 100 Hz - 1 GHz the maximum nns noise voltage10 V;wise in a foldingsignal S accounts 2.3 mY. The bandwidth of the analog preprocessing circuit equals ahout140 MHz.Considering the VLSB = 25 mV decision region of the folding signals at an input frequencyof 10 MHz and an allowed noise voltage of k VLSB it can he concluded that the noisein the analog preprocessing devices will not result in a deterioration of the AD-converterspelformance.

3.5 A folded cascode comparator

In chapter 2 the conversion of the 32 folding signals to their digital representatives wasassumed to be performed by 32 ideal comparators. Eight additional comparators arenecessary for generation of the digital L signals in the MSB and MSB-l coarse encoding.

IOThis result is obtained by integration of the noise power spectrum.


PMOS, ~,l,t

IpbiasDr--II----II----l1

r----t==J:;-:------;:-j"J

InbiasD----j~-----l1

'------.J.<:::JVSSD

LIAN::..:.:..::AL::.c0=--=G~ ..:..:MA:..::C::..:oT:..::E::..::..JR1 I~S_LA_V_E [_)I_G_IT_A_L~I

Figure 3.31: Implementation of the master slave folded cascode comparator

Obviously, the actual comparator will not be ideal. The comparator determines a lot ofthe overall system performance and dimensions:

• The maximum sampling clock frequency. As will be seen in section 3.6 the digitalencoding logic will be able to operate in a system with a sampling clock of over 100MHz. The comparator determines the maximum clock frequency which is below thissampling rate. If it is possible to clock the comparator with even higher frequencies,then the digital encoder could be implemented with 'faster' logic. With respect to theanti-aliasing filter preceding the AD-converter, a high clock frequency is favourably.

• Power dissipation: 40 comparators are necessary in the presented AD-converter architecture. This means a considerable reduction in comparator count compared toa flash-like architecture, however power dissipation of the comparators still is a substantial part of the overall power dissipation.

• Chip area: a sophisticated layout design of one comparator will save much area inthe whole circuit layout.

The implemented comparator consists of a master and a slave part. These master andslave parts have separate clock inputs.First, the master part of the comparator will be discussed. Figure 3.31 shows the circuit implementation. The comparator consists of a folded cascade structure. The inputdifferential pair and the latch pair have been implemented with fast NMOS transistors.The differential folding signal is connected to the inp and inm nodes of the input differential pair. Transistor nm3 is used as a tail current source of the differential pair and willbe biased externally through current Ilnbias with the current mirror nm3, nmln. PMOStransistors prn} and prnz are current sources biased with transistor prnlp and the external

3.5. A FOLDED CASCODE COMPARATOR 63

current Ilpbias' Folded cascode transistors pm3 and pm4 are biased with pmos transistorpm,/c and current Ilcbias'Operation of the (master) comparator consists of two phases:

• The reset phase;

• The latch phase.

These two phases are controlled by the clock signal CM at the gate of NMOS transistornm6: with a CM = VDD voltage (3.3 V, logically '1' signal) the comparator operates in thereset phase. A CM = Vss voltage (0 V, logically '0' signal) means the comparator operatesin the latch phase.

Consider CM = VDD . NMOS transistors nm4 and nms, connected as 'NMOS-diodes',are void devices in the reset phase. Node voltages Vitl and Vit2 are determined by thegate-source voltages Vas7 and Vasg of the latch pair transistors nm7 and nmg. Transistornm6 behaves like a controllable resistor. A drawback of this implementation is that thedrive (Vc;s - VT = VaT) of transistor nm6 depends on the threshold voltages of transistorsmn7, nmg and nm6. Furthermore the threshold voltage of nm6 will be increased by thebody effect. The drive of transistor nm6 will vary as a result of threshold voltage spreadll

.

With a typical threshold voltage VTO = 0.73 V assumed, VaT6 = 1.15 V. Simulations haveshown that the drive requirements of switch nm6 are even satisfied with a 'SLOW NMOS'(high VTO ) implementation. However, the maximum clock frequency of the comparatorwill decrease somewhat. Vitl,2 are determined by the gate-source voltage of transistorsnm7 and nmg: Vc;S7,g = 1.06 V. In the quiescent condition (Vinp - Vimn = 0 V) the currentsthrough transistors nm}, nm2, pm3 and pm4 are all 20 ItA. The network nm6, nm7 andnms forms the load of the differential input stage. If CM = VDD , transistor nm6 operatesin its triode region and acts as a positive resistor. Transistors nm7 and nmg behave asnegative resistors __1_ with 9mc the transconductance of transistors nm7 and nmg. These

- gmc

transistors are designed in such a way that the net resistance of nm6, mn7 and nmg fordifferential signals is positive during the reset phase. Therefore the reset phase can beconsidered as a pre-amplification phase as well. The difference in the voltages Vitl and Vit2 .

will cause the latch pair to make a right decision in the latch phase.

Now, consider CM to be logically '0'. Transistor mn6 will stop conducting anyway andits resistance becomes infinite. Latch pair transistors nm7 and nms will form a positivefepdback loop. Transistor network nmf3, mn7 and nms lIas a net negative impedance fordifferential signals (Rc ) of:

1Rc = --.

9mc(3.64)

This means, in the latch phase finally one transistor conducts all current, but has the lowestdrain voltage. This will apply to the latch pair transistor which has the highest initial gatevoltage. The settling of voltages Vitl and Vit2 in the latch phase consists of three phases:

11 Absolute threshold voltage spread has been simulated with SLOW and FAST process blocks in thePSTAR simulator.


zoom active

VN(ITI)1.6

Y_N_(~L_.

1.2

800.Om

400.Om

0.0VN(INM) 1.646Y~(!~~L __

1.64

1.634eM 3.5---

2.0

0.0

LIN), ,-- ,-- -- r I I, ,, ,,, , ,,, ,, ,,

K,:~ W H~ h , ' , ,, , I, , ,, , ,, , ,, , ,

, I ,,, , ,l..-

I I,

\..~ ~,.-. ,,_ ... _- \. _.. -

-e:t=F3 3§;3BBilDBOI0.0

25.On50.On

75.On100.On

(LIN)

I25.On150.On

T

Figure 3.32: Output signals Yin and Vit2 of the master comparator operating at a 40 MHzclock frequency

1. The settling of latch pair transistors nm7 and nms has a time constant

CiT/=-.

gme(3.65)

Ci defines the capacitances at the itl and it2 nodes; with the proposed transistordimensions T/ :::::: 800 ps.

2. The Vit voltage lwhich will reach a high state and will be delayed by the slew rate ofcurrent sources pm3 or pm4. This delay Ts satisfies

C·T s = _t :::::: 7 ns.

Ie(3.66)

with Ie the current through transistors pm3 and pm'4 in the quiescent state. This Tswill dominate the overall settling time in the latch phase.

3. The clamping of diodes nm4 or nms results in an additional delay. However, at themoment that nm4 or nms becomes active, voltages Yin and Vit2 are close to theirlimits. So, this delay will not be taken into account.

Total settling time for the latch phase of the comparator counts about 8 ns.Figure 3.32 shows the operation of the master comparator. The clock frequency of clock

3.5. A FOLDED CASCODE COMPARATOR

Table 3.5: Parameter summary of the comparator

Parameter Value

Ilnbias 39 JLAIlpbias 40 ItAIlebias 20 JLACM 40 MHzSensitivity <1 mVPc 0.24 mW @ VDD = 3 V

65

signal CM equals 40 MHz. The input signals are crossing ramp voltages with a commonmode voltage of 1.64 V, corresponding to the outputs of the analog preprocessing. Thiscommon mode voltage of the input voltages results in a constant VDS = 0.68 V of currentsource transistor nm3' Parameters of the comparator have been summarized in table 3.5.Pc defines the power dissipation of the comparator. The bias currents can be adjustedaccording to the desired dock frequency, so power dissipation Pc may increase or decrease.The latch phase will be ended with a falling edge of the dock CM: the transconductanceof transistor nm6 will become large compared to gme, so voltages Vin and Vit2 are forcedto the reset level.

The main component of the comparators slave is a flipflop built up with inverters invl andinv2' Output signals Vin and Vit2 ofthe master drive the gates oftransistors nm9 and nmlO. 'Transistors nm9 to rmt12 all have to function as a switch. Because of the flipflop structure,of inverters invl and inv2, one of the outputs of these inverters will be logically '1' and theother will be logically '0'; both outputs '1' or both outputs '0' are illegal conditions. Theslave dock Cs drives the gates of transistors nmll and nm12. Now assume Vit2 to reach itstop most voltage of about 1.59 V (figure 3.32). If at this moment dock Cs has a 0 -+ 1transition, the output of inverter inv2 will he connected to the VSSD node via the seriesimpedance of transistors nm9 and nm12' If the output of inv2 has a logical '0' state, nothingwill happen to the flipflop. However, a logical '1' state at the output of inv2 may be pulleddown to a logical '0' state. For this to occur, the transconductances of transistors nm9 andnm12 will have to he large compared to the transconductance gm of the inverters PMOStransistor (the inverter will he implemented as a standard CMOS inverter, section 3.6.1).With a ~ ratio of the inverters PMOS transistor of only f the transconductance gm of

this transistor equals 245 ~. Inverters inv3 and inv4 are implemented as buffers, sothe behaviour of the flipflop will not be deteriorated by the load of adjoining digital gatecircuits. Figure 3.33 shows the clocking schemes of both master and slave docks CM andCs , the output signals of the master Vitl and Vit2 and the comparators outputs q and nq.

With respect to clocking of the comparator, consider the following:

• The latch phase is initiated with a falling edge of the CM master dock signal;


• The reset phase is initiated with a rising edge of the CM master clock signal;

• Clocking of the master outputs into the slave is initiated with a rising edge of the CS

signal.

Simulations have confirmed, that the comparator can be clocked with an 80 MHz clockfrequency with bias currents and power dissipation numbers given in table 3.5. However,increasing the current in the circuit, sampling rates up to 125 MHz are possible1 2

• Thepositive gradient of the latch signal Vin or Vit2 during settling of the comparator providesinformation about the maximum clock frequency for which a reliable comparator performance can be guaranteed. Measurements will have to confirm whether the bit error rateof the comparators is acceptable for an 80 MHz clock frequency operation. However, theclock frequency of the comparators can be accelerated without a decrease of performanceat the expense of power dissipation.

Simulations have been performed with a 3.3 V supply voltage. It may be expected, thata redesign of the comparator for a supply voltage of 5 V makes even higher sampling frequencies possible. However, this high speed operation will be at the cost of the powerdissipation of the AD-converter.

From figure 3.31 it is clear that the master and slave parts of the comparator have differentpower supplies (VDDA , VDDD and VSSA and V5,S'D)' The digital power supply VDDD willbe easily distorted by the peak currents in the digital encoding logic. Separation of thedigital and analog power supply rails prevents direct influence of the analog preprocessingby the digital circuitry via the power supply lines.

3.5.1 Kickback noise in the comparator

As a result of a large gain in the differential input stage of the comparator, a charge dumpthrough the gate-drain capacitances Ccw of transistors nrnl and nrn2 might deterioratethe input signals Vinp and Vimn. Because of the large number of comparators in a full flasharchitecture, in that case kickback noise might be a serious problem. Two advantages ofthe folding and interpolation architecture are the reduced comparator count and the largenoise margin in a folding signal.Kickback noise will become serious with a large differential voltage Vinp- Vinm. However, theonly important part in a folding signal is its zerocrossing and at the moment of zerocrosslllgthe differential input voltage of the comparator and adjacent comparators will be small.Outside the decision region of the comparator, kickback noise will not result in wrong 0/1decisions. Consider the folding signals in figure 3.34. Figure 3.34 (b) shows a magnificationof the tops of some (differential) folding signals. It can be observed that kickback noiseindeed deteriorates the folding signals. However, figure 3.34 (a) shows some of the foldingsignals around their zerocrossings. Kickback noise pffects are hardly to be observed in this

12The propagation delay of the digital encoding network will become dominant for the maximum dockfrequency of the AD-converter. The propagation delay of the digital network will be covered in section 3.6.

3.5. A FOLDED CASCODE COMPARATOR 67

q

nq

VN(lTl)

Y_N.!!1?L __

CM

CS

::: luNl

DI- L--__UC--__-'- _::: fN) U I 0 I I

:~:::ITJJ 0 0 JJ n J::: rN

) nr-m=rTI ill ill n0.0 50.00 too.On 150.On

25.00 75.00 125.0n

(LIN) T

Figure 3.33: Output signals q and nq of the comparator and master-slave clocking scheme

0.0

LIN) •. Some foldin~ si Is S around the zerocrossing, \ \, '. , \ \\ ,\ \ \

, \, \,

\\

\\,

\,\ \ \ , ,, '. , \,

\ \,

\ \\\

,\

, ,..

,\

\ \ \ ,\ \, \ \.

,\ \ ,

\,,, ..

b. Some foldilli1 si Ials S in the top(LIN)

-300.Om

-312.5m

-12.5m

-287.5m

-25.Om

-275.0m

-325.0m

2.On 2.211 2.4u2.1u 2.3u 2.5u

(LIN)T

Figure 3.34: Influence of comparator kickback noise on the folding signals


figure. Besides, having all comparators to decide at the same common mode voltage canbe remarked an advantageous effect of the folding and interpolation architecture comparedto other (for example full flash-like) AD-converter architectures.

3.5.2 Mismatch in the comparator

Mismatch in the comparator will result in an additional offset with respect to the zerocrossing of a folding signal. Only threshold voltage mismatch will be considered. Accordingto section 3.1.6 K mismatch will be of less importance because of the small currents inthe comparator and the large K factors of the transistors. In the comparator three mainsources of offset can be distinguished:

• An offset (J(~ff1) in the input differential pair transistors nml and nm2;

• An offset (J(~ff2) due to mismatch in the current sources pm l and pm2 ;

• An offset (J(~ff3) due to the latch pair transistors nm7 and nm8.

According to [6] these mismatches satisfy:

( fib' -Ifib' )(W)p ws 2 n ws L nm7 - 1 16 V

1 W -. m."i,!inbias( L )mnl

(3.68)

(3.69)

(3.70)

(3.67)14.7

. / = 2.32 mY,V (W x L)nml

14.7----;:::====xJ(W x L)pml

14.7-----,=.====XJ(W x L)nm7

These three mismatch sources can be modeled in one (J(~ff) for the comparator:

(3.71)

This means, 4(J(~ff) of the comparator is far within the LSB voltage VLSB of one foldingsignal. Because of this area can be considered a 'grey' region with respect to the C0111

parators decision, the comf'trator mismatch will not result in a l~~'Tease of overall systemperformance. Offset eompensation of the comparators mismatch is not necessary to beimplemented. This omission of offset compensation implementation makes the very highdock frequencies of the comparator possible.

3.6 Digital error correction and 5-bit fine encoding

As an introduction to the digital encoding in the AD-converter, first the basic digitalbuilding blocks will be described.

3.6. DIGITAL ERROR CORRECTION AND 5-BIT FINE ENCODING 69

r-------------,

: v[J[~~"·:"~r ~'~:1 I1 q I

1 Cl I

I II II L I

I IL J(al 2-input NAND

r--------------,I vmP-- I1 ,

I a ,

1 1

1 1

1 II q I

1 I

1 ::~~n,nm 1

I vss 1L J

(h) 2-input NOR

r-----------,I ,

;1 · ~ "'" rj~... , ;,

~ ~.ln.mn1 II vss 1

1 1L J

(e) Inverter

Figure 3.35: Implementation of the standard CMOS digital gate circuits

VDDD-------,

q

If-:::-...,-+---<Jna

'----+--I~-.------<Jnb

vssC>---

Figure 3.36: Implementation of the EXOR gate

3.6.1 Implementation of the basic digital building blocks

Digital circuitry in the folding and interpolation AD-converter is constructed with 2/3input NAND gates, 2/3-input NOR gates, inverters and EXOR gates. All gate circuitsexcept the EXOR gate are implemented using standard CMOS logic. The standard CMOSimplementation of the inverter, NAND and NOR gates is shown in figure 3.35. The 2-inputNAND and NOR gates can be extended to 3-input gate circuits by adding additional seriesand parallel transistors.The implementation of the EXOR gate is different from standard CMOS digital circuitry.Consider the transistor implementation of the EXOR gate in figure 3.36. In this figurena and nb are the inverse versions of input signals a and b. The truth table and symbolof the EXOR gate have been shown in the previous chapter, figure 2.11. With two inputsignals four states ab of the input signals are possible: 00,01,10,11. Each of these inputstates is implemented with two transistors in series from VDD or VS'8 to the output nodeq. For instance, both a and b logical '1' will result in a logical '0' of the output q; at thismoment, no other series of two transistors will be able to generate a low impedance pathfr~)lll a supply node to the output node q than the series connection of transistors nml andnm2. All four input states correspond to only one series of two transistors in the circuit.This guarantees a negligible power dissipation in a steady state of the EXOR gate.


n---.-----x i

x-I

Figure 3.37: Implementation of the error correction cell with NAND gates

Table 3.6: Error correction gate transistor dimensions

NMOS PMOSGate type W L M W L M2-input NAND 4 1 1 6 1 13-input NAND 4 1 1 6 1 1inverter 4 1 1 6 1 1

3.6.2 Digital error correction implementation

The 30 sampled folding signals Xl...30 will be manipulated by a digital error correctioncircuit. The digital error correction consists of 30 cells. The inputs of one of those cells arethe sampled folding signal to be corrected (if necessary) and its adjacent sampled foldingsignals. Section 2.5.1 has covered the basic implementation of the error correction. In thissection, the implementation of one error correction cell will be treated.

Consider the logical function from equation 2.5. If two of the input signals are logically'1', the corrected X'i output signal will be '1'. This function can be implemented with thedigital gate circuit from figure 3.37. The inverted output 'iignal X'i is necessary for theadjoining EXOR gates. When implementing 30 of these error correction cells, 29 2-inputNAND gates can be saved.

For example: for the error correction cell generating the x'z signal, the three 2-input NANDgates implement the functions Xl . Xz, Xl . X3, Xz • X3. The cell generating X'3 implements thedigital functions X2 • X3, X2 . X4 and X3 • X4. The 2-input NAND gate implementing X2 • X3 can beshared by both gates.

The transistor dimensions in the error correction gates have been summarized in table 3.6.

3.6. DIGITAL ERROR CORRECTION AND 5-BIT FINE ENCODING

C9

:21~1II~

cl9

cl3

:17~~15~

Figure 3.38: Digital encoding of output bit Bo

71

3.6.3 5-bit fine encoding

The basic principles of the digital fine encoding have been treated in chapter 2. The firstencoding step is generating the Cl...31 signals from XO,Xl' ••. X30' and X31. For this purpose,31 EXOR gates are used.Encoding of the five fine bits, B4B3B2BIBo, will be performed with this Cl...31 code. Table 3.7 summarizes the logical functions necessary to be implemented. The logical functionspresented will be implemented with 2/3 input NAND and NOR gates and inverters. Thesebuilding blocks have been treated in section 3.6.1. The LSB output bit Bo is encoded withits own gate circuits, while the other four output bits B1, B2, B3 and B4 share severalgates in the fine encoder.First the implementation of output bit Bo will be treated. Bo is encoded with the tree-likestructure in figure 3.38. The combination of input signals of the first 2-input NOR stageis arbitrarily. For exampl:-, the two NOR gates performing opeldtions C31 + Cl and C29 + C3

could be reconfigured as C31 + C29 and C3 + Cl without any consequence. The combinationsin figure 3.38 are merely determined by easy layouting of the digital encoder.

Encoding of the other four fine bits B}, B2, B3 and B4 is a little more sophisticated. Thedigital gate count will be decreased by gate sharing in the encoding procedures of these fouroutput bits. First, from the logic expressions in table 3.7 it can be determined which two C

bits always appear together in the expressions for B l , B2, B3 and B4. These combinationsof c bits are encoded to intermediate expressions using 2-input NOR gates. Table 3.8 summarizes which couples of C bits will be combined. Each of the output bits B l , B2, B3 and


Table 3.7: Summary of the 5-bit fine encoding of Cl...3l

Output bit Logical function

Bo (LSB) - Cl +C3 +C5 +C7 +C9 +Cn +Cl3 +Cl5 +Cl7 +Cl9 +-

C2l + C23 + C25 +C27 + C29 +C3l

B l - C2 +C3 +C6 +C7 +ClO +Cll +Cl4 +Cl5 +Cl8 +Cl9 +-

C22 + C23 + C26 + C27 + C30 +C3l

B2 - C4 +C5 +C6 +C7 +Cl2 +Cl3 +Cl4 +Cl5 +C20 +C21 +-

C22 + C23 + C28 + C29 +C30 +C3l

B3 - C8 +C9 +ClO +Cll +Cl2 +Cl3 +Cl4 +Cl5 +C24 +C25 +-

C26 + C27 + C28 +C29 +C30 + C3l

B4 - C16 +C17 + C18 +C19 + C20 + C21 +C22 + C23 +C24 +-

C25 + C26 + C27 + C28 +C29 + C30 + C3l

Table 3.8: Generation of intermediate signals X in the digital fine encoder

Signal name Logic expressionXl C2 +C3

X 2 C4 + C5

X 3 C6 + C7

X 4 C8 +C9

X 5 C10 +Cll

X 6 C12 + C13

X 7 C14 + Cl5

X 8 C1C +C17 I

X 9 C18 + C19

X lO C20 + C21

X n C22 + C23

X 12 C24 + C25

X 13 C26 + C27

X 14 C28 + C29

X 15 C30 + C31

3.6. DIGITAL ERROR CORRECTION AND 5-BIT FINE ENCODING

Table 3.9: Encoding of the X signals to another set of intermediate encoding signals

Signal name Logic expression

Yi X 14 • XISY2 X l2 . X 13

Ys X 6 ,X7

Y4 X s ' X llZ Yi+Y2PI Xl' XIS' X l5P2 Xs ,X7 ,X9

Ps X 2 · X lO

P4 Yi+Y3+Y4Ps X 4 • Xs ' ZP6 Xs ,X9 ·XlO

P7 Xll·Z

73

Table 3.10: Encoding of the output bits Bl, B2 , Bs and B4 from the intermediate signalsY and P

Signal name Logic expressionB I Y4 + PI +P2

B2 ps ' P4

Bs 13 + PsB4 P6 +P7

B4 can be translated to a combination of several X signals. The next step is combinationof intermediate signals X appearing always together in B I , B 2 , Bs and B4 • This resultsin a new set of intermediate digital encoding signals. Table 3.9 shows the encoding of theX signals to this new set of interm~diate signals. Finally, with the intermediate digitalsignals Y and P the desired output bits B ll B 2 , Bs and B4 can be encoded. This finalencoding is summarized in table 3.10. The final output bit encoding of B I , Bs and B4 isperformed by NOR gates with an adjoining inverter. Figure 3.39 shows the digital gatenetwork of the B I , B2 , Bs and B4 output bit encoder.The ltV ,L and M parameters of the transistors in the digital gate circuits are summarized

in appendix A. For easy referencing, all gates in the encoding figures have a label, corresponding with the labels in appendix A.·With a PSTAR simulation, the delay in the fine encoder has been obtained. Figure 3.40


P,~H31 H35 B,P ,

PS~H30 H34 B,Y,

B,P 3

Y,~P I H28 H32 B I

P ,

XI=E)-X 13 H21 P,

X IS

XS=E)-X, Hn P,X,

X'=E)-H23 P,XIOYI=E>-Y, H24 P,Y,

X,~

~,~P,

YI=I:>-H20 ZY,

X8~X, H26 P,XIO

X,,~

Z~P,

X"=C:)-HI6 Y I

x"

X"=E)-HI7 Y,X13

X'=C:)-HI8 Y 3

X,

X'=C:)-HI9 Y,XII

Figure 3.39: Digital encoder of the output bits Bll B27 B3 and B4

3.7. COARSE ENCODING IMPLEMENTATION 75

C31 3.5

0.0BO 3.5

-SOO.OmBl 3.5

-SOO.OmB2 3.5

-SOO.OmB3 3.5

-SOO.OmB4 3.S

-SOO.Om

0.0LOn

2.On3.On

4.OnS.On

6.On7.On

S.On

T

Figure 3.40: Delay in the digital fine encoder including digital error correction circuitry

shows the five fine bits each with a 0---+ 1 transition. Initially, all c bits are logically '0'. Att = 2 ns the signal C31 has a 0 ---+ 1 transition. The delay in the fine encoder equals 2.5ns13. This maximum delay is the delay of output bit B3 . The delay includes the digitalerror correction gate delay.

Output bit Bs is obtained without any additional digital circuitry. The sampled foldingsignal Xo represents the Bs output bit.

3.7 Coarse encoding implementation

The coarse encoding of the output bits B7 (MSB) and B6 (MSB-l) consists of two parts:

1. A number of eight comparators generates the intermediate signals L 1 to L s;

2. Digital encoding logic generates the B7 and B6 output bits and overflow and underflow conditions14 from these intermediate digital signals L and the MSB-2 bit B s.The MSB-2 bit Bs is represented by the output signal Xo of one of the fine comparators. This means that the MSB-2 signal inheres the delay of the analog preprocessing.

13Interconnect and cross capacitances will result in additional propagation delay, so this simulatedencoder delay will increase.

140verflow and undertlow conditions are encoded in the right way within the input voltage range 1.25< Vin < 3. Because of the repetitive structure of the MSB-2 folding signal, out of this region overflow orunderflow encoding might fail (see also section 2.6).


Table 3.11: Reference ladder taps for generation of the intermediate digital signals L

Digital signal Reference tapL1 n22rL2 n26rL3 n14rL4 n18rL5 n30rL6 n34rL7 n9rL8 n38r

By the encoding of the MSB and MSB-1 bits and OVF and UNF signals the MSB-2bit will be used as a synchronization signal.

The comparators will be attached to the same reference ladder as used for the four foldingblocks. Table 3.11 summarizes the reference ladder taps necessary for generation of theL signals. The transition voltage of signal L 7 is different from the transition voltage infigure 2.15. For this implementation, reference tap n8r should have been attached to theL 7 generating comparator. For layout technical reasons, reference tap n9r will be used.This is possible, because of the less severe timing constraints with respect to the signal L 7 .

The encoding of the MSB, MSB-1, overflow OVF and underflow UNF signals with NANDgates, NOR gates and inverters is shown in figure 3.41. The W, Land M parametersof the transistors in the gates have been gathered in appendix A. Logical '1' states ofthe UNF and OVF signals define underflow and overflow conditions. These underflow andoverflow conditions will be used as reset and set input signals of the output flipflops. Allclock signals will be applied externally.

3.8 A positive edge triggered output flipflop

As a result of propagation delay differences in the digital encodiJl~ of the output bits, edgetriggered output latching of the signals BO...7 will be necessary. If this is omitted, largeglitches will occur in the output code. Besides, overflow and underflow signals will haveto clamp the output code to its maximum (255) or minimum (0). For this purpose, eightpositive edge triggered master slave flipflops with set and reset inputs will be implemented.First combinatory logic generates a d.r;r (data-set-reset) signal from the data d input signal,the set and reset inputs. Consider the d.r;1' encoding in figure 3.42. nd.'31' is the invertedversion of the d.r;r signal. This gate circuit implements next digital function:

d.r;1' = (d + .r;et) . re.set. (3.72)

3.8. A POSITIVE EDGE TRIGGERED OUTPUT FLIPFLOP

ViI\ ReferCKeS

77

wmpl

OOII1p2

L1

L1

L2

U

L3

MSB·2

L2

0--,------ MSB

MSB

romp?

t

·_···························· ~

. oomp8 ~ U.

oomI'4

oomp5

oomp6

lA

i4

L5

LS

L6

U.

L7

MSB-2

L3MSB

MSB-2lAo

MSB

MSB-2

L5MSB

MSB·2L6

MSB

XO~MSB-2V ~MSB-2

MSB·l

L8-l~OVFXo--L./

Us_ 115 UNFXo

Figure 3.41: Digital encoding of the MSB and MSB-1 output bits and OVF,UNF signals

d=1 Klset

reset ----------1

}---L- dsr

Figure 3.42: Encoding of the <1.51' signal from data, set and reset inputs


~clk

I ~m?8:-6.'5, L 1

~q

nm 76,5,1,1

nout

.---::=-;-----==--'~-----:::=--:"t-----------=,..."..---.-----=-~-------~,::-:2,1:-::,'-,-,'---<=:J VD~pm_J8~8,11

ds r L.>-----1

Clk~pm_'-:-4---t---+---~

8, D. 8,1

VSS [>----- --- --------_--4- --4---4--------'

Figure 3.43: Standard implementation of the positive edge triggered master slave flipflop

If the reset input has a '1' state, the dsr signal will be forced to '0' anyway. The positiveedge triggered master slave flipflop implementation is shown in figure 3.43. Transistorsnml, pm'l and nm2, pm2 form a simple two inverter flipflop. Outputs q and nq of thismaster flipflop will be steady with a logical '1' state of the elk input. The state of q andnq may change when the elk inputs are '0' according to the following:

dsr . elk =} nq = 1, q = 0;

ndsr . elk =} q = 1, nq = O.

(3.73)

(3.74)

(3.75)(3.76)

The outputs q and nq will be used as input signals of the slave flipflop. Again, transistorsnms, pms and nm6, pm7 form a two inverter flipflop. However, the state of the outputs ofthis slave flipflop out and nout may change with a logical '1' state of the elk. At the risingedge of elk the following should be considered:

• The output signals of the master q and nq become stable anyway;

• Signals q and nq determine the slave outputs out and nout:

q . elk =} out = 1, nout = 0;

nq . elk =} nout = 1, out = O.

The master slave construction ensures that the state of the dsr signal is sampled at therising edge of the elk signal and appears at the out node of the slave flipflop. So, this circuitis said to be positive edge triggered. The final output dout of the circuit is performed byinversion of the nout signal. The transistors of this inverter have ~ ratios of \2 (PMOS)a~ld i (NMOS). These transistor dimensions make the output flipflop capable of dnvingthe load of the long interconnect lines to the bonding pad. Additional output buffers haveto be implemented which are capable of driving the digital output signals off chip.

3.9 Clock buffering, output buffers and DA-converter

The master and slave, coarse and fine clocks have to be generated externally. On-chipclock buffers have been implemented to safeguard 'clean' clock signals as inputs of the ADconverter. The clock buffers are merely standard CMOS inverters with PMOS dimensions

3.10. TIMING DIAGRAM OF THE AD-CONVERTER 79

CLKCM3.3

0.0CLKCS

3.3

0.0CLKFM 3.3

0.0CLKPS

3.3

00CLKDA

3.3

0.0

11ns 60S 5ns 3DS llns

\

\ /I \ I

II / \\ \

/ \ / \ j i

\ \ /\ / \ /

00 9DS

72.0

T

Figure 3.44: Clock signals of the AD-collverter and the DA-converter

~.~ and NMOS dimensions g.~. The non-inverting output buffers have been dimensioned tobe able to drive at least a load capacitance CL = 10 pF. Testing of the chip will result in aload of about 5 pF. The output buffers consist of a cascade of two inverters with increasingdimensions. The first inverter has dimensions ~~ (PMOS) and ~.~ (NMOS). The finalinverter which drives the bonding pad has dimensions ;~~ (PMOS) and ~.~ (NMOS).An 8-bit DA-converter which was available as a C150 cell, has been implemented for easyfunctional testing of the AD-converter. In [19] the architecture and specifications of thisDA-converter type can be found. So, both the output bits and an analog reconstructionof the input signal are available for testing.

3.10 Timing diagram of the AD-converter

A 40 MHz clocking scheme for the AD-converter is shown in £'6ure 3.44. The clock signalfor the DA-converter is shown as well. These dock signals are the signals to be presentedat the IC-pins, so the inverting function of the dock buffers has been taken into account.Rise and fall times of the clock signals are 2 ns. Obviously, the rise and fall times can beless than this 2 ns. Clocking of the AD-converter is possible for clock frequencies up to 80MHz. Shown signals <Lre docking next parts of the circuit:

• eLKeM: Coarse encoding, master comparator;

• eLKC5: Coarse encoding, slave comparator;


• CLI<F M: Fine encoding, master comparator;

• CLI<FS: Fine encoding, slave comparator;

• CLI<DA: DA-converter

It can be observed that the fine clock signals have a delay of 3 ns compared to the coarseclock signals. This delay is due to the analog preprocessing delay and has been estimatedwith simulation results. External tuning of the coarse-fine delay is possible anyway. Theclock signal of the output flipflops will be the internally inverted CLI<CM signal, so theoutput bits are clocked into the output flipflops at the falling edge of the CLI<CM signal15

.

3.11 Simulation of the AD-converter using MILES

A functional test of the AD-converter has been performed with the mixed level MILES simulator. The eight output bits have been reconstructed to an analog signal with a functionalDA-converter building block. In the functional test the AD-converter is clocked with 40MHz. The input signal is a full range ramp signal with a rise time of 6.5 JlS. In figure 3.45the reconstructed output signal is shown. The deviation of this reconstructed output signalfrom an ideal (non-quantized) full range output curve is shown by curve 'DIFFERENCE?16.Although the MILES simulation has been performed with a 40 MHz clock frequency, according to other MILES simulations the AD-converter shows a comparable performance ata 80 MHz clock frequency.

15Clock buffer and circuitry for external controlling of the output flipflop clock have been integrated onthe chip, see chapter 4

16The irregularity in the output curve at t ~ 1.95/lS is a result of a too small rise time of the inputsignal. Functionality of the AD-converter in this region has been rechecked with another simulation andfound to be correct.

3.11. SIMULATION OF THE AD-CONVERTER USING MILES 81

LIN)

V

---~

---v---

-------

V

-----------

-5.Om -t+---+-----'"

-lO.Om

DACOUT 2.9

2.65

2A

2.15

1.9

1.65

1.4DIFFERENCE IO.Om

5.Om

0.0

0.0LOu

2.0u3.Ou

4.Ou 6.Ou5.Ou 7.0u

(LIN)

Figure 3.45: Funetional test of the AD-converter with MILES

Chapter 4

Layout design

In this chapter a few layout topics of the folding and interpolation AD-converter willbe described. The circuit will be implemented in the Philips C150DM CMOS process.Without modifications, processing of this design in the low threshold voltage version ofthis process (CI50LP) is possible.

4.1 Floorplan of the integrated circuit

The folding and interpolation AD-converter has been integrated on one chip together withan eight bit DA-converter. The dimensions of the die are determined by the number ofbonding pads at the outline of the circuit. A 44 pin CLCC1 package will be used for thischip. Considering the 150 JLm pitch of a bonding pad including protection circuit, overallchip dimensions will account 2050 x 2050 JLmz. The actual folding and interpolation ADeonverter will cover only a small part of this. 44 pins are required for test reasons.Figure 4.1 shows the floorplan of the chip. Active AD-converter area covers only 0.6 mmz.Folding blocks F B o and F B z appear merged in the layout on one side of the referenceladder. The differential pairs of these folding blocks have been placed in an alternatingpattern. On the other side of the reference ladder folding blocks FBI and F B 3 have beenplaced in a similar way. The dummy structures of the folding blocks have been placed onthe top and bottom sides. So, the differential pairs that realize the actual zerocrossings areall matched. Besides, the current flow direction is equal in all folding block transistors, aprE'r~quisite for accurate transistor matching. This layout topo10gy has several advantages:little area will be occupied by the reference ladder (polysilicon width, interconnect area)and it has an optimal aspect ratio with respect to the rest of the AD-converter.The other blocks of the analog preprocessing are placed on one side of the folding blocks.The total height of the analog preprocessing equals the height of the 32 fine comparators.This results in a minimal area necessary for the interconnect between analog preprocessingand fine comparators. To enhance the matching between similar circuit blocks, symmetryin the plac~ment of the analog preprocessing blocks can be observed. Furthermore, the

lCLCC = Ceramic Leadless Chip Carrier.

83

84

Bonding Pads:

I. P3BIAS2. PlBlAS3. VSSA-SFNSE4. P2BlAS5. P4BlAS6. PCBlAS7. INBlAS8. VSSA-SFNSE9. AMBlAS10. LNBlASII. lPBlAS12. LPBlAS13. LCBlAS14. YODAIS. DAC-YODA16. ANAOUT17. DAC-VSSA18. Cl!RlN19. LAD2V20. LADOV21. CLKDA22. D723. 0624. 0525. D426. 0327. D228. 0129. 0030. CLKFS31. CLKFM32. CLKCS33. CLKCM34. CVSB35. YOOD36. VSSD37. VSSA38. VIN39. VDDA40. REPHI41. NI4R42. N24R43. N36R44. REPLOW

CHAPTER 4. LAYOUT DESIGN

PB0tPB2PBI+PB3REFERENCE LADDERIV-CONVERTERINTERPOL-IAMPLIFIERINTERPOL-232 PINE COMPARATORSDIGITAL ERROR CORRECTION5 BIT PINE FNCODER8 OUTPUT PLlPPLOPSCOARSE ENCODER +SYNC.ANALOG POWER SUPPLY RAILSDIGITAL POWER SUPPLY RAILSCLOCK BUPPEROUTPUT BUPPERSUBSTRATE BOUNCING DEVICES

Figure 4.1: Floorplan of the chip

4.2. POWER SUPPLY DISTRIBUTION STRATEGY 85

analog part and the digital part of the AD-converter have been separated as much aspossible. Clocks and other digital signals are all routed outside the analog preprocessing.Analog and digital power supply lines have been separated; the transition from analog todigital power supply is at the slave parts of the comparators.The digital part of the AD-converter has been designed in a full custom way. The resultis a very compact digital encoder.The five blocks Z in figure 4.1 can be used for generation of substrate bouncing. Theseblocks are output buffers (Y) with substrate contacts in the NMOS source diffusions. Withrespect to substrate bouncing, pin 34 (CVSB) is of main interest. Three functions can beassigned to this pin by laser cutting the interconnect (INS) on the chip after fabrication:

• VrJDD : default, the CVSB pin will be used as a second digital power supply pin;

• Separate clock input for the output flipflops of the AD-converter;

• Generation of substrate bouncing by the Z devices.

An overview of the IC pin assignment and a test setup of the chip have been summarizedin appendix B.

4.2 Power supply distribution strategy

The layout realization of the power supply rails on the chip can have a substantial influenceon the overall performance of the AD-converter. With respect to the power supply railrealization, consider the following:

• The analog power supply V DDA and the digital power supply VDDD do not have anyon-chip connection. The whole analog preprocessing, including the master parts ofthe comparators will be supplied by the VDDA. The rest of the circuit (slave parts ofthe comparators and digital encoders) will be supplied by VDDD.

• The DA-converter has separate analog power supply pins (DVDDA, DVSSA). Thedigital power supply lines of the AD- and DA-converter are connected on-chip.

• A substrate contact ring senses the substrate voltage round the AD-converter. Thissubstrate ring is connected with the analog V"SA. In this way, substrate and V"SA

are equally distorted. In the analog circuit of the AD-converter only NMOS currentsources are connected with the V"SA supply node except of the latch pair transistorsin the comparators. If the bulk, source and gate voltages of the NMOS currentsource transistors are changed equally, the drain currents of these transistors willnot be affected2

. The gate voltages of the current source transistors will becomedependent of the substrate voltage by connecting capacitors between the bias pins(F1BIAS, F2BIAS, F3BIAS, F4BIAS, FCBIAS, INBIAS, AMBIAS and LNBIAS)and the V"S,sellse pins 3 and 83

. Because of the differential construction of the analog

2This statement is valid as long as the transistor continues to operate in saturation.:1 A prerequisite is that the V.,S,sense bond wires do not conduct any DC current

86 CHAPTER 4. LAYOUT DESIGN

Table 4.1: I ---+ V converter bias currents, power dissipation and harmonic distorsion ofthe AD-converter. Maximum input signal frequency equals 10 MHz

Simulation Inbias [pAl Ipbias [pAl PAD [mW] @ VDD = 3 V THD [dB]LOCALI 30 30 40 < -41LOCAL2 45 45 43.5 < -46LOCAL3 60 60 47 < -51LOCAL4 90 90 54.5 < -57

preprocessing, capacitive currents, for instance due to Cdb of the transistors, will notresult in a substantial decrease of overall system performance. However, mismatchin these capacitances can result in a differential error.

4.3 Local45 layout extractions

The realized layout can be extracted with the CAD-tool Local45. Local45 returns a netlistof the layout including interconnect capacitances and cross capacitances. A simulationof the circuit including these capacitances will result in a reliable overview of the realAD-converter performance. However, layout extractions and simulations have strict limitsas well. The number of parasitic capacitances easily exceeds practical simulation limits.Therefore, Local45 has been used to extract the layout of the analog preprocessing partonly.It is to be expected that the performance of the AD-converter will decrease as a result ofthe interconnect and cross capacitances in the analog preprocessing: especially third-orderdistorsion will become dominant for the AD-converters performance at high-frequency input signals. The dominant role of third-order distortion of the analog part of the systemcan be observed in figure 3.28 as well, but it will be further increased by the additionalcapacitances.A Fast Fourier Transform of the reconstructed AD-converter output signal is shown infigure 4.2. The input signal frequency equals 10 MHz. In this figure four FFT curves havebeen drawn; the difference in these curves is adjustment of the bias currents of the I ---+ Vconverters. Curve LOCALI shows the performance of the AD-converter with I ---+ V converter bias currents from table 3.2. Increasing the bias currents Inbias and Ipbias will increasethe transconductances gmi. As a result the (differential) input and output impedances ofthe I ---+ V converters will decrease. This is favourable for the high frequency operation ofthe analog preprocessing. Curves LOCAL2 , LOCAL3 and LOCAL4 correspond to simulations with increasing I ---+ V converter bias currents. Harmonic dis torsion and powerdissipation PAD of the AD-converter have been summarized in table 4.1. It can be concluded from these simulations, that the maximal input signal frequency the system will

4.3. LOCAL45 LAYOUT EXTRACTIONS 87

-yl-axis

LOCAU-9Ou

.!-95:.-,*3.-.~~LOCAL2-45u._-------~-------_.

LOCAL1 -3Ou- - - --(dB)

10.0

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

-70.0

-80.0

-90.0

-100.0

(LIN)

11\

I

If'. \

It<\\ (l~~t,

I1: ':, .' ....\ ,1['\ if \\ /'1~\ i \\ ! ~ f "\1 fl ~ 'tJj V ,~ f '\ I \, II

¥ V '-./ '<J '-00 f;J

0.01O.0M

20.0M30.0M

40.0M50.0M

60.0M70.0M

80.0M

(LIN) Frequency

Figure 4.2: Distortion of the AD-converter according to Local45 extraction and simulationof the analog preprocessing for various bias conditions of the I ---t V converters. Inputsignal frequency equals 10 MHz

be able to convert with an eight bit performance can be increased easily at the expense ofincreased power dissipation. With the realized integrated circuit, external biasing of theAD-converters building blocks is possible.

Additionally, the entire chip including DA-converter is simulated with a pulse shaped input voltage, corresponding to a 0 ---t 255 transition of the digital output code. Togetherwith the functional MILES simulation of the AD-converter, dracula design rule and layoutversus-schematic checks, Local45 extractions of the AD-converter layout and detailed mismatch analysis and simulations, this test shows that the realized integrated circuit has areasonable chance of success.

Chapter 5

Conclusions

A high speed 8 bit CMOS folding and interpolation AD-converter has heen designed.Considering the design constraints from the introduction, next conclusions can he stated:

• The power dissipation of the AD-converter accounts 40 mW @ VDD=3 V. This number includes the power dissipation of the reference ladder. For operation from asupply voltage of 3 V, the circuit should be processed in the C150LP process.

• The error (offset) correction capability of the two-stage interpolation network solveserrors in the zerocrossings due to device mismatch convincingly. In the prospect ofoffset, the implementation of large transistors in the folding blocks is advantageous.It has been shown that the AD-converter satisfies a 40"(~VT) design with respect tothe differential non-linearity. This means, offset compensation is not necessary tosafeguard a reliable system performance.

• The AD-converter is expected to operate at a maximum clock frequency of 80 MHz.Further increase of the clock frequency will be possible at the cost of of power dissipation. Since clocks and digital signals with frequencies over 80 MHz are difficultto feed through IC pins, in that case clock signals will have to be generated on-chip(PLL) and the output signals of the AD-converter will have to be processed on-chip.Measurements will have to confirm if the hit error rate of the comparators is stillacceptable for an 80 MHz clock frequency.

• The effective resolution bandwidth1 equals 15 .MHz according to 'normal' PSTARsimulations and 9 MHz according to Local45 layout extractions and simulations. Thisdecrease is due to the high internal signal frequencies and additional interconnect andcross capacitances. The zerocrossings of the folding signals are affected around thetops of the input signal. This results in dominant third-order distorsion. However,an increase of the effective resolution bandwidth up to 12 MHz is possihle at theexpense of an increased power dissipation (+14.5 mW) according to section 4.3.

IThe effective resolution bandwidth is defined the maximum input frequency with a 7.5 bit AD-converterperformance.

89

90 CHAPTER 5. CONCLUSIONS

Table 5.1: AD-converter characteristics

System architecture Folding and two-stage interpolationResolution 8 bitInput voltage range 1.4 VDifferential non-linearity < ±0.5 LSBMax. clock frequency 80 MHzEffective resolution bandwidth 9 MHzPower supply 3.3 VPower dissipation 45 mWActive chip area 0.6 mm2

CMOS process C150DMPackage 44 pin CLCC

• The chip area of the folding and interpolation AD-converter accounts only 0.6 mm2•

This is much smaller than any other actual AD-converter with comparable specifications.

Overviewing these AD-converter specifications it can be stated that the folding and interpolation architecture is a very promising approach for the implementation of a high speedlow power and compact CMOS AD-converter. The proposed system can be used as astarting point for the implementation of a 10 bit AD-converter. Besides, operation of theAD-converter at very high clock frequencies offers several possibilities for further researchin video signal processing.Tahle 5.1 summarizes the characteristics of the realized folding and interpolation ADconverter. All conclusions stated have heen hased on layout extractions and simulations.Measurements of the chip will have to confirm the results so far.

Chapter 6

Acknowledgement

The design of the folding and interpolation AD-converter has heen placed in the contextof my graduation at the Eindhoven University of Technology and this project has heenperformed at the Philips Research Lahoratories, Eindhoven.I wish to thank dr.ir. B. Nauta for his support and co-operation during the design processand prof.dr.ir. R.J. van de Plassche for giving me the opportunity to do my graduationproject at the Philips Research Lahoratories.Furthermore I wish to thank dr.ir. M.J.M. Pelgrom for his hints during the design processand ing. J .P.M. Verdaasdonk for his support and tips with respect to MILES simulationsand the software tools in general. Finally, I wish to thank all other members of ResearchGroup Wouda, who have been helpful in this project.

Eindhoven, June 1993

Ardie Venes

91

Bibliography

[1] Wassenaar, R.F. and B. Nauta, 'Analoge CMOS basisschakelingen', Chiptronix consultancy, Almelo, version 1.2, January 1991.

[2] Plassche, R,J. van de, 'High Speed and High Resolution Analog-to-Digital and Digitalto-Analog Converters', Philips Research Laboratories, printed by Eindhoven DrukB.V.1990.

[3] Grift, R.E.,J. van de et al., 'An 8-bit Video ADC Incorporating Folding and Interpolation Techniques', IEEE ,Journal of Solid-State Circuits, vol. 22, no. 6, Dec 1987.

[4] Plassche, R,J. van de and P. Baltus, 'An 8-bit 100 MHz Full Nyquist Analog-to-DigitalConverter', IEEE Journal of Solid-State Circuits, vol. 23, no. 6, Dec. 1988.

[5] Valburg, J. van and RJ. van de Plassche, 'An 8-b 650-MHz Folding ADC', IEEEJournal of Solid-State Circuits, vol. 27, no. 12, Dec. 1992.

[6] Pelgrom, M.J.M. et al., 'Matching properties of MOS Trans'istors', IEEE Journal ofSolid-State Circuits, vol. 24, no. 5, Oct. 1989.

[7] Kasahara, M. et al., 'A CMOS 9 bit 25 MHZ 100 m W ADC for mixed analog/d'igitalLSIs', Proc. IEEE 1991 Custom Integrated Circuits Conference, San Diego, 12-15May 1991. New York: IEEE, 1991. P. 26.7/1-4.

[8] Tsuji, K. et al., 'A CMOS 20 MHz 8 bit 50 m W ADC for mixed analog/digital ASICs "Proc. IEEE 1991 Custom Integrated Circuits Conference, San Diego, 12-15 May 1991.New York: IEEE, 1991. P. 26.3/1-4.

[9] Shiwaku, N. et al., 'A rail-to-rail video-band full NYQ'u'ist 8-bit A/D converter', Proc.IEEE 1991 Custom Integrated Circuits Conference, San Diego, 12-15 May 1991. NewYork: IEEE, 1991. P. 26.2/1-4.

[10] Lewis, S.H. et al., 'A pipelined 9-stage video-rate analog-to-d'igital converter', Proc.IEEE 1991 Custom Integrated Circuits Conference, San Diego, 12-15 May 1991. NewYork: IEEE, 1991. P. 26.4/1-4.

[11] Hosotani, S. et aI., 'An 8-bit 20-MS/s CMOS A/D converter with 50 m W powerconsumption', IEEE Journal of Solid-State Circuits, vol. 25, Feb. 1990.

93

94 BIBLIOGRAPHY

[12] Fukushima, No et al., 'A CMOS 40 MHz 8 b 105 m W two-step ADC', ISSCC Digestof Technical Papers, first edition, 1989.

[13] Hosotani, S. et al., 'A low-power CMOS AjD converter for video applications', Mitsubishi Denki Giho, vol. 65, 1991, p. 50-53.

[14] Matsuura, T. et alo, 'An 8-b 50-MHz 225-mW submicron CMOS ADC using saturationeliminated comparators', Proc. IEEE 1990 Custom Integrated Circuits Conference,Boston, 13-16 May 19900 New York: IEEE, 1990. P. 6.4/1-4.

[15] Song, B. et al., 'A 10-b 15-MHz CMOS recycling two-step AjD converter', IEEEJournal of Solid-State Circuits, vol. 25, Dec. 1990.

[16] Kusumoto, K. et al., 'A lOb 20MHz 30mW Pipelined Interpolating CMOS ADC',ISSCC Digest of Technical Papers, 1993.

[17] Steyaert, M. et aI., 'A 100 MHz 8 bit CMOS interpolating AjD Converter', Proc.IEEE 1993 Custom Integrated Circuits Conference.

[18] Yotsuyanagi, M. et al., 'A 10-b 50-MHz Pipelined CMOS AjD Converter with SjH',IEEE Journal of Solid-State Circuits, vol. 28, no. 3, March 1993.

[19] Pelgrom, M.J.M., 'A 10-b 50-MHz CMOS DjA Converter with 75-f! Buffer', IEEEJournal of Solid-State Circuits, vol. 25, no. 6, Dec. 1990.

[20J Kattmann, K. and J. Barrow, 'A technique for Reducing Differential Non-LinearityErrors in Flash AjD Converters', ISSCC Digest of Technical Papers, 1991, p.170.

[21] Dingwall AoG.F. et al., 'CMOS, lJl) 8b, 50 MHz Averaging Flash AjDC BuildingBlock', ISSCC Digest of Technical Papers, 1992, p.418.

[22] Conroy, CoS.G. et al., 'An 8-b 85-MSjs Parallel Pipeline AjD Converter in l-JlmCMOS', IEEE Journal of Solid-State Circuits, vol. 28, no. 4, April 1993.

Appendix A

Transistor dimensions in the digitalencoders

Table A.1: Coarse encoding

PMOS dimensions NMOS dimensionsGate number Type wp Ip mp wn In lun

J1--J2 2-inp. NAND 6 1 1 4 1 1J3 2-inp. NAND 6 1 1 4.5 1 1J4 INVERTER 6 1 1 4 1 1J5-J8 3-inp. NOR 6 1 1 4 1 1J9-J10 2-inp. NOR 6 1 1 4 1 1.Ill 2-inp. NAND 6 1 1 4 1 1

I

.I12 INVERTER 8 1 1 5 1 1J13 INVERTER 6 1 1 4 1 1.J14-.J15 2-inp. NOR 12 1 1 8 1 1

95

96 APPENDIX A. TRANSISTOR DIMENSIONS IN THE DIGITAL ENCODERS

Table A.2: Encoding of the LSB bit Bo

PMOS dimensions NMOS dimensionsGate number Type wp lp mp wn In mn

GI-G8 2-inp. NOR 6 0.8 1 4 1 1G9-G12 2-inp. NAND 8 1 1 4 1 1G13-G14 2-inp. NOR 8 0.8 1 4 1 1G15 2-inp. NAND 8 0.8 1 4 1 1

Table A.3: Encoding of the bits B4 , B3 , B 2 and B1


HI-H15 2-inp. NOR 6 0.8 1 4 1 1H16-H19 2-inp. NAND 8 1 1 4 1 1H2O 2-inp. NOR 8 0.8 1 4 1 1H21-H22 3-inp. NAND 8 1 1 4 1 1H23 2-inp. NAND 8 1 1 4 1 1H24 3-inp. NOR 8 0.8 1 4 1 1H25-H26 3-inp. NAND 8 1 1 4 1 1H27 2-inp. NAND 8 1 1 4 1 1H28 3-inp. NOR 8 0.8 1 4 1 1H29 INVERTER 8 1 1 4 1 1H30-H31 2-inp. NOR 8 0.8 1 4 1 1H32 INVERTER 8 1 1 5 1 1H33 2-inp. NAND 8 1 1 4 1 1H34-H35 INVERTER 8 1 1 5 1 1

Table A.4: Data-set-reset encoding in the output flipflops


KI-K2 2-inp. NOR 6 1 1 4 0.8 1K3 INVERTER 6 1 1 4 0.8 1

Appendix B

Test setup of the chip

A test setup of the chip is shown in figure B.lo The pin assignment has been summarizedin table B.lo

97

98 APPENDIX B. TEST SETUP OF THE CHIP

~-12 +-L-t----{

~ ~ ~ ~ij~ ij~ ij~ ij;:! § § § § § § §d~ d~ d~ d~ 8 Q a S Q a ~

[J[J[][~][~]G[]G[~]GGVDo8 G D70Uf

VDo8 G~~TOR

vss [J_~~D~IG;gIT.~AL=I~C ~PI;NS~==--G vss

~ ~-"'II"'I!: !::~E~.I:.II.r.I!llllrl I 'i.11 11111I .••. :'•. :1.·1:.1•..·1: .••:.·.:: ~~~ ~;..." + n" .n Hi H.U/ :: : .:.:.: .•.• ·.Y.• •.•• .. :.. :."'.... nl6 ANAOUf;;: ~ :::::::::::::::::::::::::::::::::::::::;.;..... L.:..J

I ~ :•......:•.......:•......:•......:•.......:•.......:•......:•.......:•.....:•.......:•......:•......:•.....:•.....:•......:•.....:.:•...•••....:•..::.::::.~:•.•:..::.:;.•;.~:~ .•..:••....:•.~..:::[..:~ ..•..:: .•[.:::..:•.. :•.::••.•...:•...:..•..:..•.:..:.:.:.: ..:.: •.:•..:..:•..:•...:•..:•..•:•.•.•::..:: .•:::•.•.::•.•:•.•.•.~:!:.: : 11::11:::::::; ~ VDOILJ •• "' L LJ~~~TIr--, .----, ,--,r--. ,,----

Figure B.!: Test setup of the AD-converter chip

Table B.1: IC pin function assignment1 F3BIAS 12 LPBIAS 23 D6 34 CVSB2 F1BIAS 13 LCBIAS 24 D5 35 VDDD3 VSSA-SN 14 VDDA 25 D4 36 VSSD4 F2BIAS 15 DVDDA 26 D3 37 VSSA5 F4BIAS 16 ANAOUT 27 D2 38 VIN6 FCBIAS 17 DVSSA 28 D1 39 VDDA7 INBIAS 18 CURIN 29 DO 40 REFHI8 VSSA-SN 19 LAD2V 30 CLKFS 41 N14R9 AMBIAS 20 LADOV 31 CLKFM 42 N24R

10 LNBIAS 21 CLKDA 32 CLKCS 43 N36R11 IPBIAS 22 D7 33 CLKCM 44 REFLOW

eindhoven university of technology master design of an 8 ...noise analysis of the analog...

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