interfacing with advanced devices

8/13/2019 Interfacing With Advanced Devices

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2

INTRO TO I/O INTERFACE

I/O instructions are IN, INS, OUT, and OUTS

Also isolated (direct I/O or mapped I/O) andmemory-mapped I/O, the basic input and output

interfaces, and handshaking.

Knowledge of these topics makes it easier tounderstand the connection and operation of the

programmable interface componentsand I/O techniques.


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Interfacing Configurations

2 Types

1.Memory mapped I/O

2. I/O mapped I/O (Isolated I/O)

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Interfacing Configurations

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Isolated I/O: uses the dedicated I/O instructions (IN, OUT

and INS, OUTS) and has its own address space for I/Oports (0000H-FFFFH), isolatedfrom the memory addressspace.

Memory mapped I/O: uses memory reference instructions(e.g. MOV). So address space is sharedbetween memoryand I/O (used by only one of them).

Both techniquescanbe used with Intel processors.

But mostIntel-based systems use isolated I/O.


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a. Isolated I/O

Using dedicated I/O

instructions e.g. IN, OUT

b. Memory-mapped I/O

Using ordinary memory

transfer instructions e.g. MOV

64 K I/O bytes

Range of memory addresses

assigned for I/O transfers

Memory: MOV

I/O: IN

Memory

MOV


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Memory Mapped I/O

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Isolated I/O

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I/O devices are treated

separatelyfrom memory

Address 0000 to 00FF is

referred topage 0.

Special instructions exist

for this address range

Byte wide ports

Word wide ports


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Isolated I/O

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The most common I/O transfer technique used in the

Intel-based system is isolated I/O.

Isolated describes how I/O locations are isolated from

memory in a separate I/O address space

Addresses for isolated I/O devices, called ports, are

separate from memory.

Because the ports are separate, theuser can expand the

memory to its full size without using any of memory

space for I/O devices.


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Memory interface

Memory is a device to store data.

To interfacing with memories, there must be:

address bus, data bus and control signals (chip

enable, output enable etc)

To study memory interface, we must learn how to

connect memory chips to the microprocessor and

how to write/read data from the memory


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Block diagram of a memory interface

Data

0000

FFFF

Address

Control signals

Include enable (chip select)

, read/write

Content


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Memory Banking

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INTERFACINGWITHMEMORIES

The figure 1

shows a generalblock diagram of

an 8086 memory

array. In this, the

16-bit wordmemory is

partitioned into

high and low 8-bit

banks on the

upper halves of

the data bus

selected by BHE,

and AO.

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a) ROM and EPROM

ROMS and EPROMs are the simplest memory chips to

interface to the 8086.

Since ROMs and EPROMs are read-only devices, A0 andBHE are not required to be part of the chip enable/select

decoding. The 8086 address lines must be connected to theROM/EPROM chip chips starting with A1 and higher to all the

address lines of the ROM/EPROM chips. The 8086 unused

address lines can be used as chip enable/select decoding. To

interface the ROMs/RAMs directly to the 8086-multiplexedbus, they must have output enable signals. The figure 2

shows the 8086 interfaced to two 2716s. Byte accesses are

obtained by reading the full 16-bit word onto the bus with the

8086 discarding the unwanted byte and accepting the desired

byte. 14


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Different Types of Interrupts

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INTERRUPTS

HARDWARE INTERRUPTS SOFTWARE INTERRUPTS

EXTERNAL

INTERNAL SYSTEM USER-DEFINED

MASKABLE

NON-MASKABLE

DOS INTERRUPTS BIOS INTERRUPTS


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Computer Interrupt

2 General Types of Interrupts:

External- generated outside CPU by other hardware

Internal- generated within CPU as a result of instruction or operation- x86 internals: int, into, divide error, and single step

- trap generally means any processor generated interrupt;

in x86, usually means the single step interrupt

x86 Terminology for Interrupts:

1) Hardware InterruptExternal, uses INTR and NMI control bus lines

2) SoftwareInterruptInternal, from intor into3) Processor Interrupttraps, exceptions


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Classification 8086 INTERRUPTS

256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS

1. TYPE 0 TO TYPE 4 INTERRUPTS-

THESE ARE USED FOR FIXED OPERATIONS AND

HENCE ARE CALLED DEDICATED INTERRUPTS

2. TYPE 5 TO TYPE 31 INTERRUPTS

NOT USED BY 8086,RESERVED FOR HIGHER PROCESSORS LIKE

80286 ,80386 ETC

3. TYPE 32 TO 255 INTERRUPTS

AVAILABLE FOR USER,CALLED USER DEFINED INTERRUPTSTHESE CAN BE H/W INTERRUPTS AND ACTIVATED THROUGH INTR

LINE OR CAN BE S/W INTERRUPTS


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PRIORITY OF INTERRUPTS

INTERRUPT TYPE PRIORITY

INT0,INT3-INT 255,INTO HIGHEST

NMI(INT2)

INTR

SINGLE STEP LOWEST


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Interrupt Vector Table IVT (in memory)

x86 has 256 interrupts, specified by Type Numberor Vector

1 byte of data must accompany each interrupt; specifies Type

Vectoris a pointer(address) into Interrupt Vector Table,IVT

IVT is stored in memory from 0000:0000to 0000:03ffh

IVTcontains 256 far pointer values (addresses)

Far pointer is CS:IPvalues

Each far pointer is address of Interrupt Service Routine, ISR

Also referred to as Interrupt Handler


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IVT Format

Offset

Offset

Offset

Segment

Segment

Segment

Interrupt 0

Interrupt 1

Interrupt 255

0000:0000

0000:0001

0000:00020000:0003

0000:0004

0000:0005

0000:0006

0000:0007

0000:03fc

0000:03fd

0000:03fe

0000:03ff

IP LSB

IP MSB

CS LSB

CS MSB

Given a Vector, where is theISR address stored in memory ?

4Offset Type

Example: int 36h

Offset = (544) = 216= 00d8h


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23Structure of Interrupt Vector Table 8086/88


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Interrupt Service Routine (ISR)

Similar to a subroutine

Attends to the request of an interrupting source Clears the interrupt flag

Should save register contents that may be affected bythe code in the ISR

Must be terminated with the instruction RETFIE

When an interrupt occurs, the MPU:

Completes the instruction being executed

Disables global interrupt enable Places the return address on the stack

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I S i R i (ISR)


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Interrupt Service Routine (ISR)

High-priority interrupts

The contents of W, STATUS, and BSR registers areautomatically saved into respective shadow registers.

Low-priority interrupts

These registers must be saved as a part of the ISR If they are affected

RETFIE [s] ;Return from interrupt

RETFIE FAST ;FAST equivalent to s = 1 If s =1: MPU also retrieves the contents of W, BSR, andSTATUS registers

DOS & BIOS I t d ti


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DOS & BIOS Introduction

INT10Video s ervicesINT13 Disk ServicesINT16Keyboard funct ion sINT17Paral lel pr inter func t ions

BIOS

functions(Basic

Input/

Output

System)

DOS

functions

(Disk

Operating

System)

INT21

keyboard

displaypr interdiskdate/t imememo ry managementprogram cont ro l

Reserved

INTs

DOS F i U i h K b d


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DOSINT 21, function 01H:Wait for Keyboard Input

Specification: waitsfor the user to press a key on the keyboard and

returns the ASCII code.

Input: AH = 01 (function code)

Output: AL = ASCII code of the pressed key. The character is echoed to

the video display

Constrain: doesnt return the control to the main program until a key is

pressed.

If the key correspond to an extended ASCIIcode, AL returns 00. The next

INT 21, function 01 returns in AL the extended ASCII code.

DOSINT 21, function 08H: Console Input without Echo

Specification: similar to function 01 butno echo on video display.

DOS Functions-Using the Keyboard

Ex:MOV ah, 01H; Request keyboard input

INT 21h


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DOSINT 21, function 02H:Display Output

Specification: writes a single character to the display screen, at the current

cursor position.

Input: AH = 02 (function code), DL = ASCII character to be sent to display.

Control characters perform their specific action (0DH = Carriage Return, 0AH

= Line Feed, 08H = Backspace, etc.).

DOSINT 21, function 09H: Display A CHARACTER String

Specification: Send to display a string in the current data segment. The

string ends with $ character (not displayed).

Input: AH = 09 (function code), DX = The offset of the first character in the

string.

Controlling the Video Display

Ex:

String DB Enter your name: $MOV AH, 09h; request display

LEA DX, String; load address

INT 21h

Ex: MOV AH, 02h;request character displayMOV DL, SINT 21h

BIOS F ti U i th K b d


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BIOSINT 16, function 00H: Read keyboard InputSpecification: similar to INT21function 01butif the pressed key

correspond to an extended ASCII code,AL returns 00 andAH returns the

extended ASCII code. No echo to display.

BIOSINT 16, function 01H: Read keyboard status

Specification: doesnt wait. If the keyboard buffer is empty, ZF is set to 1. If

not, returns the first ASCII code from buffer in the same way like function 00,

and clear ZF.

BIOS Functions: Using the Keyboard


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BIOSINT 16, function 02H:Return Shift Flag StatusSpecification: waitsfor the user to press a key on the keyboard and

returns the ASCII code.

Input: AH = 02 (function code)

Output: AL = Status of the special function keys:

B7=Insert, B6=Caps Lock, B5=Num Lock, B4=Scroll Lock (active bit=1

=> function active)

B3=Alt, B2=Ctrl, B1=Left Shift, B0=Right Shift(active bit=1 => button

pressed )

Using the Keyboard(Contd)


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BIOSINT 10, function 00H: Set Video ModeSpecification: set video mode of the display (ex: mode 1 = 25

linesX40 characters,

mode 3 = 25 linesX80 characters).Input: AH = 00 (function code), AL = The desired video mode .

BIOSINT 10, function 0FH: Read Current Video Mode

Specification: returns video mode of the display.Input: AH = 0F (function code)

Output: AL = The current video mode.

Controlling the Video Display(Contd)


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BIOSINT 10, function 02H:Set Cursor Position

Specification: movesthe cursor to specified position (in text mode).

Input: AH = 02 (function code), DH = the row (0-24), DL column (0-79), BH

= page (0)

BIOSINT 10, function 03H: Read the Current Cursor Position

Input: AH = 02 (function code), BH = page (0)

Output: DH = the row (0-24), DL column (0-79)


C t lli th Vid Di l


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BIOSINT 10, function 0AH: Write Character to Screen

Specification: write multiple times a character to screen at current cursor

position.

Input: AH = 0A (function code), AL = ASCII code, BH = page number, CX =

repeat value.

BIOSINT 10, function 09H: Write Character/Attribute to

Screen

Specification: write multiple times a character to screen at current cursor

position. Specify the video attribute of the character: B7 = blink, (B6 = red, B5

= green, B4 = blue)=background, B3 = intensity, (B2 = red, B1 = green, B0 =

blue)=foreground

Input: AH = 09 (function code), AL = ASCII code, BH = page number,

BL = characters attribute, CX = repeat value.



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8259 F t


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8259 Features

8259 is Programmable Interrupt Controller

(PIC)

It is a tool for managing the interrupt requests.

8259 is a very flexibleperipheral controller chip: PIC can deal with up to 64 interrupt inputs

interrupts can be masked individually.

various priority schemes can also programmed.

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8259 Pin Diagram


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8259 Pin Diagram

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Pi D t il


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Pin Details

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I t f i 8259


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Interfacing 8259

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Bl k Di


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Block Diagram

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Working of 8259


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Working of 8259

1. One or more of the INTERRUPT REQUEST lines

(IR0IR7) are raised high, setting the correspondingIRR bit(s).

2. The 8259A evaluates these requests, and sends an

INT to the CPU, if appropriate.

3. The CPU acknowledges the INT and responds with

an INTA* pulse.

4. Upon receiving an INTA* from the CPU group, the

highest priority ISR bit is set and the corresponding

IRR bit is reset.41

W ki f 8259


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Working of 8259

5. Then 8086 will send one more INTA pulse to 8259.

On this second interrupt acknowledge cycle, 8259 will send aninterrupt vector byte of data to the CPU, which is a pointer of the

interrupt to be processed.

5. This completesthe interrupt cycle.

6. The ISR bit is reset at the end of the 3rd INTA

pulse.

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W k fl i id 8259


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Work flow inside 8259

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ICW1 Format

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ICW3 Format This word is read only when there is more than one 8259in

the system and cascading is used, in which case SNGL = 0 in

ICW1.

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ICW4Format

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Operation Command Words (OCWs)

After the Initialization Command Words (ICWs) areprogrammed into the 8259A, the chip is ready to acceptinterrupt requests at its input lines.

However, during the 8259A operation, a selection ofalgorithms can command the 8259A to operate in variousmodesthrough the Operation Command Words (OCWs).

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OCW2 Format


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OCW2 Format

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R, SL, EOI: These three bits control the Rotate and End of Interruptmodes and combinations of the two.

L2, L1, L0: These bits determine the interrupt level acted upon

when the SL bit is active.

OCW3 F t


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OCW3 Format

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8259 Working Modes


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8259 Working Modes

There are 4 different modes for 8259.

1. Fully nested mode.

2. Rotating priority mode.

3. Special mask mode.

4. Polled mode.

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Cascaded Mode


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Cascaded Mode

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Fully nested mode


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Fully nested mode This mode is entered after initialization unless another mode

is programmed.

The interrupt requests are ordered in priority from 0 through 7(0 highest).

When an interrupt is acknowledged the highest priority

request is determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is

set.

This bit remains set until the microprocessor issues an End of

Interrupt (EOI) command immediately before returning fromthe service routine

If AEOI (Automatic End of Interrupt) bit is set, until the trailingedge of the last INTA.

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Rotating priority mode


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Rotating priority mode

In some applications there are a number of

interrupting devices of equal priority.

In this mode, a device after being serviced, receivesthe lowest priority.

So a device requesting an interrupt will have to wait, inthe worst case until each of 7 other devices are

serviced at most once .

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Special mask mode


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Special mask mode Some applications may require an interrupt service routine to

dynamically alter the system priority structure during its

execution under software control.

For example, the routine may wish to inhibit lower priorityrequests for a portion of its execution but enable some of

them for another portion.

That is where the Special Mask Mode comes in.

In the special Mask Mode, when a mask bit is set in OCW1, itinhibits further interrupts at that level and enables interrupts

from all other levels (lower as well as higher) that are not

masked.

Thus, any interrupts may be selectively enabled by loading

the mask register.58

Polled mode


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Polled mode In Polled mode the INT output functions as it

normally does.

The microprocessor should ignore this output.

This can be accomplished either by not connectingthe INT output or by masking interrupts within the

microprocessor, thereby disabling its interrupt input.

Service to devices is achieved by software using aPoll command.

The Poll command is issued by setting P = 1 in

OCW3.59


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Direct memory access


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Direct memory access

Direct memory access (DMA) is a process in which

an external device takes over the control of systembus from the CPU.

DMA is for high-speed data transfer from/to massstorage peripherals, e.g. hard disk drive, magnetic

tape, CD-ROM, and sometimes video controllers.

The basic idea of DMA is to transfer blocks of datadirectly between memory and peripherals.

The data dont go through the microprocessor butthe data bus is occupied.

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Basic process of DMA Minimum Mode


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Basic process of DMA Minimum Mode

The HOLD and HLDA pins are used to receive andacknowledge the hold request respectively.

Normally the CPU has full control of the system bus.

In a DMA operation, the peripheral takes over bus controltemporarily.

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Basic process of DMA Maximum Mode


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Basic process of DMA Maximum Mode

The RQ/GT1 and RQ/GT0 pins are used to issue

DMA request and receive acknowledge signals.

Sequence of events of a typical DMA process:

1. Peripheral asserts one of the request pins, e.g. RQ/GT1or RQ/GT0 (RQ/GT0 has higher priority)

2. 8086 completes its current bus cycle and enters into aHOLD state.

3. 8086 grants the right of bus control by asserting a grantsignal via the same pin as the request signal.

4. DMA operation starts.

5. Upon completion of the DMA operation, the peripheralasserts the request/grant pin again to relinquish buscontrol. 63

DMA controller


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DMA controller A DMA controller interfaces with several peripherals that

may request DMA.

The controller decides the priority of simultaneous DMArequests communicates with the peripheral and the CPU,

and provides memory addresses for data transfer.

DMA controller commonly used with 8086 is the8257/8237 programmable device.

The 8257/8237 is a 4-channel device.

Each channel is dedicated to a specific peripheraldevice and capable of addressing 64 K bytes section of

memory.64

8237 - DMA Controller


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8237 DMA Controller

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8237 Registers


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8237 Registers

1. Current address register

2. Current word register

3. Command register

4. Mode register

5. Request register

6. Mask register

7. Status register

8. Temporary register

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8237 Registers


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8237 Registers

1.Current address register

One 16-bit register for each channel Holds address for the current DMA transfer

2.Current word register

Keeps the byte count Generates terminal count (TC) signal when the count

goes from zero to FFFFH

3.Command register Used to program 8257

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8237 Registers


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8237 Registers4.Mode register

Each channel can be programmed to Read or write

Autoincrement or autodecrement the addressAutoinitialize the channel

5.Request register For software-initiated DMA

6.Mask register Used to disable a specific channel

7.Status register

8.Temporary register

Used for memory-to-memory transfers69

interfacing with advanced devices

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