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Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

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Page 1: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Information Theory Based Parametric Network Consolidation

Team Dark KnightAkhil Singhvi

Anup GaneshAvinash VarmaSushrith Hegde

Vishaal Nagaraja

Page 2: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Motivation

Electricity consumptionof network links > Electricity consumption

of the United Kingdom(2011)Fiber optics, copper cable

0%

10%

20%yearly growth rate

Reduce power consumption of network links.Source: Opportunistically reduce link capacity to save energy Lingwen Gan, Anwar Walid, Steven Low

Caltech, Bell Labs

Page 3: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Packet flow Vs Energy

Capping the packet flow to 5 packets/sec will save

0.9 J or 64.28% of Energy [2]

Source: International Journal of Computer Science & Information Technology (IJCSIT) Vol 3, No 4, August 2011

Packets/Sec Energy Consumption(J)

5 0.5

20 1.4

Page 4: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Packet

Packet

Encrypting

Decrypting

Encoding

Decoding

Processor on NetFPGA

Power Measuring Unit

Power Mgmt. Unit

System Overview

Source: Information theoretic measures for power analysis – Diana Marculescu, Radu Marculescu and Massoud Pedram

Node1

Node2

Node3

Node4

Page 5: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Processor

Power Measuring Unit

Power Management Unit

Threshold

Output QueuesPacket

> Threshold

Packet

< Threshold

Controlling Pkt Flow

Power Monitoring

Page 6: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

OUPUT PORT LOOK UP

INPUT ARBITER

FIFO1

FIFO2

OUTPUT QUEUES

OUTPUT ARBITER

CORE #1 CORE #2

P1 P2

Dual-Core 4-Thread

T1 T2 T3 T4 T1 T2 T3 T4

Page 7: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

PROCESSOR FEATURES

• 5 stage MIPS pipeline

• Custom ISA

• Custom Compiler

• 4 Threads: Fine grain Threading

• NO Hazard Detection Unit or Forwarding Unit

• Saved resources

• Achieved Parallelism

Page 8: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

PC-0

MU

X

INST. MEM AL

U

ID/E

X R

egist

er

FIFO/SRAM

Branch

PC3_next=Branch

Thread_sel

DEMUX

Thread_Sel_next

Multi-thread Processor

EX/M

EM R

egist

er

MEM

/WB

Reg

ister

PC-1

PC-2

PC-3

PC2_next=Branch

PC1_next=Branch

PC0_next=Branch

Control Unit

Reg Bank 0

Reg Bank 1

Reg Bank 2

Reg Bank 3

IF/I

D R

egist

er

thread0add $1,$2,$3

thread1j 10

thread2lw $2,10($0)

thread3 sw $2,10($0)

thread0add $3,$2,$3

$2=1, $3=1$2=1, $3=2

2

11

Page 9: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Future Work

• Use of sophisticated encryption/decryption techniques.

• Threads to be used for additional functionalities.

• Implementation as ASIC • Scale frequency

• Scale Voltage

Page 10: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Evaluation

• Logic functionality Check and Bug Analysis

• Rectify Design

• Compare With The Software Results

Page 11: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

PROJECT TIMELINE

Phase Description Date

Single Core Processor with Multi Threading

04/07/2014

Multi Core Processor with Multithreading

Hardware Accelerators Design

SimulationHardware Accelerators

Individual Implementation

Integration of Hardware Accelerators with

Multicore Processors

Evaluation of the System ( Software )

04/14/2014

05/05/2014

04/21/2014

04/28/2014

05/12/2014

Completed

Completed

In Progress

Completed

Completed

In Progress

Status

Page 12: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

THANK YOU !

Page 13: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Appendix-1Power Measurement

• Power is proportional to

• Activity factor

• Frequency

Reference: Probabilistic Modeling of Frequent Value Bus Encoding Scheme for Low Power Computation by Mehta, K.K. ; Kowar, M. ; Sharma, H.R. Advance Computing Conference, 2009. IACC 2009. IEEE International

Page 14: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Appendix-2Applications

• Disaster recovery in data center.

• Security applications like video surveillance.

• More applications

Page 15: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Appendix-3 Analysis

• Capping the packet flow to 5 packets/sec will

save 0.9 J or 64.28% of Energy

• International Journal of Computer Science & Information Technology (IJCSIT) Vol 3, No 4, August 2011 PERFORMANCE EVALUATION AND IMPACT OF WEIGHTING FACTORS ON AN ENERGY AND DELAY AWARE DYNAMIC SOURCE ROUTING PROTOCOL Jihen Drira Rekik, Leïla Baccouche and Henda Ben

Ghezala RIADI-GDL laboratory, ENSI National school of computer sciences Manouba University, 2010 Manouba, Tunisia ]

Packets/Sec Energy Consumption(J)

5 0.5

20 1.4

Page 16: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

APPENDIX -4 Power Saving Within A Processor

• Major power consuming blocks in a processor are Memory, Register File, and ALU.

• Techniques used to reduce:

• Loopback Mux to reduce the bus transitions.

Page 17: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

Appendix -5 Packet Flow

Encryption

Bus Encoding

Processor

Power Measuring Unit

Power Management Unit

Output Queues

Threshold

Packet

Application

Packet

Packet

Encrypted

Encoded

Page 18: Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

REFERENCES

• [1] Opportunistically reduce link capacity to save energy Lingwen Gan, Anwar Walid,

Steven Low Caltech, Bell Labs