in0 thesis 初稿 - national chiao tung university ·...

國立交通大學電機與控制工程研究所

碩士論文

晶片內部 5-Gbs 低功率脈波訊號傳輸介面

5-Gbs Low Power On-Chip Pulse Signaling Interface

研究生方盈霖

指導教授蘇朝琴教授

中華民國九十六年九月

2



研究生方盈霖 Student Ying-Lin Fang

指導教授蘇朝琴教授 Advisor Chau Chin Su

國立交通大學

電機與控制工程研究所

碩士論文

A Thesis

Submitted to Department of Electrical and Control Engineering

College of Electrical Engineering and Computer Science

National Chiao Tung University

in partial Fulfillment of the Requirements

for the Degree of

Master

in

Electrical and Control Engineering

September 2007

Hsinchu Taiwan Republic of China


i


研究生方盈霖指導教授蘇朝琴教授


摘要

本論文提出一個在晶片內部的脈波傳輸介面來達到 SOC 晶片內的長距離低

功率消耗的傳輸接收電路研究內容包括脈波傳輸端電路脈波接收端電路與晶

片內部的差動傳輸線傳輸端部分實現電容偶合的方式產生脈波訊號經由長距

離的差動傳輸線在接收端同樣利用電容偶合的方式將脈波訊號偶合回接收端電

路設計上首先經由利用較高的傳輸端端電組來將傳送出的脈波訊號振幅提

升並配合提出的傳輸端 de-emphasis 電路架構可將脈波的尾端消除以減少訊

號 ISI 效應接收端則是自偏壓電路將脈波訊號載回接收端共模準位經過放大

及電路將脈波訊號放大後由栓鎖閘將訊號轉回 NRZ 訊號整個傳輸電路在台積電

RF013μm 製程下傳輸 5Gbps 的亂數資料功率消耗在傳輸端 34mW接收端

32mW 總功率消耗 64mW傳輸距離 5mm

關鍵字脈波傳輸電容偶合晶片內部傳輸高速傳輸電路

ii


Student Ying Lin Fang Advisor Chau Chin Su

Department of Electrical and Control Engineering National Chiao Tung University

Abstract

In this thesis we propose an on-chip pulse signaling communication It can be

used for long distance and low power interconnection on SOC The pulse signaling

communication consists of a transmitter an on-chip transmission-line and a receiver

By increase the termination resistance at the near end we can increase the amplitude

of the transmitted pulse signal And then a de-emphasis circuit is employed to reduce

the ISI effect both in the transmitter and in the receiver A TSMC 013um RF process

was utilized in our design In the simulation result 5Gbps signal transmission can be

achieved through a 5mm-length differential interconnect The power consumption at

Tx and Rx are 32mW and 34mW respectively and the total power consumption is

66mW

Keyword AC coupled pulse signaling capacitive coupling on-chip

communication driver receiver de-emphasis equalization

iii

誌謝

首先要感謝我的指導教授蘇朝琴老師感謝老師將近五年時間內從大二基

礎電子學到研究所論文的栽培您費心指導我在實驗室內的所有學習到做研究應

有的精神與態度將陪我進入碩士後的人生旅途

感謝實驗室內煜輝鴻文鴻愷(丸子)仁乾孟昌盈杰等博士班學長

們的指導忠傑緯達(阿達)瑛佑冠羽(KU)柏成(CGU)俊銘(阿銘)順

閔宗諭匡良楙軒智琦冠宇(小冠)等歷屆碩班學長傳授所學汝敏慶

霖(教主)永祥(祥哥)英豪(小馬)議賢村鑫威翔(小潘潘)存遠勇志

(阿伯)季慧雅婷挺毅俊彥繁祥(孔哥)碩廷子俞等同學和學弟妹在

碩班日子的相處和學習依萍俊秀雅雯上容佳琪嘉琳(大姐)志憲(totoro)

等 918 之友在生活上的照顧謝謝你們陪我度過碩班的日子

此外也要由衷感謝蔡中庸老師給予了我兩年碩士生涯的所有助教機會這些

助教收入雖然不至優渥但也等同於一筆獎助學金足夠讓我在研究之餘不至於

太過擔心交大生活上所需的開銷蔡媽妳對教學的熱忱與不放棄任何學生的愛心

在這段期間深深撼動著我也讓我更懂得回饋與感恩

平日研究外的生活兩位家教小妹瑜和宜安妳們給了我很多八九年級生

新穎的想法西洋棋社的 zayinacmonkyy浩浩阿杰mediclightningfox

給了很多棋藝上的切磋電控 16 號家族的鎮源(ican)普暄虹君維祐永遠

忘不了你們給的畢業禮物和家族的溫情室友們宇軒(鯉魚)旻廷依寰(Hubert)

將近五年的朝夕相處感謝你們的包容和帶給我的快樂

最後要感謝老爸老媽爺爺奶奶老哥老妹及女友上容在這段期間內

無盡的鼓勵與支持你們對我付出的關心是永遠報答不完的僅將自己這段時間

的努力與收穫獻給我愛的你們

盈霖 20070904

List of Contents

iv

List of Contents Abstract helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellipii

Acknowledgements helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellipii

List of Contents helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip iv

List of Tables helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip vi

List of Figureshelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip vii

Chapter 1 Introduction 1 11 Motivationhelliphelliphelliphelliphelliphelliphelliphelliphellip1

12 Link Components 3

13 Thesis Organizationhelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip3

Chapter 2 Background Study5 21 High Speed Serial Link Interface helliphelliphelliphelliphelliphelliphelliphelliphellip5

211 PECL Interfacehelliphelliphelliphelliphellip7

212 CML Interfacehelliphelliphellip7

213 LVDS Interfacehelliphelliphellip8

22 AC Coupled Communicationhelliphelliphellip 10

221 AC Coupled Communicationhelliphelliphellip10

222 Typical pulse transmitterreceiver11

Chapter 3 On-Chip Pulse Signaling14 31 Pulse Signaling Schemehelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip15

32 On-Chip Pulse Signaling Analysishelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip 16

33 On-Chip Differential Transmission Linehelliphelliphelliphelliphelliphelliphelliphelliphellip 18

331 Mode of Transmission Linehelliphellip helliphelliphelliphelliphelliphelliphelliphelliphellip 18

332 Geometry Analysis of Transmission Linehelliphelliphelliphelliphelliphellip20

Chapter 4 5Gbps Pulse Transmitter Receiver Circuit Design23 41 Pulse Transmitter Circuithelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip23

411 Voltage Mode Transmitter with De-emphasishelliphelliphelliphellip23

412 The Proposed De-emphasis Circuithelliphelliphelliphelliphelliphellip25

42 Pulse Receiver Circuithelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip28

421 Receiver End Terminationhelliphelliphelliphellip 29

List of Contents

v

422 Self-Bias and Equalization Circuithelliphelliphelliphellip 31

423 Inductive Peaking Amplifierhelliphelliphelliphellip 32

424 Non-clock Latch with Hysteresishelliphelliphellip35

Chapter 5 Experiment39 51 Simulation Setup39

52 Measurement Considerations41

53 Experiment45

Chapter 6 Conclusion47

Bibliography49

List of Tables

vi

List of Tables Table 21 Electrical characteristics of the CMLhelliphelliphelliphellip8

Table 22 Electrical characteristics of LVDShellip9

Table 31 Parasitic RLC of the on-chip transmission linehellip20

Table 51 Specification Tablehellip43

Table 52 Comparison of high speed data communicationhellip45

List of Figures

vii

List of Figures Fig 11 On-chip long distance interconnection2

Fig 12 Basic link components the transmitter the channel and the receiver3

Fig 21 A generalized model of a serial link6

Fig 22 High speed interfacehelliphelliphellip6

Fig 23 (a) output structure of PECL hellip 7

Fig 23 (b) input structure of PECLhellip 7

Fig 24 (a) output structure of CML hellip 8

Fig 24 (b) input structure of CMLhellip 8

Fig 25 (a) output structure of LVDS helliphellip 9

Fig 25 (b) input structure of LVDS hellip 9

Fig 26 (a) AC coupled communication helliphellip 10

Fig 26 (b) pulse waveform in channelhellip 10

Fig 27 Voltage mode transmitter 11

Fig 28 (a) pulse receiver 12

Fig 28 (b) equivalent circuit with enable on 12

Fig 29 Low swing pulse receiver 13 Fig 31 Pulse signaling scheme 15

Fig 32 (a) On-chip pulse signaling model17

Fig 32 (b) Transient response of the transmitterhelliphelliphellip 17

Fig 33 On-chip transmission line as a distributed RLC transmission line 19

Fig 34 (a) Micro-strip structure and the parasitic effect 20

Fig 34 (b) Cross section of the on-chip transmission line 20

Fig 35 Transmission line dimension vs characteristic impedancehellip 22

Fig 36 Transmission line dimension vs parasitic RtotalCtotalhelliphellip 22

Fig 41 Output pulse signal at transmitter with different termination resistance24

Fig 42 Voltage mode transmitter (a) without de-emphasis 25

Fig 42 (b) with de-emphasis 25

Fig 43 Coupled pulse signal with de-emphasis circuit 26

Fig 44 Pulse transmitter26

Fig 45 Pulse Transmitter design flowcharthellip 27

List of Figures

viii

Fig 46 Simulation of coupled pulse signal with de-emphasishelliphellip 28

Fig 47 Receiver end circuit blockhelliphelliphellip 29

Fig 48 Receiver end termination scheme helliphellip 30

Fig 49 Impedance looking from the transmission line to the receiver 31

Fig 410 Receiver end Self-bias and equalization circuithelliphelliphellip 32

Fig 411 Pulse waveform after equalization circuit 32

Fig 412 Receiver end Inductive peaking amplifierhelliphelliphellip 33

Fig 413 (a) Inductive peaking cell 34

Fig 413 (b) Pulse waveform after inductive peaking amplify 34

Fig 414 Gain-Bandwidth plot of inductive peaking amplifier 34

Fig 415 Receiver end Non-clock latch with hysteresis 35

Fig 416 Non-clock latch with hysteresis circuit 36

Fig 417 Simulation of non-clock latch with hysteresis circuit 37

Fig 418 Jitter from the receiver 37

Fig 51 System Architecture 40

Fig 52 Common source circuit connects to pad for output signal measurement 41

Fig 53 System simulation results 42

Fig 54 Corner case simulation results 43

Fig 55 Layout 44

Fig 56 Measurement instruments 46

Chapter 1 Introduction

1


11 Motivation

With the COMS technology grows in recent years there has been a great interest

in SOC design It results in large chip size and high power consumption In

conventional chip design the overall system efficiency depends on the performance

of individual module However with the distance between modules increases the

module-to-module data communication bandwidth becomes an important issue of

SOC design Because the long distance communication not only decays the signal

amplitude but also requires high power consumption to transmit the signal The long

distance on-chip transmission line has a large parasitic resistance and the resistance

has frequency dependence due to the skin effect The large parasitic resistance and

parasitic capacitance make the signal decay greatly Furthermore the power

consumption of an electrical signal in SOC is governed by two components The first

component is due to leakage current and DC path between VDD and GND known as

the static power and the second one is due to switching transient current and short

circuit transient current known as the dynamic power [1] In conventional high speed


2

link design current mode logic (CML) Positive emitter coupled logic (PECL) low

voltage differential signaling (LVDS) are mostly used They all require a current

source to drive the communication data and the current source will increase the power

consumption especially when high speed data is transmitted

In this thesis we will explore the pulse signaling to improve the power efficiency

of long distance on-chip interconnection The pulse signaling method is base on the

fact that the AC component actually carries all the information of a digital signal and

that treat the DC component as redundant The pulse signaling transmits data by using

AC coupled method and that consumes only the dynamic power Therefore the pulse

signaling would reduce the power consumption of the on-chip data communication

Fig 11 On-chip long distance interconnection

Fig 11 shows the high speed data communication in the SOC design The

distance from driver end to receiver end is in the range of 1000um to 5000um The

long distance transmission line goes through the space between modules for saving

chip area In this way a long distance transmission of small area overhead is required

Besides there are also two targets to design this pulse signaling The first is the

structure must be simple and easy for implementation The second is the circuit

should operate at high speed and consume low power for SOC application These

design methodology and much more circuit details will be discussed in the following

chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components

A typical high speed link is composed of three components a transmitter a

transmission line and a receiver Fig 12 illustrates these components At near end

the transmitter converts the digital data into an analog signal stream and sends that to

the transmission line During the signal propagates to the receiver the transmission

line attenuates the signal and introduces noise In order to achieve high data rate and

reduce the distortion a transmission line with low attenuation at high frequency is

required At far end the signal comes into the receiver The receiver must be able to

resolve small input and then amplify the incoming signal After that the receiver

converts the signal back into binary data

Fig 12 Basic link components the transmitter the channel and the receiver

In this thesis we use a pulse form signal stream which known as return-to-zero

(RZ) signaling We also use a differential structure of transmission line to reduce the

common mode disturbance At the far end a receiver with a built-in latch is able to

convert the RZ pulse back into the non-return-to-zero (NRZ) signal Then the

converted NRZ data can be used for further receiver end usage

13 Thesis Organization

This thesis describes a voltage mode pulse transmitter a pulse receiver and an

on-chip transmission line In chapter 2 we study the background of the high-speed

serial link interface and the AC coupled communication Some typical structures are

also introduced in this chapter In chapter 3 the on-chip pulse signaling is present An

Transmitter Receiver

Timing Recovery

Data out Data in

Transmission Line


4

analysis of on chip pulse signaling and an on-chip differential transmission are

discussed Chapter 4 shows the design of the pulse transmitter and the pulse receiver

The experimental results and conclusions are addressed in the last two chapters The

results are also compared with some prior works

Chapter 2 Background Study

5


System on chip (SOC) is the trend of todayrsquos IC design and the high speed

interface [2] [3] between chip modules is an important design issue In the electrical

industry positive-referenced emitter-coupled logic (PECL) current mode logic

(CML) and low voltage differential signaling (LVDS) are the structures commonly

used in high speed link interface design However a current source is required to

produce the IR drop that makes the signal swing The current source not only

consumes the dynamic power but also the static power In order to save more power

AC coupled method is introduced because it only consumes the dynamic power by

coupling pulse mode data Besides with the growing of chip size on-chip

interconnect is also getting more attention as on-chip interconnect is becoming a

speed power and reliability bottleneck for the system In this chapter we will briefly

overview the background of high-speed serial link interface and AC coupled

communication Of course some typical structures are also introduced in this chapter

21 High Speed Link Interface

High speed links for digital systems are widely used in recent years In the

computer systems the links usually appear in the processor to memory interfaces and


6

in the multiprocessor interconnections In the computer network the links are used in

the long-haul interconnect between far apart systems and in the backplane

interconnect within a switch or a router Fig 21 is a generalized structure of a high

speed serial link [4] It consists of a transmitter a transmission line and a receiver

The transmitter side serializes the parallel data and delivers the synchronized data into

the transmission line Timing information is embedded in this serial data which is

sent over a single interconnect The receiver side receives the serial data and recovers

its timing Then the serial data returns to the parallel one

Fig 21 A generalized model of a serial link

As the demand for high-speed data transmission grows the interface between

high speed integrated circuits becomes critical in achieving high performance low

power and good noise immunity Fig22 shows the typical structure of a high speed

interface The interface usually appears in the chip-to-chip high speed data

communication [5] Three commonly used interfaces are PECL CML and LVDS

The signal swing provided by the interface depends on the IR drop on the termination

resistance and that decides the power consumption The signal swing of most designs

is in the range of 300mV to 500mV

Fig 22 High speed interface

Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery

Transmitter Parallel to

Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7

211 PECL Interface PECL [6] is developed by Motorola and originates from ECL but uses a positive

power supply The PECL is suitable for high-speed serial and parallel data links for its

relatively small swing Fig 23 (a) shows the PECL output structure It consists of a

differential pair that drives source followers The output source follower increases the

switching speeds by always having a DC current flowing through it The termination

of PECL output is typically 50Ω that results in a DC current and makes Vop and Von to

be (Vdd-Vov) The PECL has low output impedance to provide good driving capability

Fig23 (b) shows the input structure of PECL It consists of a differential current

switch with high input impedance The common mode voltage is around (Vdd-IR) to

provide enough operating headroom Besides decoupling between the power rails is

required to reduce the power supply noise

Fig 23 (a) output structure of PECL (b) input structure of PECL

212 CML Interface CML [6] [7] is a simple structure for high speed interface Fig 24 (a) shows the

output structure of the typical CML which consists of a differential pair with 50Ω

drain resistors The signal swing is supplied by switching the current in a

common-source differential pair Assuming the current source is 8mA typically with

the CML output connected a 50Ω pull-up to Vdd and then the single-ended CML

output voltage swing is from Vdd to (Vddminus04V) That results in the CML having a

differential output swing of 800mVpp and a common mode voltage of (Vddndash04V) Fig

Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8

24 (b) shows the CML input structure which has 50Ω input impedance for easy

termination The input transistors are source followers that drive a differential-pair

amplifier

Fig 24 (a) output structure of CML (b) input structure of CML

In conclusion the signal swing provided by the CML output is small and that

results in low power consumption Besides the termination minimizes the back

reflection thus reducing high-frequency interference Table 21 [6] summarizes the

electrical characteristics of a typical CML

Table 21 Electrical characteristics of the CML [6]

Parameter min typ max Unit

Differential Output Voltage 640 800 1000 mVpp

Output Common Mode Voltage Vdd-02 V

Single-Ended Input Voltage Range Vddndash06 Vdd+02 V

Differential Input Voltage Swing 400 1200 mVpp

213 LVDS Interface LVDS [6] [8] has several advantages that make it widely used in the telecom and

network technologies The low voltage swing leads to low power consumption and

makes it attractive in most high-speed interface Fig 25 (a) shows the output

structure of LVDS The differential output impedance is typically 100Ω A current

VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

steering transmitter provides Ib (at most 4mA) current flowing through a 100Ω

termination resistor The signal voltage level is low which allows low supply voltage

such as 25V The input voltage range of the LVDS can be form 0V to 24V and the

differential output voltage can be 400mV These allow the input common mode

voltage in the range from 02V to 22V Fig 25 (b) shows the LVDS input structure

It has on-chip 100Ω differential impedance between Vip and Vin A level-shifter sets

the common-mode voltage to a constant value at the input And a Schmitt trigger with

hysteresis range relative to the input threshold provides a wide common-mode range

The signal is then send into the following differential amplify for receiver usage

Table 22 [6] summarizes the LVDS input and output electrical characteristic

Fig 25 (a) output structure of LVDS (b) input structure of LVDS

Table 22 Electrical characteristics of LVDS [6]

Parameter Symbol Cond min typ max UnitOutput high voltage VOH 1475 V Output low voltage VOL 0925 V Differential Output Voltage |Vod| 250 400 mV Differential Output Variation |V od| 25 mV Output Offset Voltage Vos 1125 1275 mV Output Offset Variation |V os| 25 mV Differential Output Impedance 80 120 Ω

Output Current Short together 12 mA

Output Current Short to Gnd 40 mA

Input Voltage Range Vi 0 24 V

Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10

Differential Input Voltage |Vid| 100 mV

Input Common-Mode Current Input Vos=12V 350 uA

Hysteresis Threshold 70 mV Differential Input Impedance Rin 85 100 115 Ω

22 AC Coupled Communication

221 AC coupled communication The AC coupled interface [9] [10] [11] uses pulse signal to transmit data It has

the advantage of less power consumption The AC component actually carries all the

information of a digital signal and thus an AC coupled voltage mode driver can be

used to improve the power consumption because only the dynamic power is presented

Coupling capacitor acts like a high-pass filter that passes the AC component of the

data to the data bus

(a)

(b)

Fig 26 (a) AC coupled communication [12] (b) pulse waveform in transmission line

GND

VDD300mV

GND

VDD 1ns


11

Fig 26 (a) shows the AC coupled communication [12] The transmitter (in chip

1) and the receiver (in chip 4) are connected to the data bus through an on-chip

coupling capacitor Cc at pad Both end of the data bus are terminated by the

impedance matching resistors Z0 with termination voltage Vterm Fig 26 (b) indicates

the waveform of the pulse communication The input full swing data sequence is

coupled to pulse form by the capacitor at the transmitter output The amplitude of the

pulse signal is roughly 300mV at the data rate of 1Gbps The receiver obtains the

pulse mode data through the coupling capacitor and then amplifies the decayed signal

to full swing

222 Typical pulse transmitter receiver Pulse signaling [15] [16] typically uses a voltage-mode transmitter [17] as shown

in Fig 28 The transmitter output is connect to a coupling capacitor and then to the

transmission line Return impedance matching at the transmitter output is provided by

the termination resistor The voltage mode transmitter provides a full swing as well as

high edge rate output to drive the transmission line Without DC current consumption

the voltage mode transmitter consumes less power than a current mode transmitter

Fig 27 voltage mode transmitter

Fig 29 (a) shows the pulse receiver proposed by Jongsun Kim in 2005 [12] The

enable function is design for saving power if the circuit is in the off mode The

equivalent circuit with enable on is shown in Fig 29 (b) The cross-couple structure


12

not only senses the pulse signal but also provides the latch function to transform the

pulse signal into NRZ data

(a)

(b)

Fig 28 (a) pulse receiver (b) equivalent circuit with enable on

Fig 210 shows another low swing pulse receiver proposed by Lei Luo in 2006

[14] The diode connected feedback M1~M4 limits the swing at the out of inverter

Meanwhile M5 also M6 provide a weak but constant feedback to stabilize the bias

voltage making it less sensitive to the input pulses Source couple logic M7~M9

further amplifies the pulse and cross-coupled M11 amp M12 serves as a clock free latch

to recover NRZ data In addition a clamping device M10 limits the swing of long 1rsquos

or 0rsquos and enable latch operation for short pulse which improves the latch bandwidth

The structure is able to receive pulse of the swing as small as 120mVpp


13

Fig 29 low swing pulse receiver

Chapter 3 On-Chip Pulse Signaling

14


This chapter introduces the on-chip pulse signaling It includes the pulse

signaling mathematic model and the geometry of the on-chip differential transmission

line On-chip transmission line [18] [19] has a large parasitic resistance The

resistance is frequency dependent due to the skin effect The large parasitic resistance

and parasitic capacitance make the signal decay greatly [20] Thus a wide line is

required for long distance and high-speed signal transmission However the wider

line and space between lines require more layout area That will increase the costs of

the SOC That is why a low cost and large bandwidth transmission line is desired

Moreover the characteristic impedance of transmission line is also discussed in this

chapter Theoretically impedance matching among the transmitter end the receiver

end and the transmission line is required That can prevent the signal from reflecting

in the transmission line In this thesis a single end termination is implemented The

single termination method can guarantee the signal reflects at most once The

designed termination impedance is 75Ω for less attenuation The width space and

length of the transmission line are 23um 15um and 5000um respectively The

transmission is implemented with Metal 6 and Metal 5 of TSMC RF013um

technology


15

31 Pulse Signaling Scheme

Fig 31 shows the on-chip pulse signaling scheme The transmitter and the

receiver are coupled to the on-chip transmission line through the coupling capacitor

Cctx and Ccrx Transmitter and receiver ends of the data bus are terminated by the

impedance Ztx and Zrx respectively with the terminated voltage Vterm Furthermore the

transmission line acts like the distributed RLC that decays the transmitted data The

coupling capacitor makes it a high-pass filter that transmits the transient part of the

input data The DC component is blocked The pulse signaling method is base on the

fact that the AC component actually carries all the information of a digital signal The

DC component is treated as redundant In this way the pulse data acts as return to

zero signaling (RZ) In contrast to non-return to zero (NRZ) signaling pulse signaling

has been used to reduce the power consumption by only dissipating the dynamic

power at transient time

Fig 31 Pulse signaling scheme

In Fig 31 full swing data is fed into the transmitter input The transmitted data

in the transmission line is a pulse coupled by the coupling capacitor at the transmitter

output After long distance of transmission the received pulse is coupled to the

On-Chip Transmission Line Cascaded Driver Hysteresis Receivers

Full Swing

Coupling Pulse Coupling

Pulse Full

Swing


16

hysteresis receiver by the coupling capacitor as well The receiver end biases the pulse

to the DC common mode voltage of the hysteresis receiver After that the hysteresis

receiver transfers the RZ pulse data to NRZ full swing data

32 On-chip pulse signaling analysis

Fig 32 (a) defines the on-chip pulse signaling model and Fig 32 (b) is the

corresponding transient response of the transmitter Let Zt be the characteristic

impedance of the transmission line Ztx and Zrx the termination resistances at the

transmitter end and receiver end Cctx and Crtx the coupling capacitors Cd and Cg the

parasitic capacitance at transmitter output and receiver input respectively The transfer

function from transmitter output (A) to near end transmission line (B) is

tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)

Equation (31) shows the high-pass characteristic and that HAB(s) is dominated by

tx t ctx d(Z Z )C C in high frequency In other words large coupling capacitor and

termination resistance are better for transferring the pulse signal Moreover the

transfer function from the near end (B) to the far end C) is

crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C

H (s)= C +C1R + sL +( Z )sC sC C

Because Ccrx and Cg are typically in the order of femto-farad (Ccrx+Cg)sCcrxCg ltlt1

and the transfer function becomes

chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17

Equation (32) shows the channel bandwidth is roughly 1RchCch The parasitic

resistance and capacitance of the transmission line limits the channel bandwidth

Furthermore the transfer function from the far end (C) to the receiver input (D) is

gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)

Equation (33) shows that the receiver pulse is proportional to the value of coupling

capacitor (Ccrx )

Fig 32 (a) On-chip pulse signaling model (b) Transient response of the transmitter

Node A

Node B

Vp

Vterm

Vdd

tr td Pulse Width≒ tr + td

(a)

A

B C

D

Z

(b)


18

The step response is important in analyzing the pulse signaling A step input

voltage at node A results in a transient on node C Transforming a square wave into a

short triangular pulse wave on the transmission line The amplitude (Vp) becomes

p eff cV = R I Atx t c

dV= (Z Z )Cdt

(34)

and the voltage value at node B is

eff eff

t-R C

B p termV (t)=V e +V t-t

p term=V e +V (35)

Where eff tx t eff ctx d eff ctx d ctx dR = (Z Z ) 1C = 1C +1C C = C C (C +C ) and eff efft = R C

Equation (34) shows that the amplitude of the pulse is proportional to three parts the

equivalent value of the termination resistance parallel to the characteristic resistance

coupling capacitance and the slew rate at the transmitter output As illustrated in Fig

32 (b) the transmitter needs to provide a large amplitude value of pulse signal for the

decay in the transmission line However after the transition time the transmitted

waveform becomes steady and the coupling pulse decays according to the RC time

constant The pulse width roughly equals to the rise time during the pulse transition

plus the RC decay time If the amplitude is too large it creates the pulse tail and that

leads to the ISI effect This ISI effect not only limits the communication speed but

also increases the jitter at the receiver end In other words large coupling capacitance

and large termination resistance are good for transferring the pulse signal but that also

create the ISI issue In this thesis we bring up an equalization method to reduce the

ISI effect The details will be discussed in the chapter 4

33 On-Chip Differential Transmission Line

331 Mode of Transmission Line As the wire cross-section dimension becomes smaller and smaller due to the

technology scaling down and the wire length increases due to growing in chip size

not only the capacitance but also the resistance of the wire becomes significant

Besides the wire inductance becomes important as well for the faster circuit operating

speed and relatively lower resistance from the new technology The current

distribution inside the conductor changes as the frequency increases This change is

called the skin effect and that results in variations of resistance and inductance value


19

Fig 33 shows the on-chip transmission line When ωL is comparable to R then the

wire should be modeled as a distributed RLC network The frequency dependent

behavior of the transmission line decays the pulse signal in the channel and makes the

amplitude too small to receive at the far end

Fig 33 On-chip transmission line as a distributed RLC transmission line

Fig 34 (a) shows the proposed on-chip differential transmission line which is

fabricated by TSMC 013microm RF technology A co-planar transmission line is placed

in Metal 6 Metal 5 below is reserved for ground shielding A micro-strip structure is

used in GSGSG placing lsquoSrsquo for signal and lsquoGrsquo for ground The ground path is not only

for signal return but also for the ground shielding The transmission line model is

analyzed and extracted to build the distributed RLC parameters by PTM [21] Fig 34

(b) illustrates the cross section of the differential transmission line The total length (l)

of the line is 5mm The line width (w) is 23microm and line-to-line space (s) is 15microm

On-Chip Transmission Line

Characteristic Impedance Z0


20

Fig 34 (a) Micro-strip structure and the parasitic effect (b) Cross section of the

on-chip transmission line

332 Geometry Analysis of Transmission Line

Table 31 shows the data obtained from PTM The dimension is obtained form

the TSMC 013RF technology document The thickness (t) of Metal 6 is 037microm the

height (h) from Metal 5 to Metal 6 is 045microm and the dielectric constant (k) is 39

The total parasitic RLC value divided by the total length of the transmission line

obtains the parasitic RLC in unit length The distributed parasitic parameters are

Rul=2585Ωmm Lul=174nHmm and Cul=30670 fFmm

Table 31 Parasitic RLC of the on-chip transmission line

Dimension RLC ( 5mm ) RLC ( mm ) w = 23microm s = 15microm l = 5000microm t = 037microm h = 045microm k = 39

R = 129259Ω L = 8728nH M12 = 6876 nH M13 = 6183 nH M14 = 5779nH K12 = 0787 K13 = 0708 K14 = 0662

Rul =258518 Ωmm Lul =17456 nHmm Cg =251088 fFmm Cc =27807 fFmm Cul =306702 fFmm

k h w s

Gnd

l

S G S G G t

Ccouple Ccouple Ccoupl Ccouple

S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF

According to the data mentioned above the characteristic impeadance (Z0) of the

transmission line is

0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)

The characteristic impedance of the designed differential transmission is 75Ω Fig 35

shows the relationship between the dimension of the transmission line versus its

characteristic impedance Fig 36 also illustrates the relationship between the

dimension of transmission line versus its parasitic RtotalCtotal which is equivalent to

the bandwidth of the line These two figures tell that smaller width as well as spacing

results in larger characteristic impedance value From (31) we know that it is good

for coupling pulse because the high pass characteristic However small width as well

as spacing results in large parasitic RtotalCtotal which makes the signal decay greatly

On the contrary wider width and spacing of the transmission line results in better

frequency performance of the transmission line But it also requires more layout area

which increases the cost of SOC The design of w=32microm and s=15microm meets the

characteristic impedance of 75Ω And there are three main reasons for this value

Firstly 75Ω of characteristic impedance makes the parasitic RtotalCtotal lt 2E-10

(ΩF) which decay the signal roughly 18dB Secondly 75Ω is close to 77Ω which

theoretically causes minimum attenuation Thirdly the values of the width and

spacing reduce the layout area as well as the costs


22

Fig 35 Transmission line dimension vs characteristic impedance

Fig36 Transmission line dimension vs parasitic RtotalCtotal

40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um

05 1 15 2 25 3 35 4 T-Line Spacing (s) (um)

T-Line Dimension (sw) vs Characteristic Impedance (Z0)

1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um


T-Line Dimension (sw) vs Rtotal Ctotal (ΩF)

Chapter 4 5Gbps Pulse TransmitterReceiver Circuit Design

23

Chapter 4 5Gpbs Pulse TransmitterReceiver Circuit Design

This chapter introduces the pulse transmitter and pulse receiver operating at

5Gbps At the near end we increase the termination resistance for better high-pass

characteristics The equalization circuit built in the transmitter also cuts the pulse tail

and depresses the ISI effect as discussed in chapter 32 At the far end three functions

are required biasing the received pulse to the common mode voltage of the receiver

amplifying the received pulse amplitude and transferring the RZ pulse to NRZ data

These functions are implemented by a self-bias and equalization circuit an inductive

peaking amplifier and a non-clock latch The following sections will discuss these

circuits and their design methodology

41 Pulse Transmitter Circuit

411 Voltage Mode Transmitter In high-speed serial link design the near end typically uses a current mode driver

as discussed in Chapter 2 but the pulse signaling must use a voltage mode driver as


24

shown in Fig 42 (a) The transmitter output is connect to a coupling capacitor (Cctx)

and then to the on-chip transmission line Return impedance matching at the

transmitter output is provided by the termination resistances (Ztx) There are two

advantages to use a voltage mode transmitter rather than a current mode one First the

voltage mode transmitter is much easier to drive the transmission line of high input

impedance Secondly the transmission line loss as well as the high frequency

pass-band characteristic of the transmission line requires a full swing and high edge

rate transmitter output The voltage mode transmitter is quite suit for that Besides the

voltage mode transmitter consumes dynamic power and has no DC current component

on the transmission line That results in less power consumption than a current mode

transmitter Although dynamic supply current will introduce the synchronous

switching noise (SSN) we can add slew rate control circuit or add decoupling

capacitor between power rails to reduce the effect

Fig 41 Output pulse signal at transmitter with different termination resistance

As discussed in Chapter 3 the high pass characteristic of the transmitter passes

the transient part of the input data and blocks the DC signal component Equation (31)

and (34) also implies that we can use a large termination resistor to generate the

better high-pass characteristics Fig 41 shows different values of the termination

resistors and the corresponding pulse signals The larger value of the termination

Ztx -- 1000Ω hellip 150Ω － 75Ω


25

resistance is the larger amplitude of the pulse signal will be delivered The trade off is

that the large termination resistance will introduce a pulse tail within a bit time This

tail not only limits the maximum transmission speed but also increases the ISI effect

In section 412 we introduce an equalization method to solve this problem

412 The Proposed De-emphasis Circuit Fig 42 (b) shows a de-emphasis structure for the equalization The structure

consists of a buffer and a coupling de-emphasis capacitor (Ccde) connected to the

differential node of the transmitter output The main idea is to use the structure to

generate a complementary pulse and add the complementary pulse to the original

signal In this way the output pulse signal at the near end can be describes as

y(n)= x(n)+kx(n) (41)

Fig 42 Voltage mode transmitter (a) without de-emphasis (b) with de-emphasis

Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26

Where x(n) is a full swing data at the last stage of the transmitter x(n)rsquo is the

complement of x(n) and k is a weighting factor which depends on the delay of the

buffer and the value of the de-emphasis capacitor Fig 43 illustrates the circuit

behavior of the transmitter Take the positive terminal for example The Vop is a

positive full swing data at the transmitter output and the x is the coupling pulse The

Von is negative as contrast to Vop The buffer at negative terminal delays the full swing

data And then the de-emphasis capacitor adds the complement pulse xrsquo to the

positive terminal to remove the pulse tail The de-emphasis circuit can reduce the ISI

effect and increase the maximum transmission speed

Fig 43 Coupled pulse signal with de-emphasis circuit

413 Pulse Transmitter Design Flow and simulation results

Fig 44 Pulse transmitter

Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27

Fig 44 shows the pulse transmitter circuit which consists of a series of cascaded

inverters as the driver (last stage of size Ninv) a de-emphasis buffer and the coupling

capacitors The driver uses n cascaded inverters and each one of them is larger than

the preceding stage by a width factor f Then the relationship between the output

loading capacitor (CL) and the driver input capacitance (Cgi) can model to be

n L L

gigi

C Cf = n = log logfCC

rArr (42)

Let the equivalent pull-up resistance (Rpu) and the equivalent pull-down resistance

(Rpd) of the inverter are equal The time constant (τ ) of the first stage is ( Rpu+

Rpd)Cgi2 and total delay (td) becomes fτ (log(CLCgi)logf) Take dtddf=0 can

obtain the best choice of f (usually take f=easymp2~3) And then the loading of the driver

including de-emphasis circuit becomes

CL=fnCgi=Cctx+Cgbufferr (43)

Let the gate capacitance of the buffer is x factor larger than Cgi (Cgbufferr= xCgi) then

the coupling capacitor can be calculated

Cctx=fnCgi-Cgbufferr=(fn-x) Cgi (44)

Fig 45 Pulse Transmitter design flowchart

Slew Rate (or Power Budget ) Decide Ninv

Rising Time of Input Data Decide Td

Equation (44) Decide Cctx

Equation (31) Decide Ztx

Decide Ccde For De-emphasis (Cut Pulse Tail)


28

Besides from equation (31) the proper termination resistance (Ztx) can be

decided Fig 45 shows the design flowchart of the transmitter The buffer delay (Td)

depends on the process and we can obtain the best result by fine tuning the de-couple

capacitor (Ccde) Fig 46 is the simulation of the pulse signal at the transmitter output

with de-emphasis circuit included The diamond eye shows the de-emphasis circuit

cuts the pulse tail and reduces the ISI effect in one data period (200ps) The voltage

swing at the near end is 400mVpp with using a coupling capacitor of 280fF and a

de-emphasis capacitor of 140fF

Fig 46 Simulation of coupled pulse signal with de-emphasis

42 Pulse Receiver Circuit

A pulse receiver is used to transfer RZ pulse into NRZ data Since the coupling

capacitor blocks the DC signal the receiver end needs to bias amplify and then

convert the RZ pulse signal into NRZ data Fig 47 illustrates the receiver end circuit

blocks Because the incoming signal at far end is a short pulse with amplitude smaller

then 50mV a self-bias and equalization circuit is used to bias the pulse to the receiver

common-mode voltage A differential pre-amplify is then connected to amplify the

small pulse After that a non-clock latch with hysteresis has the ability to filter out the

incoming noise from imperfect termination and common-mode disturbances such as

--- Without de-emphasis With de-emphasis


29

ground bounce The recovered NRZ data can then fed to a traditional clock and data

recovery circuit to generate receiver end clock and re-sample the NRZ data

Fig 47 Receiver end circuit block

421 Receiver End Termination

To minimize reflections either or both side of the transmission line should be

impedance matched In this thesis a receiver end termination is implemented

Terminating at the receiver side reduces reflections and allows the transmitter side to

have high-pass behavior as a transmitted pulse encounters the high impedance

transmitter There is reflection noise at the far end transmission line due to the

forward reflection at the un-terminated near end transmission line This forward

reflection noise is absorbed by the far end termination resistor and thus no further

backward reflection noise shown at the near end termination line Fig 48 illustrates

the receiver end termination The Ceq is the equivalent capacitance of the receiver end

coupling capacitor (Ccrx) in serial with the receiver end gate capacitance (Cg) In

general a node capacitance of a digital circuit is roughly 20fF The Ccrx in our design

is 240fF Thus the equivalent capacitance Ceq=CcrxCg(Ccrx+Cg) asymp20fF In other

words the input impedance at receiver end becomes

Driver End 200mV Pulse

Non-Clock Latch With Hysteresis

Self-Bias amp Equalization

CircuitA

Full Swing NRZ Data

Receiver End lt50mV Pulse

5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq

1RsC R R1Z = R = = =1sC 1+ sRC 1+2 fR C jR +sC

π (45)

Where the Rrx is the receiver end termination resistance which is equal to the

characteristic resistance of the transmission line (75Ω) and the magnitude is

rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)

Equation (46) tells that Zrx is equal to Rrx in low frequency range According to

TSMC 013RF technology the maximum rise time (Tr) of a single inverter is roughly

40ps over 12V power rails This means that the edge rate of a pulse signal is fasymp03

Tr =9GHz The termination resistance in our design matches well over the frequency

range including at the data rate (5Gbps) as well as at the signal edge rate (9GHz)

Fig 48 Receiver end termination scheme

Fig 49 shows the simulation results of the impedance matching at the receiver

end Though at high frequencies the parasitic gate capacitance and the coupling

capacitor reduce Zrx the impedance still matches well across a wide frequency range

A

B C

D

ZZrx

Ceq


31

Fig 49 Impedance looking from the transmission line to receiver

422 Self-Bias and Equalization Circuit

Fig 410 shows the self-bias and equalization circuit The circuit not only

automatically generates the receiver end common-mode voltage but also reduces the

low frequency component of the incoming pulse signal As illustrated in the dash line

area an inverter with input connected to output generates the Vdd2 common mode

voltage The common mode voltage is then connected to the receiver differential ends

through two transmission gates The size of the self-bias inverter in our design is the

same as the pre-amplifier in the next stage for the matching consideration Besides

the transmission line has a low-pass response which is due to the skin effect The

low-pass response results in a long tail on the pulse signal If there is no equalization

the tail will cause the ISI effect and reduce the timing margin at the receiver end In

Fig 410 the dotted line area indicates the equalization circuit which consists of an

inverter and a de-emphasis capacitor The circuit de-emphasizes the low frequency

components by generating a small complementary pulse and adding the

complementary pulse to the original signal The output pulse signal of the self-bias

and equalization circuit can be express in

y(n)= x(n)+kx(n)

Impedance Matching (Zrx)

Impedance

Frequency (log) (Hz)


32

Fig 410 Receiver end Self-bias and equalization circuit

Where x(n) is the pulse signal at the output of the self-bias and equalization circuit

x(n)rsquo is the complement of x(n) and k is the weighting factor which depends on the

delay of the inverter and the size of the de-emphasis capacitor Fig 411 shows the

behavior of the circuit with using a coupling capacitor of 240fF and a de-emphasis

capacitor of 5fF

Fig 411 Pulse waveform after equalization circuit

423 Inductive Peaking Amplifier

An inductive peaking amplifier is composed of parallel inverters as the gain

stage with its output connected to an inductive peaking cell as shown in Fig 412 The

main idea of the circuit is to use the inverter gain for signal amplification and the

Self-bias And Equalization Circuit

Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33

inductive peaking for improving the high-frequency performance Fig 413 (a) shows

the inductive peaking cell Each inductive peaking cell consists of a small size

inverter and a resistor The inverter is configured as diode connected by a resistor

which is implemented with a transmission gate as illustrated in Fig 412 The diode

connected inductive peaking cell lowers the output resistance of the inverter and so

does the gain As a result the 3dB frequency increases as the output resistance

decreases At low frequency the output resistance is roughly 1gm while it roughly

equals to the resistance of a transmission gate at high frequency It is intended to

design the resistance of a transmission gate to be larger than 1gm so it increases gain

and extends bandwidth at high frequency

Fig 412 Receiver end Inductive peaking amplifier

In other words the attached inductive peaking cell at the output of the inverter

sacrifices gain but obtains bandwidth to enhance the high-frequency performance

Moreover as illustrated in Fig 413 (b) this circuit not only amplifies the high

frequency component but also depresses the low frequency pulse tail A lightly

transition overshoot due to the inductive peaking results in good performance in the

high frequency part The pulse signal is amplified larger than 200mV and fed into the

hysteresis latch



Pre-amplify With Inductive Peaking


34

Fig 413 (a) Inductive peaking cell (b) Pulse waveform after inductive peaking amplify

Although the inductive peaking cell doesnrsquot have any actual inductor inside the

parasitic capacitance of inverter (Cgdp Cgdn) combining the resistor generates a high

frequency zero that improves the high frequency performance The frequency

response is like adding an inductor This broadband technique is so called the

inductive peaking Fig 414 shows the gain-bandwidth plot of the inductive peaking

amplifier The 3dB bandwidth extends from 388GHz to 113GHz after the inductive

peaking cell is used The receiver sensitivity depends on the equalization as well as

the peaking ability of the amplify stage

Fig 414 Gain-Bandwidth plot of inductive peaking amplifier

No Inductive Peaking f3db=388GHz

Inductive Peaking f3db=113GHz

i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

424 Non-clock latch with hysteresis The non-clock latch transforms the RZ pulse into NRZ data So that the

recovered NRZ data can then be fed to a traditional clock and data recovery circuit to

generate the receiver end clock to re-sample the NRZ data Fig 415 illustrates the

non-clock latch structure established from four inverters and Fig 416 shows its

schematic Via and Vib are the differential inputs and Voa and Vob are their

corresponding differential outputs Two small size inverters are connected back to

back at the differential output to generate the hysteresis range

Fig 415 Receiver end Non-clock latch with hysteresis

As demonstrated in Fig 416 and Fig 417 when the input Via goes from logic

high (H) to the trigger point (Vtrp-) the corresponding output Voa will goes from logic

low (L) to the threshold point (Vth) If we let p =β p ox pminC (WL)μ n =β

n oxCμ nmin(WL) (where micro is the mobility of transistor Cox is the oxide capacitance

and (WL) is the aspect ratio of the transistor) Then the total current flows through

the node Voa becomes

px py nx nyI + I = I + I

- 2 2ddp dd TRP tp p dd tp

V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=

- 2 2ddn TRP tn n tn

V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36

Where X is size of the input inverter and Y is the size of the back to back inverter pair

With the following replacements

1 pB = X β 2 nB = X β 3 dd tpB = (V -V ) 4 tnB =V

2 2dd dd5 p dd tp n tn

V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β

2 21 1 2A = (B - B ) 2 l 2 2 4 1 3 1 2 2 4 1 3A = (B + B )(B B - B B )-(B - B )(B B + B B )

2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0

The trigger point can be solved

[ ] TRP-V = roots( A1 A2 A3 ) (48)

Fig 416 Non-clock latch with hysteresis circuit

Take TSMC 013RF technology for example for X = 3 Y = 1 ddV = 12(V)

2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and

tnV = 403596e - 3(V) we can obtain the trigger point ( TRP-V ) of 05578V The proper

design of X and Y values makes the hysteresis range to filter out the incoming noise

and the interference

Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37

Fig 417 Simulation of non-clock latch with hysteresis circuit

Fig 418 Jitter from the receiver

Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter

Trigger PointOf Latch

VTRP+VTRP

-

Voa

Via

VOL

VOH


38

Inductive peaking amplifier may over peak the pulse signal for some corner

cases especially in the SS corner This is because the resistance of the peaking cell

will change and results in different peak ability Fig 418 illustrates the circuit

behavior of the pulse receiver This over peaking behavior will contribute some jitter

at the receiver end However the hysteresis range of the latch can solve this problem

As long as the peaking amplitude is smaller than the hysteresis range the latch can

ignore the over peaking

Chapter 5 Experiment

39


One prototype chip was designed in TSMC 013RF technology to verify the

research ideas presented in previous chapters The prototype chip contains a voltage

mode transmitter a 5mm long differential transmission line and a pulse receiver

Besides in order to drive the large parasitic capacitance on the output pad open drain

output drivers are used for the receiver differential output In this way the 5Gbps

high-speed data can be measured on the oscilloscope The simulated peak-to-peak

jitter at the pulse receiver output is 437ps The die size of the chip is 884times644microm2

with the power consumption of 34mW at the transmitter end and 32mW at the

receiver end

51 Simulation Setup

A test chip is implemented in TSMC 013microm RF technology The building block

of the system is shown in Fig 51 We apply a sequence of random data to the input

of the voltage mode pulse transmitter The data are transported in pulse mode through

the coupling capacitor (Cctx) to the on-chip transmission line As illustrated in Fig

51 the differential structure of the transmission line is built in Metal 6 and we use


40

Metal 5 as the shielding ground In addition the differential structure of the

transmission line also has the shielding grounds in the arrangement of lsquoGSGSGrsquo

between signal paths The differential scheme has higher immunity to reject noise and

the shielding ground reduces the environmental interference as well as the crosstalk

between signal lines At far end the pulse data is coupled to the hysteresis receiver by

the coupling capacitors (Ccrx) The receiver then transforms RZ pulses signal to NRZ

data

Fig 51 System Architecture

In order to drive a large parasitic capacitance of an output pad open drain output

drivers are used for receiver differential output as shown in Fig52 The package of

the chip is modeled as a pad (C=1pF) connected to a pin (C=1pF) on the printed

circuit board through a pounding wire (L=2nH) Thus the open drain circuit will

introduce a current (Ics) from the outside-chip power supply The current goes through

the impedance matching resistor (50Ω) and drives the large parasitic capacitance on

O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm

Cctx=280fF Cde=140fF

Ccrx=240fF Cde=5fF

Ztx=1000Ω

5mm on-chip differential line with shielding ground

5Gpbs eye

G S G S G

Cross-section of T-Line

M5(G) M5(G)


41

the package One oscilloscope with 100nF bypass capacitor connected to the pin is

used to probe the signal at the chip output Therefore we can observe the eye diagram

on the oscilloscope

Fig 52 Common source circuit connects to pad for output signal measurement

52 Experiment and Results

Fig 53 shows the system simulation results The transmitter end sends the

differential pulse signal with an amplitude of 400mVpp After a 5mm long on-chip

transmission line the pulse amplitude decays to 50mVpp at the receiver front end The

pre-amplifier stage amplifies the pulse amplitude to 400mVpp and fed it to the

hysteresis latch The latch then turns the RZ pulse signal into the full swing NRZ data

After the open drain circuit as discussed in section 51 the oscilloscope can measure

the received data with a swing of 240mVpp Fig 54 shows the eye diagrams at the

receiver output in different process corners The eye diagram of the receiver shows

the peak-to-peak jitter is 437ps (0218UI) in the TT case The worse case takes place

in SS corner and the jitter is 827ps (0413UI)

Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip

Common Source (Open Drain) Connect To PAD

Ics

1pF 50Ω


42

Fig 53 System simulation results

The proposed on-chip pulse signaling is implemented by National Chip

Implement Center (CIC) in TSMC 013RF technology The core area is

5847micromtimes4115microm including a transmitter of 961micromtimes578microm a receiver of

801micromtimes521microm and a 5mm long on-chip transmission line The total area is

884micromtimes644microm as shown in Fig 55 Table 51 lists the chip summary The power

consumption of the transmitter is 34mW and it is 32mW for the receiver at the data

rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43

Fig 54 Corner simulation results

Table 51 Specification Table

Item Specification (unit) Process TSMC 013microm RF Supply Voltage 12V Data Rate 5Gbs channel (at 25GHz) BER lt10-12 Coupling Caps Tx (280+140)fF Rx (240+5)fF Link 5mm and 75Ω on chip micro-strip line Jitter of receiver data (pk-to-pk) 437ps (0218UI) Transmitter End Layout Area 57microm x96microm Receiver End Layout Area 52microm x78microm Core Layout Area 884microm x644microm

Pulse Driver 3402mW Power dissipation Pulse Receiver 3213mW

Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout

Table 52 lists the comparison of the pulse signaling and other on-chip

communications Our work uses TSMC 013RF technology to implement an on-chip

5Gbps pulse signaling The total communication distance is 5mm with a differential

transmission line of width in 23microm and line-to-line spacing in 15microm The line

consumes small area overhead as compares to other on-chip differential lines [22]

[23] Compared to the twisted differential wire method [24] our work uses a wider

width as well as the wider line-to-line space But the twisted differential wire method

has only 40mVpp voltage swing at the far end However our work has full swing data

at receiver output and that can be used for further receiver end usage The power

consumption of the transmitter in our work is 068pJbit and the total power is

132pJbit Our work is the lowest in power consumption

5mm On-Chip Differential Transmission Line

Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45

Table 52 Comparison of high speed data communication

Communication Chip-to-chip On-chip On-chipYear 2005 [12] 2006 [14] 2005 [22] 2006 [23] 2006 [24] This work

Method Pulse Signaling

Pulse Signaling

Differential T-Line

Differential T-Line

Twisted Differential

Wires

Pulse Signaling

Technology 01microm 018microm 018microm 018microm 013microm 013um Data rate 1Gbps 3Gbps 4Gbps 5Gbps 3Gbps 5Gbps

T-Line (microm) - - w=40 s=42

w=40 s=40

w=04 s=04

w=23 s=15

T-Line length 10cm FR4 15cm FR4 2mm 3mm 10mm 5mm Tx Power

(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66

Tx Powerbit (pJbit) 29 167 - 07 05 068

Total Powerbit (pJbit) 56 5 - 13 2 132

53 Measurement Considerations

The whole measurement environment is shown in Fig 56 We use a N4901B

Serial BERT to generate 5Gbps random data and send that into the chip The data pass

through the pulse transmitter on chip transmission line and then into the pulse

receiver The output data of the chip are sent back to the N4901B Serial BERT for the

bit error rate (BER) measurement At the same time the output data are also sent to

an Agilent 86100B for the eye diagram measurement We expect the output data rate

is 5Gbps with 240mV swing and the peak-to-peak jitter of 021UI Besides three HP

E3610A DC Power Supplies are used One is for the output open drain circuit and the

other two are for the transmitter and the receiver power rails The power consumption

is also measured by a Ktythley 2400 Source Meter


46

Fig 56 Measurement instruments

Agilent 86100B Wide-Bandwidth

Oscilloscope

HP E3610A DC Power Supply

(Tx Rx CS)

N4901B Serial BERT 5 Gbps

Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V

Ktythley 2400 Source Meter

Power Measurement

Power Measurement

Bibliography

47

Chapter 6 Conclusion

In this thesis we have proposed a 5Gbps on-chip pulse signaling interface

Different from previous researches of pulse signaling or other on-chip communication

our near end architecture uses a high termination resistor combing the de-emphasis

scheme to reduce ISI effect as well as to increase the maximum data rate At far end

the self-bias circuit the pre-amplifier and the non-clock latch compose the receiver

circuit The self-bias circuit generates the common mode voltage for the receiver such

that the pulse mode data can be received The amplifier stage and the non-clock latch

increase the amplitude of the pulse signal and then transfer the RZ pulse signal into

NRZ data The latch also has an input hysteresis range that can filter out the incoming

noise from imperfect termination and common-mode disturbances such as the ground

bounce The receiver circuit is design in a simple scheme and easy for

implementation

In chapter 3 we have analyzed the pulse signaling as well as the on-chip channel

model We have also designed a 5mm on-chip differential transmission line in our

chip The characteristic impedance of the line is 75Ω to minimize the attenuation

Furthermore the geometry of the line is chosen in the width of 23microm and the spacing

Bibliography

48

of 15microm Our on-chip transmission line has small area overhead as compares to other

works

The simulation results show that the receiver has a peak-to-peak jitter of 407ps

from 12V supply The power consumption of the transmitter is 068pJbit and total

power is 132pJbit This on-chip pulse signaling is fabricated in TSMC 013microm RF

technology The total chip occupies 884micromtimes644microm of area including a transmitter of

57micromtimes96microm a receiver of 52micromtimes78microm and an on-chip transmission line The chip

will be sent back and measured in October 2007

Bibliography

49

Bibliography [1] Hamid Hatamkhani Chin-Kong Ken Yang ldquoPower Analysis for High-Speed

IO Transmittersrdquo IEEE Symposium On VLSI Circuit Digest of Technical Papers pp142-145 Jan 2004

[2] Ramin Farjad-Rad Chih-Kong Ken Yang Mark A Horowitz and Thomas H

Lee ldquoA 04- m CMOS 10-Gbs 4-PAM Pre-Emphasis Serial Link Transmitterrdquo IEEE J Solid-State Circuits VOL 34 NO 5 MAY 1999

[3] Bashirullah R Wentai Liu Cavin R III Edwards D ldquoA 16 Gbs adaptive

bandwidth on-chip bus based on hybrid currentvoltage mode signalingrdquo IEEE J Solid-State Circuits Vol 41 Issue 2 pp 461-473 Feb 2006

[4] Chih-Kong Ken Yang ldquoDESIGN OF HIGH-SPEED SERIAL LINKS IN

CMOSrdquo PhD Dissertation Stanford University California Dec 1998 [5] Kun-Yung Chang ldquoDesign Of A CMOS Asymmetric Serial Linkrdquo PhD

Dissertation Stanford University California Aug 1999 [6] ldquoIntroduction to LVDS PECL and CMLrdquo MAXIM High-FrequencyFiber

Communications Group Application Note HFAN-10 (Rev 0 900) Some parts of this application note first appeared in Electronic Engineering Times on July 3 2000 Issue 1120

[7] Ching-Te Chiu Jen-Ming Wu Shuo-Hung Hsu Min-Sheng Kao Chih-Hsien

Jen Yarsun Hsu ldquoA 10 Gbs Wide-Band Current-Mode Logic IO Interface for High-Speed Interconnect in 018μm CMOS Technologyrdquo IEEE International SOC Conference pp 257-260 25-28 Sept 2005

[8] Mingdeng Chen Silva-Martinez J Nix M Robinson MErdquo Low-voltage

low-power LVDS driversrdquo IEEE J Solid-State Circuits Vol 40 Issue 2 pp 472-479 Feb 2005

[9] Gabara TJ Fischer WC ldquoCapacitive coupling and quantized feedback

applied to conventional CMOS technologyrdquo IEEE J Solid-State Circuits Vol 32 No 3 pp 419-427 March 1997

[10] Kuhn SA Kleiner MB Thewes R Weber W ldquoVertical signal

transmission in three-dimensional integrated circuits by capacitive couplingrdquo IEEE International Symposium on Circuits and Systems Vol 1 pp 37 ndash 40 May 1995

[11] Mick S Wilson J Franzon P ldquo4 Gbps High-Density AC Coupled

Interconnectionrdquo Custom Integrated Circuits Conference pp 133 ndash 140 May 2002

[12] J Kim I Verbauwhede and M-C F Chang ldquoA 56-mW 1-Gbspair pulsed

signaling transceiver for a fully AC coupled busrdquo IEEE J Solid-State Circuits vol 40 no 6 pp 1331ndash1340 Jun 2005

[13] Mick S Luo L Wilson J Franzon P ldquoBuried bump and AC coupled

interconnection technology rdquoIEEE TRANSACTIONS ON ADVANCED PACKAGING VOL 27 No 1 Feb 2004

Bibliography

50

[14] L Luo J MWilson S E Mick J Xu L Zhang and P D Franzon ldquoA 3 Gbs

AC coupled chip-to-chip communication using a low swing pulse receiverrdquo IEEE J Solid-State Circuits Vol 41 No 1 pp 287-296 Jan 2006

[15] Min Chen and Yu CaordquoAnalysis of pulse signaling for low-power on-chip

global bus designrdquo Proceedings of the 7th International Symposium on Quality Electronic Design Mar 2006

[16] Jongsun Kim Jung-Hwan Choi Chang-Hyun Kim Chang AF Verbauwhede

I ldquoA low power capacitive coupled bus interface based on pulsed signalingrdquo Custom Integrated Circuits Conference pp 35 ndash 38 Oct 2004

[17] Gijung Ahn Deog-Kyoon Jeong Gyudong Kim ldquoA 2-Gbaud 07-V swing

voltage-mode driver and on-chip terminator for high-speed NRZ data transmissionrdquo IEEE J Solid-State Circuits Vol 35 Issue 6 pp 915-918 June 2000

[18] Gomi S Nakamura K Ito H Sugita H Okada K Masu K ldquoHigh speed

and low power on-chip micro network circuit with differential transmission linerdquo International Symposium on System-on-Chip pp 173-176 Nov 2004

[19] Chang RT Talwalkar N Yue CP Wong SS ldquoNear speed-of-light

signaling over on-chip electrical interconnectsrdquo IEEE J Solid-State Circuits Vol 38 Issue 5 pp 834-838 May 2003

[20] So Young Kim ldquoModeling And Screening On-Chip Interconnection

Inductancerdquo PhD Dissertation Stanford University California July 2004 [21] httpwww-deviceeecsberkeleyedu~ptm [22] Ito H Sugita H Okada K Masu K ldquo4 Gbps On-Chip Interconnection

using Differential Transmission Linerdquo Asian Solid-State Circuits Conference pp 417-420 Nov 2005

[23] Takahiro Ishii Hiroyuki Ito Makoto Kimura Kenichi Okada and Kazuya

Masu ldquoA 65-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180 nm CMOS Technologyrdquo IEEE A- Solid-State Circuits Conference pp131-134 Jul 2006

[24] Danieumll Schinkel Eisse Mensink Eric A M Klumperink Ed (A J M) van

Tuijl and Bram Nauta ldquoA 3-Gbsch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnectsrdquo IEEE J Solid-State Circuits vol 41 no 1 pp 297ndash306 Jan 2006

2



研究生方盈霖 Student Ying-Lin Fang

指導教授蘇朝琴教授 Advisor Chau Chin Su

國立交通大學

電機與控制工程研究所

碩士論文

A Thesis

Submitted to Department of Electrical and Control Engineering

College of Electrical Engineering and Computer Science

National Chiao Tung University

in partial Fulfillment of the Requirements

for the Degree of

Master

in

Electrical and Control Engineering

September 2007

Hsinchu Taiwan Republic of China


i




摘要












ii




Abstract










66mW



iii

誌謝























盈霖 20070904

List of Contents

iv


























List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















i




摘要












ii




Abstract










66mW



iii

誌謝























盈霖 20070904

List of Contents

iv


























List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















ii




Abstract










66mW



iii

誌謝























盈霖 20070904

List of Contents

iv


























List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















iii

誌謝























盈霖 20070904

List of Contents

iv


























List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















List of Contents

iv


























List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















List of Contents

v






53 Experiment45


Bibliography49

List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















List of Tables

vi






List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















List of Figures

vii






























List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















List of Figures

viii



















Fig 55 Layout 44



1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















1


11 Motivation
















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















2




















chapters

TX

RX

Module 1

Module 2

Module 3

Module 4

SOC


3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















3

12 Link Components






















Timing Recovery

Data out Data in

Transmission Line


4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















4






5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















5



















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















6



















Serial to Parallel

Receiver N

N

Phase Lock Loop

Clock Recovery


Serial

Transmission Line

IR~300-500mV

Iout

D

D

ZL

RT-T RT-R

ZL

I

Chip1

Channel

Chip2

Gnd

Vdd

Gnd

Vdd


7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















7




















Von Vop D D

(a) (b)

Vop

Von

D

RI

D


8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















8



amplifier
















VonVop

50Ω50Ω

Vdd

VonVop

50Ω 50Ω

Vip

Vin

Vdd

(a) (b)


9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















9

















Vo

Vip Vin

(a) (b)

Vocm Von Vop

Ib

Ib

Vin

Vip Vin

Vip


10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















10











(a)

(b)


GND

VDD300mV

GND

VDD 1ns


11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















11









to full swing












12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















12



(a)

(b)











13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















13



14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















14


















technology


15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















15



















Full Swing


Pulse Full

Swing


16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















16











tx tctx tx t

AB

tx t tx td ctx ctx

1 +(Z Z )sC (Z Z )H (s)= 1 1 1+ +(Z Z ) +(Z Z )

sC sC sC

times

tx t ctx d

tx t ctx d ctx d

(Z Z )C C s=(Z Z )C C s+(C +C )

(31)





crx grx

ch crx gBC

crx gch ch rx

ch crx g

C +C1( Z )sC sC C




chrx

BC

ch ch

chrx

1( )1sC +ZH (s) 1R + sL +( )1sC +

Z

asymp (32)


17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















17




gCD

crx g

1sC

H (s)= 1 1+sC sC

crx

crx g

C=C +C

2 ch ch

ch ch ch chrx rx

1= L RC L s +(R C + )s+( +1)Z Z

(33)


capacitor (Ccrx )


Node A

Node B

Vp

Vterm

Vdd


(a)

A

B C

D

Z

(b)


18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















18





dV= (Z Z )Cdt

(34)


eff eff

t-R C


p term=V e +V (35)
























19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















19

















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















20














k h w s

Gnd

l

S G S G G t


S G SG G

Gnd

Cground Cground

Metal 6

Metal 5

(a)

(b)


21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















21

Cc = 125544 fF Cg = 139035 fF Ct = 153351 fF



0ul ul

ul

R j LZj C

ωω+

=

ul

ul

LC

cong (36)


















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















22



40

50

60

70

80

90

100

110

120

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Z 0 (Ω

)05um

1um

2um

6um

4um

w=23um



1E-10

15E-10

2E-10

25E-10

3E-10

35E-10

4E-10

45E-10

5E-10

55E-10

6E-10

50E-07 10E-06 15E-06 20E-06 25E-06 30E-06 35E-06 40E-06

T-Line Spacing (m)

Rto

tal

Cto

tal (Ω

F) 05um

1um

2um

6um

4um

w=23um




23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















23















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















24






















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















25










y(n)= x(n)+kx(n) (41)


Cctx

Ninv

Ztx

Cctx Ccde

Ninv

Ztx


26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















26













Td

Data

Coupling Pulse

Vop

Von

Pulse x

xrsquo

y


27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















27






n L L

gigi


rArr (42)

















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















28





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















29





















CircuitA

Full Swing NRZ Data


5mm

Pre-amplifier

gt200mV Pulse

A


30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















30

rxeq rx rx

rx rxeq eq rx eq

rxeq


π (45)



rxrx rx2 2

rx eq

RZ = R1 +(2 fR C )π

asymp (46)










A

B C

D

ZZrx

Ceq


31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















31


















y(n)= x(n)+kx(n)


Impedance



32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















32






capacitor of 5fF







Pre-amplify Stage


x

xrsquo

y

x

xrsquo

y

Td


33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















33


















hysteresis latch





34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















34













i OC gdp

C gdnR

200ps

lt50mVPulse

gt200mV Pulse

(a) (b)


35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















35

















V1 1X [(V -V )-V ] + Y [(V - ) -V ]2 2 2

β β=


V1 1= X (V -V ) + Y ( -V )2 2 2

β β (47)


Pre-amplify Stage



36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















36





V VB = (Y [(V - )-V ] +Y ( -V ) )2 2

β β


2 2

3 1 3 2 4 5A = (B B ) -(B B ) - B

(47) becomes

- 2 -

1 TRP 2 TRP 3A (V ) + A (V )+ A = 0


[ ] TRP-V = roots( A1 A2 A3 ) (48)



2p = 15166e - 3 (AV )β 2

n = 18198e - 3 (AV )β tpV = 403817e - 3 (V) and




Voa

Vob

Via

Vib

HrarrVTRP-

LrarrVth

X

Y


37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















37



Data

Ideal Pulse

Over Peaking

Vp

Vp

Vp

Vp Jitter


VTRP+VTRP

-

Voa

Via

VOL

VOH


38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















38









39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















39










receiver end

51 Simulation Setup







40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















40







data








O

OCcr Rx

Zrx=75Ω Vterm

D

D

Tx

C ct

Ztx Vterm


Ccrx=240fF Cde=5fF

Ztx=1000Ω


5Gpbs eye

G S G S G


M5(G) M5(G)


41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















41



on the oscilloscope













Vpp= Ics x 50 PAD

Buffer Receiver

50Ω

Oscilloscope

100nF

PIN2nH

1pF

div Ldt

=

Inside Chip


Ics

1pF 50Ω


42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















42








rate of 5Gbps

400mVpp

~240mV

Full Swing

Rx after Pre-Amp

400mVpp

50mVpp

Input Data

Tx Pulse

Rx Pulse

400mVpp

~240mV

Full Swing

Latch

Oscilloscope


43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















43





Total 6615mW

TT 437ps (0218UI)

FF 296ps (0148UI)

FS 525ps (0262UI)

SF 497ps (0248UI)

SS 827ps (0413UI)


44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















44

Fig 55 Layout













Tx

Rx

gndtx

vip

vddtx

vddrx

vpon vpop

vbrx

gndrx

gndcs

884um

vin vbtx

Decouple Cap

644um


45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















45




Pulse Signaling

Differential T-Line

Differential T-Line


Wires

Pulse Signaling



w=40 s=40

w=04 s=04

w=23 s=15


(mW) 29 5 317mA 35 - 34

Rx Power (mW) 27 10 24mA 3 - 32

Total power (mW) 56 15 - 65 6 66















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50





















46



Oscilloscope


(Tx Rx CS)


Input [vipvin]

Output [vpopvpon]

BER Measurement

Jitter Measurement

Supply 12V0V


Power Measurement

Power Measurement

Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















Bibliography

47













implementation





Bibliography

48


works







Bibliography

49

























Bibliography

50




















Bibliography

48


works







Bibliography

49

























Bibliography

50




















Bibliography

49

























Bibliography

50




















Bibliography

50




















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