implementing digital lock-in amplifiers using the dspic dsc

AN1115Implementing Digital Lock-In Amplifiers Using the dsPIC® DSC

INTRODUCTIONLock-in amplifiers use phase-sensitive detection tomeasure the presence of small signals buried in largeamounts of noise. By measuring the coherent systemresponse from an incoming AC signal, the digital lock-in amplifier can detect even minute changes. Bothmagnitude and phase can be used to characterize thesystem.

Conventionally, lock-in amplifiers use complicated (andexpensive) analog circuitry to perform the phase-sensitive detection and filtering. However, modernDigital Signal Controllers (DSCs), such as thedsPIC30F and dsPIC33F families, can be used toremove large amounts of the analog circuitry byperforming the necessary operations in software. Thiscapability provides a number of additional benefitsincluding increased reliability, resistance totemperature and aging effects, and the ease with whichthe system can be modified in the field. By using thebuilt-in signal processing capabilities of the dsPIC33F,it is possible to perform high-speed, high-accuracymeasurements on sensors such as strain gauges. Thesame technique can be applied to other noisy systemssuch as capacitive sensors or the measurement ofmodulated light levels.

While the basic process is conceptually simple, thereare a number of possible ways of implementing it in amicrocontroller, and the implementation details arefrequently missing from existing published material.

This application note provides information on practicalways in which a digital lock-in amplifier can beimplemented in software using thedsPIC33FJ256GP710 on an Explorer 16 board. Thisapplication note also considers a number ofperformance enhancements that can dramaticallyreduce the processing requirements. Source code isprovided that will execute on the Explorer 16 board(see Appendix A: �Source Code�).

THEORYA lock-in amplifier can measure small AC signals ofonly a few nanoVolts even in the presence of noisesources of much greater amplitude. They do this byusing a Phase Sensitive Detection (PSD) circuit that

can discriminate a single frequency of interest bycomparing the incoming signal's phase and amplitudeto a reference signal. Signals from interfering sourcesthat do not have the same frequency and phaserelationship to the reference are rejected by the PSD.

To illustrate why this technique is useful, consider theexample of a 100 nV sine wave with a frequency of40 kHz. It would be difficult to measure this signaldirectly, so some amplification is necessary. Equation 1shows the resulting output signal, assuming that theamplifier has a gain of 1000.

EQUATION 1:

However, any amplifier adds noise to the signal. A goodcircuit will add around .

Assuming the amplifier in this example has abandwidth of 200 kHz, the circuit will also addbroadband noise equal to that of Equation 2.

EQUATION 2:

In other words, after amplification, the noise level willbe 22 times the signal level at the desired frequency.

It is possible to precede the amplifier with a band passfilter centered at 40 kHz. But even a very high qualityanalog filter will only have a Q factor of 100.

Such a Q factor would still give a noise signal as shownin Equation 3.

EQUATION 3:

This 100 µV signal is still difficult to measure relative tothe noise. However, because a Phase SensitiveDetector can have a Q as high as 10,000, the noisesignal in our example could be reduced to only 10 µV,making it possible to perform measurements on theoriginal signal.

Author: Darren WennMicrochip Technology Inc.

Note: Q, which is referred to as the quality factor,is equal to the center frequency of a signaldivided by its bandwidth at the half powerpoint and describes how �tight� a filter is.

1000 100nV× 100μV=

5nV Hz⁄

5nV 1000× 200kHz× 2.2mV=

5nV 1000× 40kHz Q⁄× 100μV=

where Q = 100

© 2007 Microchip Technology Inc. DS01115A-page 1

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Phase Sensitive DetectorsPhase Sensitive Detectors are common signalprocessing elements that are often used to demodulatea signal�s frequency from its fixed-frequency carrier. Iftwo signals are multiplied together, basic physicsdictates that the result will be a signal consisting of thesum and difference of the two original signals, asexpressed by the following derivation shown inEquation 4.
EQUATION 4:

Based on this, Voutput is then equal to that of Equation 5.

EQUATION 5:

If we call the second signal the reference and set itequal to the frequency of interest, the output will beproportional to the magnitude of the input signal andthe phase relationship between the input and thereference. It will also be modulated at twice thereference frequency.

By then passing the output signal through a low-passfilter, the 2ωt signal can be removed, leaving the finalDC signal.

By adjusting the response of the low-pass filter, anyinterfering signals with a varying phase relationshipand, consequently, any varying frequency, can beremoved from the final result. It is useful to consider thebasic operation of the analog lock-in amplifier beforemoving on to a digital solution.

Analog Lock-In AmplifiersThe block diagram of a conventional analog lock-inamplifier is shown in Figure 1. The system consists ofan input amplifier stage that amplifies the signal to asuitable level for further manipulation, perhapsperforming an impedance conversion in the process. Aband-pass filter is then used to remove any signalcomponents that are either at the DC level or atharmonics of the signal to be measured.

The next stage is the Phase Sensitive Detector, alsoknown as a synchronous demodulator or mixer. Thiscircuit can take many forms, from a logarithmicamplifier to dedicated four-quadrant multipliers. The

input signal is multiplied by a reference signal derivedfrom the system being measured. Since the referencesignal must maintain a fixed-phase relationship to theinput signal, it is often locked to the reference signalusing a Phase-Locked Loop (PLL).

A further refinement commonly found on commercialdevices is the dual channel function. In this case theinput is mixed with the reference, and is also mixedwith a 90 degree phase-shifted version of thereference. This channel function has the usefulproperty that it is then quite simple to directly calculatethe magnitude of the input and its phase relationshipto the reference. These two separate channels arenormally called the In-Phase component and theQuadrature component, or I and Q, respectively.

Finally, the output from the mixers is fed into low-passfilters, which effectively remove any non-coherentsignals, leaving a final DC signal proportional to theamplitude and phase of the input signal.

There are a number of problems with analog lock-inamplifiers. For the highest accuracy, the referencesignal must have a very low harmonic content. In otherwords, it must be a very pure sine wave since anyadditional harmonic content will cause distortion at theoutput. Analog sine wave generators can also sufferfrom amplitude variations due to temperature drift.

Temperature drift and component toleranceselsewhere in the system can cause further problems inthe analog system. Real world op amps have offsetsassociated with them that need careful trimming toprevent errors in the DC output.

Finally, any non-linearity in gain and phase will lead tofurther errors in the final output. While these problemsare not insurmountable, the result is that analog lock-inamplifiers tend to be expensive pieces of equipmentand are more often used if high-input bandwidths arerequired.

FIGURE 1: ANALOG LOCK-IN AMPLIFIER

Voutput Vin ωt⟨ ⟩cos Vref ωt θ+( )cos×=

where θ is the phase difference between the twosignals.

Voutput VinVref 2ωtcos θcos ωtcos ωtsin θsin–( )=

VinVref2

------------------ θcos 2ωtcos θcos 2ωtsin θsin–+( )=

VinVref2------------------ θcos

VinVref2------------------ 2ωt θ+( )cos+=

Phase Shifter

+90

Reference Oscillator

Input

Reference

Main Filter Low Pass Filter

Low Pass Filter

In-Phase Demodulator

Quadrature Demodulator

I

Q

Amplifier

DS01115A-page 2 © 2007 Microchip Technology Inc.

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Digital Lock-In AmplifiersIn the case of a digital lock-in amplifier, most of theprocessing is performed in the digital domain usingsoftware and dedicated Digital Signal Processing(DSP) hardware. The basic block diagram for a digitallock-in amplifier is shown in Figure 2. The system stillfeatures a front-end amplifier; however, this is thenfollowed by an anti-aliasing filter to remove any signalcomponents higher than half the sampling frequency.
For a dsPIC® DSC-based solution, the samplingwould be performed in 12-bit resolution at up to 400kHz, so the anti-aliasing filter needs to be set toattenuate any signals above 200 kHz. In practice, thefilter may have a much narrower band than this, andfor a signal of interest at 25 kHz, the filter may be setas low as 40 kHz.

The reference signal is generated internally or can bederived from sampling an external signal. In the case ofinternally generated signals, the individual samplepoints of the reference signal can be calculated to ahigh degree of accuracy, and therefore do not sufferfrom the typical errors found in the analog Lock-In. Thereference signal is also phase-shifted by 90 degrees byeither a table lookup or simple mathematicaloperations. Next, the reference and phase-shiftedreference values are multiplied directly by the DSP togenerate the intermediate I and Q signals. Finally,these signals are passed through digital low-pass filtersto generate the final output values. Interestingly, it isthe digital low-pass filter stage that can cause the mostimplementation problems for the software engineer.The data being sampled is arriving at a high rate, andeven though the output filters could be operating at onlya few Hertz, the Finite Impulse Response (FIR) filterstypically used may require many thousands of taps.The amount of RAM required for the implementationcan become prohibitively large and result in a costlyimplementation. However, as is shown later, someclever DSP techniques can be used which reducethese requirements.

Once the input signal has been quantized by theanalog-to-digital converter, there is no further loss ofsignal quality. Furthermore, since the referencesignal can be digitally computed, it can be made tohave a very low harmonic content. In the case of the16-bit dsPIC DSC processor, any harmonics will be atthe -90 dB level.

Most importantly, the deviations due to non-linear gainand phase of the analog components are removed inthe digital lock-in amplifier and there will be novariations due to temperature drift or component aging.Similarly, the offsets associated with real analogcomponents are removed and the limitation onintermediate accuracy is purely down to the resolutionof the processor and DSP engine.

FIGURE 2: DIGITAL LOCK-IN AMPLIFIER

APPLICATIONAlthough the amplifier can be used in many areas, ittypically is found where high-resolution, high-accuracymeasurements are required at relatively low data rates.So, having examined how the digital lock-in amplifierworks, let us now consider how it can be used toimprove the performance of an important application,such as weight measurement using the WheatstoneBridge.

The Wheatstone BridgeCommercial weighing scales are made from foursimilar value resistors, or strain gauges, connected toform a Wheatstone Bridge. Typically, this bridgearrangement is stimulated by applying a 10V DCsignal. Small deflections cause a voltage to appear onthe output of the circuit.

Noise SourcesOne reason to use a bridge arrangement is that errorsources, such as temperature drift, can be made tocancel each other out. However, since the nominaloutput is half the drive voltage, it can be difficult tomeasure small µV signals at the output. Any form ofinduced noise in the system can easily be picked up bythe high-impedance amplifiers that are used. A highCommon-Mode Rejection Ratio (CMRR) is requiredbecause of the high input voltage at the amplifier stage.Any junctions between dissimilar metals in the systemcan result in noise induced by the thermoelectric effect,so this condition must also be accounted for.

In fact, any electronic system will be subject tointernally generated noise and, if we consider the moregeneral situation, it is apparent that interference cancome from any number of sources. Interference fromthe local main power supply can be seen on DCmeasurements, but a lock-in amplifier can beharmonically linked to this noise source and, therefore,provide complete rejection of the interfering signal.

Digital Signal ControllerReference LUT

Phase Shifter

+90 LP FIR LP FIR

Q

IDecimate

Decimate

LP FIR LP FIR

Q Multiplier

I Multiplier

ADCAnti-alias

Filter

Amplifier

Input

Reference


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Resistors in a measurement system generate Johnsonnoise across their terminals. This generated noise isproportional to temperature and bandwidth. In general,the noise spectrum of any electronic system follows a1/f relationship. It is for this reason that a lock-inamplifier can yield such good performance.
Figure 3 shows the typical noise spectrum found inmany electronic circuits with a general broadbandcomponent covering all frequencies, 1/f noise locatedat the lower end of the spectrum and individualinterfering signals. As indicated by locating thereference signal at a higher frequency, it will be subjectto a much lower noise floor than if the measurementhad been made at DC levels.

FIGURE 3: ELECTRONIC NOISE SPECTRUM

IMPLEMENTATIONThe basic requirement for the hardware is that it shouldbe able to sample a single analog channel at highspeed. The data should be collected and analyzed inreal time, and the calculated I and Q values should beoutput via an RS-232 serial channel or displayeddirectly on an LCD. As we shall see later, themagnitude and phase relationship between the signalscan be simply calculated and it should be possible todisplay these values as well. A further enhancement,described in the next section, is for the hardware to beable to generate the reference signal that is applied tothe application circuit.

The implementation of a digital lock-in amplifier hasbeen achieved using the Explorer 16 developmentboard. This multipurpose unit can be used to test out anumber of different Microchip 16-bit processors anddigital signal controllers and, in this case, adsPIC33FJ256GP710 DSC was used. The processoris set to derive its main clock from an external crystal,such that it will operate at its maximum speed of40 MIPS, which results in an instruction cycle time of25 nS. While other values could be chosen, it wouldnormally be selected so that the majority of timings inthe rest of the system are integer multiples of theinstruction cycle time. A simplified block diagram isshown in Figure 4.

FIGURE 4: EXPLORER 16 IMPLEMENTATION

The application circuit, consisting of an R-2R ladder,low-pass filters and amplifiers, was designed andconstructed on a small PCB designed to fit into thePICtail� Plus connector of the Explorer 16 board. Thecircuit is fairly simple and could also be easilyconstructed within the prototyping area of the board ifrequired. The load cell is a commercial device capableof measuring up to 10 kg loads connected to the circuitvia leads.

The built-in digital signal processing capabilities of thedsPIC DSC allow for high-speed sampling andmanipulation of the data coming from the sensor. Themajority of the software was developed in C using theMPLAB® C30 compiler and MPLAB IDE. Writing theprogram in C enables the DSP libraries supplied withMPLAB C30 to be used to implement the signalprocessing operations required by the algorithm.

The Reference SignalThe lock-in amplifier requires a reference signal toperform the phase sensitive detection. This referencesignal could be derived from the system beingmeasured. For instance, a common application is low-light level measurement in spectroscopy. In thesesystems, minute changes in a light beam are detectedby first modulating the light using a rotating slottedwheel. This chops the light beam, which is then passedthrough the rest of the system to the detector. At thesame time, the reference signal can be derived byplacing a photo detector next to the wheel measuringthe output from an index hole.

In this application, it is necessary to generate an ACsignal to drive the bridge circuit and thus the straingauges. Therefore, it is convenient to use the DSC togenerate an output at the desired frequency. There area number of techniques that can be used includingPWM sine wave generation, overlapping the outputsfrom a number of Capture/Compare/PWM (CCP)modules, or simply using an R-2R ladder circuit. In thisapplication, the latter technique has been used.

The multi-way connector on the Explorer 16 givesaccess to the port lines and these outputs are used todrive a resistor network and buffer amplifier providingan output sine wave with 16 discrete levels. The output

0.1

1

10

100

1000

0.01 0.1 1 10 100 1000 10000 100000

Signal of Interest

Interfering Signal

1/f Noise

Broadband Noise

dsPIC33FJ256GP710

RG12

RG13

RG14

RG15

AN8

LP SallenKey Filter Buffer

LP Filter Amplifier

Load Cell

R-2R


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waveform is generated at 400 kHz with 16 outputcodes per wave, thereby generating an AC signal at25 kHz. To smooth the output and remove unwantedharmonics, the signal is fed through a low-passSallen-Key filter with a corner frequency of 40 kHz.
Basic operationThis section will go on to describe the operation of thesoftware detailing how the hardware is initialized, howthe modules interact and also how the calculationswere performed to generate the desired performance.

Since the ideal Wheatstone Bridge contains onlyresistive elements, there should not be any additionalphase errors introduced by the sensor itself. Instead, allmeasured phase changes are solely due to thegeneration and measurement system. However, sincethis technique is applicable to a number of fields,including those where it is required to measuresubstantial phase changes, the software anddiscussion will be kept generic, and both I and Q will becalculated.

The initial description relates to the first iteration of thesoftware, and the reader should note that a number ofoptimizations are possible that can improve theperformance. It is only the final, optimized version ofthe code that is provided as source code along with thisapplication note (see Appendix A: �Source Code�).

OUTPUT GENERATIONAs previously mentioned, the reference signal can beexternally derived or generated internally within themeasuring device. In this case, we use a Timer togenerate an interrupt every 2.5 µS. The source codefor the initialization can be found in the fileinit_timers.c. Since it is essential that thisroutine never be interrupted or delayed, it is assigneda high priority level. Each time, through the InterruptService Routine (ISR), a simple circular countermoves through a table of values that are output onport pins RG<12:15>. The digital outputs are fedthrough the R-2R ladder and summed and filtered toform a sine wave with an amplitude of 3.3 Volts.

SAMPLINGThe dsPIC33F family of devices features a 12-bit high-speed Analog-to-Digital Converter (ADC) module. Thismodule can be configured at run time to operate ineither 10-bit mode at up to 1 MSPS, or 12-bit mode atup to 500 kSPS. The ADC can take its conversionsignal from a number of sources including self-timing,external triggers, timers or Motor Control (MC) PWMcontrollers.

For this application, it is important that all sampling andsignal generation clocks are synchronized and that it ispossible to change the phase relationship of the signalsby changing the timings. For this reason, the ADCconversion is derived from Timer3 and is set to produce

the convert signal every 2.5 µS (a rate of 400 kHz). Theresult is that there will be 16 sample points per cycle ofthe 25 kHz waveform. It should be noted that this is atthe high end of the conventional 4-10 times samplingrates that are often selected by engineers, and as weshall see later, faster is not always most efficient.

Since the processor is simultaneously generating theoutput waveform, it would be difficult to directly sampleand manipulate the data points as they arrive. For thisreason, they are collected automatically andtransferred into system RAM using the DynamicMemory Access (DMA) controller on the dsPIC DSC.This flexible peripheral allows up to eight independentchannels to be set up and can perform automatic datamoves between configured peripherals and systemmemory or vice versa without processor intervention. Inthis case, DMA Channel 0 is set to transfer 32 samplesinto dual port memory using a ping-pong transfermode. After the transfer, and while the next 32 samplesare being collected, a VectorMultiply operation willperform the PSD multiplication generating initial I andQ data sets. Because the dsPIC DSC is generating thedrive signal, it is not necessary to reconstruct thereference signal; therefore, the two multiply operationsuse idealized copies of the reference and 90 degreephase shifted reference signals.

SAMPLE SYNCHRONIZATIONSince the data is arriving at such a high rate, it is notpossible to complete the entire signal processing taskbetween batches of the arriving samples. For thisreason, the software collates the results of 1024multiply operations in memory and only then performsthe low-pass filtering.

After having collected this many samples, the results ofany subsequent data points are ignored until thecurrent data has been processed. This introduces aproblem if the restart of sampling occurs at a differentpoint in the waveform than was previously beingsampled because it will show up as a phase changeand an error in the final output. To overcome thisproblem, the sampling is resynchronized to the start ofthe output waveform for each batch. Since some of theslower filters will use data from many batches of 1024samples, they will, to a crude approximation, ignore theintervening gap and treat the data stream as if it hadarrived in a continuous fashion. The problem thiscreates is that it can introduce significant noise into thefinal result, especially if the interfering signals have alow frequency and are synchronous with the batchedsampling rates.


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FILTERING AND DECIMATIONIf we consider that a first attempt would be to filter thedata using a low-pass FIR filter with a cut-off frequencyof 10 Hz, a filter with over 55,000 taps would berequired. This would imply that it would be necessary touse a device with access to very large amounts of RAM(up to 250 kBytes) to perform the required calculations.In addition to this, even with the highly efficient DSPengine in the dsPIC DSC, this would take over 5.6million instruction cycles to compute, assuming it couldbe performed. This would effectively prevent thesystem from operating in anything like a real-timemanner. To overcome the problem of filters with a largenumber of taps, the data is decimated (literally N-1samples in N discarded) to reduce the effective datarate in a number of stages.
The decimation is performed by first low-pass filteringthe data using a filter with a corner frequency less thanhalf the desired final sample rate, and then discardingN-1 of the N original samples. For example, if wedecimate a signal sampled at 400 kHz by a factor of 10,the final output will have a sample rate of just 40 kHz.However, to prevent aliasing, the original data must firstbe low-pass filtered using a 20 kHz filter to removeunwanted components. Finally, for every 10 data pointsin the original data stream just one output is produced.

If required, the output can then be filtered again butnow using filters designed for the lower rate. This multi-stage technique allows considerable gains in efficiencyover the brute force approach and can significantlyreduce the computational load. The dsPIC DSC libraryincludes the dedicated function, FIRDecimate, toperform these operations.

In the file isr_DMAC.c, the DMA Channel 0 ISRfunction takes 1024 sample points and decimatesthese samples down by a factor of 64, resulting in aneffective sample rate of 6.25 kHz. This result is thenFIR filtered again to yield a final pair of I and Q values.The pre-decimation filter contained 512 taps and thefinal 20 Hz low-pass filter contained 493 taps. Inaddition to the coefficient storage, each filter requiresits own delay line storage so the total RAM requirementis just over 6 kBytes which is an improvement over thesingle filter.

OUTPUT DATAEach time a new pair of results is generated, a globalflag is set and the main program loop will convert thevalues to ASCII strings and display them on theExplorer 16 LCD display. The final I and Q data valuescan also be used by a higher level algorithm, or theycan be directly converted into two values describing themagnitude and phase of the source signal using thefollowing relationships shown in Equation 6.

EQUATION 6:

The final output data can be seen in Figure 5, wherethe block mode curves indicate the output from thisiteration of the software. Notice that the curves have arapid response time. However, this response comes atthe expense of considerable overshoot and largeamounts of noise in the output.

One area where the application example differs from anormal digital lock-in amplifier is its ability to tune thephase offset to zero. If this were done, the output wouldconsist purely of a single value, proportional to theforce applied to the load cell. This capability couldeasily be incorporated by adjusting the starting valuesin the sampling and signal generation timers (TMR2and TMR3) thereby affecting the phase relationship.

Magnitude I2 Q2+=

Phase 1– QI----( )tan=


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FIGURE 5: OUTPUT CURVES FOR 1 KG LOAD PLACED ON CELL
FasterHaving discussed the main features of the software, itis worthwhile to consider how its operation can beimproved. If a timing analysis is performed, it can beseen that a significant amount of time must be spentperforming the PSD multiplications and FIR routines.As previously mentioned, the amount of time requiredfor these activities prevents the complete set ofcalculations from being performed before another setof 1024 samples arrive. Consequently, the samplinghas to be halted and restarted each time, which canlead to discontinuities and ultimately noise in the finaloutput.

A simple technique to improve the overall response ofthe system is to actually slow down the sampling rate.If we consider the operation of the PSD, it simplyperforms a sequence of multiplications. One argumentis the sample value from the ADC. The other argumentis mathematically derived from the value of the idealwave at that discrete point in the sampling sequence.For example, the Q signal is derived from multiplyingthe incoming data, one sample point at a time, by thecosine value of the ideal wave at that sample point. A25 kHz signal sampled at 400 kHz would give 16 pointsper cycle. Equation 7 shows the sequence of numbers.

EQUATION 7:

Of course, the cosine terms can be precalculated. Inthis case, the series would have the values: 0.000,0.383, 0.707, 0.924, 1.000, 0.924, 0.707, 0.383, 0.000,-0.383, -0.707, -0.924, -1.0, -0.924, -0.707, -0.383,0.000. The DSP core of the dsPIC DSC can efficientlycalculate these product terms; however, it is the highrate with which the data arrives that causes moreproblems.

A useful technique is to use fs/4 frequency translation.This is a complicated term to describe a simplemathematical trick. If instead of sampling at 400 kHzwe only sample at 4x the carrier frequency, 100 kHz inthis case, then there will only be 4 points in each of thereference signal sequences. The sequence of numbersto multiply for I is then (1, 0, -1, 0) and Q is (0, -1, 0, 1).Consequently, the frequency translation performed bythe PSD is reduced to a sequence of moves andnegations without requiring any multiplications savingan entire processing step.

It is now possible to perform the mixing as the data isbeing collected rather than waiting until a completebatch of data has been collected. Additionally, since thesample rate is now 100 kHz, the FIR filtering anddecimation can also take place in between batches ofsamples being collected without stalling the sampling.Effectively every sample point in the original signal isprocessed with none being omitted.

Continuous Mode Phase

Block Mode Phase

Continuous Mode Magnitude

Block Mode Magnitude

15

20

25

30

35

40

45

Time

Phas

e

0.35

0.37

0.39

0.41

0.43

0.45

0.47

0.49

0.51

Mag

nitu

de

Q n( ) x n( ) 2 π n16------××⎝ ⎠

⎛ ⎞cos×=


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Faster StillThe general purpose FIRDecimate routine providedby the dsPIC DSC libraries is designed to operate ongeneric data sets with relatively unrestricted data sizes.Therefore, if it is passed 60 input values and decimatedby a factor of 10, 6 output samples will be generated.This can be improved upon by applying additionalrestrictions on the incoming data. If it is assumed thatthe number of input values to the function is equal tothe decimation factor rather than calculating multipleoutputs, the new data can just be written into the delaybuffers and a single pass of the FIR filter will generateone output value.
A final enhancement involves the FIR filtersthemselves. It can be seen that alternating samples inthe I and Q data sets will have the value �0� and will notbe affected by the FIR filter tap weights at those samplepoints, and will not be accumulated into new outputvalues. By mathematically analyzing the behavior ofthe FIR filters, it is possible to deduce that if the zerovalue entries are discarded, and the remainder passedthrough a filter designed for half the original samplingfrequency, the output will be identical. In other words,by only storing the alternating non-zero elements, afilter designed for a sampling rate of 50 kHz can beused.

The reduction in effective sampling rate is importantsince it will require many fewer taps to achieve thedesired low-pass response. By reducing the number oftaps, the group delay of the filter can be reducedthereby improving the system response. Alternately,the length of the filter can be kept at a similar numberbut the shape of its response curve can be sharpened.

The output of the system for a unit step input can beseen in Figure 5, where the continuous mode curvesrepresent the data from the improved algorithm. Whileit has a slower response, the overall performance andresults are much improved over the first version of thesoftware.

CONCLUSIONThe digital lock-in amplifier is a useful tool formeasuring small signals. By translating the signalmeasurement to a high frequency, it is possible to avoidnoise introduced at DC and low frequencies.

Since it is possible to detect both amplitude and phasechanges using the lock-in amplifier, it is possible tomeasure signal changes caused by devices withcomplex impedances, such as capacitive sensors.

When implementing any DSP algorithm, it is importantto understand the fundamental processes involved;however, in addition, it is necessary to consider howthe chosen processor architecture can best be used toarrive at an optimal solution. The dsPIC33F is apowerful digital signal controller and its capabilities arewell suited to both the signal generation andprocessing tasks in this application. The high-speedADC and DMA allow for a high data throughput, whilethe efficient DSP engine can perform the multiplefiltering stages with ease.

The supplied source code (see Appendix A: �SourceCode�) can easily be modified by the reader to performmeasurements in similar applications where highaccuracy signals are required at low final output rates.

REFERENCESLyons, R., �Understanding Digital Signal Processing�,Prentice Hall, ISBN 0131089897

Microchip Technology Inc., �dsPIC30F/33FProgrammer's Reference Manual� (DS70157)

Microchip Technology Inc., �dsPIC® DSC LanguageTools Libraries� (DS51456)


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APPENDIX A: SOURCE CODEThe the libraries and source files associated with thisapplication note are available for download as a singlearchive file from the Microchip corporate Web site at:

www.microchip.com


http://www.microchip.com

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NOTES:

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© 2007 Microchip Technology Inc.

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The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

DS01115A-page 11

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company�s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip�s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

10/05/07

implementing digital lock-in amplifiers using the dspic dsc

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