ieee p802.3ba™/d0 - nag.ru802.3 project/amendment is identified with a suffix (e.g., ieee...

Draft Amendment to IEEE Std 802.3-2008 IEEE Draft P802.3ba/D0.9IEEE 802.3ba 40Gb/s and 100Gb/s Ethernet Task Force 25th Aug 2008

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IEEE P802.3ba™/D0.9, 25th Aug 2008(Amendement of IEEE Std 802.3-2008)

IEEE P802.3ba™/D0.9Draft Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements

Part 3: Carrier Sense Multiple Access withCollision Detection (CSMA/CD) Access Methodand Physical Layer SpecificationsAmendment: Media Access Control Parameters, Physical Layers and ManagementParameters for 40 Gb/s and 100 Gb/s Operation

Prepared by the

LAN/MAN Standards Committeeof theIEEE Computer Society

This draft is an amendement of IEEE Std 802.3-2008 (IEEE P802.3ay/D2.3) and defines 802.3 MediaAccess Control (MAC) parameters, physical layer specifications, and management parameters for thetransfer of 802.3 format frames at 40 Gb/s and 100 Gb/s. Draft D0.9 is prepared by the IEEE 802.3ba 40Gb/sand 100Gb/s Ethernet Task Force for Task Force Review. This draft expires 6 months after the date ofpublication or when the next version is published, whichever comes first.

Copyright © 2008 by the IEEE.3 Park AvenueNew York, NY 10016-5997, USAAll rights reserved.

This document is an unapproved draft of a proposed IEEE Standard. As such, this document is subject tochange. USE AT YOUR OWN RISK! Because this is an unapproved draft, this document must not beutilized for any conformance/compliance purposes. Permission is hereby granted for IEEE StandardsCommittee participants to reproduce this document for purposes of international standardizationconsideration. Prior to adoption of this document, in whole or in part, by another standards developmentorganization, permission must first be obtained from the IEEE Standards Activities Department. Otherentities seeking permission to reproduce this document, in whole or in part, must obtain permission from theIEEE Standards Activities Department.

IEEE Standards Activities Department445 Hoes LanePiscataway, NJ 08854, USA

Copyright © 2008 IEEE. All rights reserved.This is an unapproved IEEE Standards draft, subject to change.

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Abstract: This amendment to IEEE Std 802.3–2008 (IEEE P802.3ay) includes changes toIEEE Std 802.3–2008 and adds Clauses 150 through Clause 158 and Annex 153A. This amend-ment includes 802.3 Media Access Control (MAC) parameters, physical layer specifications, andmanagement parameters for the transfer of 802.3 format frames at 40 Gb/s and 100 Gb/s.

Keywords: 802.3ba, 40GbE, XLGMII, XLAUI, 40GBASE-R, 40GBASE-KR4, 40GBASE-CR4,40GBASE-SR4, 100GbE, CGMII, CAUI, 100GBASE-R, 100GBASE-CR10, 100GBASE-SR10,100GBASE-LR4, 100GBASE-ER4, FEC, Auto-Negotiation (AN), Backplane (BP), MMF, SMF, Op-tical Transport Network (OTN)


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Introduction

IEEE Std 802.3™ was first published in 1985. Since the initial publication, many projects have added func-tionality or provided maintenance updates to the specifications and text included in the standard. Each IEEE802.3 project/amendment is identified with a suffix (e.g., IEEE 802.3an-2006). A historical listing of allprojects that have added to or modified IEEE Std 802.3 follows as a part of this introductory material. Thelisting is in chronological order of project initiation and for each project describes: subject, clauses added (ifany), approval dates, and committee officers.

The Media Access Control (MAC) protocol specified in IEEE Std 802.3 is Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD). This MAC protocol was included in the experimental Ethernet devel-oped at Xerox Palo Alto Research Center. While the experimental Ethernet had a 2.94 Mb/s data rate, IEEEStd 802.3-1985 specified operation at 10 Mb/s. Since 1985 new media options, new speeds of operation, andnew capabilities have been added to IEEE Std 802.3.

Some of the major additions to IEEE Std 802.3 are identified in the marketplace with their project number.This is most common for projects adding higher speeds of operation or new protocols. For example, IEEEStd 802.3u added 100 Mb/s operation (also called Fast Ethernet), IEEE Std 802.3x specified full duplexoperation and a flow control protocol, IEEE Std 802.3z added 1000 Mb/s operation (also called GigabitEthernet), IEEE Std 802.3ae added 10 Gb/s operation (also called 10 Gigabit Ethernet) and IEEE Std802.3ah specified access network Ethernet (also called Ethernet in the First Mile). These major additions areall now included in, and are superceded by, IEEE Std 802.3-2008 and are not maintained as separate docu-ments.

At the date of IEEE Std 802.3ba-200X publication, IEEE Std 802.3 is comprised of the following docu-ments:

IEEE Std 802.3-2008

Section One -- Includes Clause 1 through Clause 20 and Annex A through Annex H and Annex 4A. SectionOne includes the specifications for 10 Mb/s operation and the MAC, frame formats and service interfacesused for all speeds of operation.

Section Two -- Includes Clause 21 through Clause 33 and Annex 22A through Annex 33E. Section Twoincludes management attributes for multiple protocols and speed of operation as well as specifications forproviding power over twisted pair cabling for multiple operational speeds. It also includes general informa-tion on 100 Mb/s operation as well as most of the 100 Mb/s physical layer specifications..

Editor’s Note (to be removed prior to publication):

This front matter is provided for comment only. Front matter is not part of a published standard and istherefore, not part of the draft standard. You are invited to review and comment on it as it will be includedin the published standard after approval.

One exception to IEEE style that is conciously used to simplify the balloting process is the numbering ofthe front matter. Instead of the front matter being lower case Roman numeral page numbers, with the draftrestarting at 1 with arabic page numbers, balloted front matter and draft are numbered consecuively witharabic page numbers.

This introduction is not part of IEEE Std 802.3ba-200X, IEEE Standard for Information technology—Tele-communications and information exchange between systems—Local and metropolitan area networks—Spe-cific requirements, Part 3: CSMA/CD Access Method and Physical Layer Specifications, Amendment: MediaAccess Control Parameters, Physical Layers and Management Parameters for 40 Gb/s and 100 Gb/s Opera-tion


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Section Three -- Includes Clause 34 through Clause 43 and Annex 36A through Annex 43C. Section Threeincludes general information on 1000 Mb/s operation as well as most of the 1000 Mb/s physical layer speci-fications.

.Section Four -- Includes Clause 44 through Clause 55 and Annex 44A through Annex 55B. Section Fourincludes general information on 10 Gb/s operation as well as most of the 10 Gb/s physical layer specifica-tions.

Section Five -- Includes Clause 56 through Clause 74 and Annex 57A through Annex 74A. Clause 56through Clause 67 and associated annexes specify subscriber access physical layers and sublayers for opera-tion from 512 kb/s to 1000 Mb/s, and defines services and protocol elements that enable the exchange ofIEEE Std 802.3 format frames between stations in a subscriber access network. Clause 68 specifies a 10Gb/s physical layer specification. Clause 69 through 74 and associated annexes specify Ethernet operationover electrical backplanes at speeds of 1000 Mb/s and 10 Gb/s.

IEEE Std 802.3at™–200X

This amendment includes changes to IEEE Std 802.3–2008 to augment the capabilities of the IEEE Std802.3 standard with higher power levels and improved power management information.

IEEE Std 802.3av™–200X

This amendment includes changes to IEEE Std 802.3–2008 and adds Clauses 91 through 93 and Annex91A. This amendment adds new Physical Layers for 10 Gb/s operation point-to-multipoint passive opti-cal networks.

IEEE Std 802.3az™–200X

This amendment includes changes to IEEE Std 802.3–2008 and adds Clauses xx through xx and Annexxx through xx. This amendment includes PHY enhancements for selected subset of PHY types toimprove energy efficiency and a protocol to facilitate transition to and from low power consumption inresponse to changes in network demand.

IEEE Std 802.3ba™–200X

This amendment includes changes to IEEE Std 802.3–2008 and adds Clauses 150 through 158 andAnnex 153A through Annex xx. This amendment includes 802.3 Media Access Control (MAC) param-eters, physical layer specifications, and management parameters for the transfer of 802.3 format framesat 40 Gb/s and 100 Gb/s.

IEEE 802.3 will continue to evolve. New Ethernet capabilities are anticipated to be added within the nextfew years as amendments to this standard.

Notice to users

Errata

Errata, if any, for this and all other standards can be accessed at the following URL: http://standards.ieee.org/reading/ieee/updates/errata/index.html.Users are encouraged to check this URL for errata periodically.


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Downloads

Portions of this standard can be downloaded from the Internet. Materials include PICS tables, data tables,and code. URLs are listed in the text in the appropriate sections.

Interpretations

Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee.interp/index.html

Patents

Attention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEEE shall not be responsible for identifying pat-ents or patent applications for which a license may be required to implement an IEEE standard or for con-ducting inquiries into the legal validity or scope of those patents that are brought to its attention. A patentholder or patent applicant has filed a statement of assurance that it will grant licenses under these rightswithout compensation or under reasonable rates and nondiscriminatory, reasonable terms and conditions toapplicants desiring to obtain such licenses. The IEEE makes no representation as to the reasonableness ofrates, terms, and conditions of the license agreements offered by patent holders or patent applicants. Furtherinformation may be obtained from the IEEE Standards Department.


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ParticipantsThe following individuals were members of the IEEE 802.3 working group at the beginning of the P802.3baworking group ballot. Individuals may have not voted, voted for approval, disapproval, or abstained on thisamendment.

David J. Law, Working Group ChairWael William Diab, Working Group Vice Chair

Adam Healy, Working Group SecretarySteven B. Carlson, Working Group Executive Secretary

Bradley Booth, Working Group Treasurer

John D’Ambrosia, Chair, IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet Task ForceIlango S. Ganga, Chief Editor, IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet Task Force

IEEE P802.3ba Editorial teamPete AnslowHugh BarrassPiers Dawe

Chris DiminicoMark GustlinJonathan King

Ryan LatchmanArthur Marris

Stephen J (Steve) Trowbridge

INSERT NAME, LIST OTHER TF OFFICERS, EDITORS, TF_NAME Task Force


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xxx

CoThis is an un

pyright © 2008 IEEE. All rights reserved.approved IEEE Standards draft, subject to
change.
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The following members of the individual balloting committee voted on this standard. Balloters may havevoted for approval, disapproval, or abstention.

xxx

CoThis is an un

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change.


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When the IEEE–SA Standards Board approved this standard on 15 September 200X, it had the followingmembership:

xxx, Chairxxx, Vice Chairxxx, Past Chairxxx, Secretary

*Member Emeritus

Also included are the following nonvoting IEEE–SA Standards Board liaisons:

NRC RepresentativeDOE RepresentativeNIST Representative

Michelle TurnerIEEE Standards Program Manager, Document Development

Michael D. KipnessIEEE Standards Program Manager, Technical Program Development

xxx

xxx

CoThis is an un

change.
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List of special symbolsFor the benefit of those who have received this document by electronic means, what follows is a list of specialsymbols and operators. If any of these symbols or operators fail to print out correctly on your machine, the editorsapologize, and hope that this table will at least help you to sort out the meaning of the resulting funny-shapedblobs and strokes.

Special symbols and operators

Printed character Meaning Keystrokes Character code Font

∗ Boolean AND * ALT-042 Symbol

+ Boolean OR, arithmetic addition + ALT-043 Symbol

^ Boolean XOR ^ ALT-094 Times New Roman! Boolean NOT ! ALT-033 Symbol× Multiplication Ctrl-q 4 ALT-0180 Symbol

< Less than < ALT-060 Symbol

≤ Less than or equal to Ctrl-q # ALT-0163 Symbol

> Greater than > ALT-062 Symbol

≥ Greater than or equal to Ctrl-q 3 ALT-0179 Symbol

= Equal to = ALT-061 Symbol

≠ Not equal to Ctrl-q 9 ALT-0185 Symbol

⇐ Assignment operator Ctrl-q \ ALT-0220 Symbol

∈ Indicates membership Ctrl-q Shift-n ALT-0206 Symbol

∉ Indicates nonmembership Ctrl-q Shift-o ALT-0207 Symbol

± Plus or minus (a tolerance) Ctrl-q 1 ALT-0177 Symbol° Degrees Ctrl-q 0 ALT-0176 Symbol

∑ Summation Esc ^ Shift-a ALT-0229 Symbol

√ Square root Ctrl-q Shift-v ALT-0214 Symbol— Big dash (em dash) Ctrl-q Shift-q ALT-0151 Times New Roman– Little dash (en dash), subtraction Ctrl-q Shift-p ALT-0150 Times New Roman| Vertical bar | ALT-0124 Times New Roman† Dagger Ctrl-q Space ALT-0134 Times New Roman‡ Double dagger Ctrl-q ‘ ALT-0135 Times New Romanα Lower case alpha a ALT-097 Symbol

β Lower case beta b ALT-098 Symbolγ Lower case gamma g ALT-103 Symbolδ Lower case delta d ALT-100 Symbolε Lower case epsilon e ALT-101 Symbolλ Lambda l ALT-0108 Symbolµ Micro Ctrl-q 5 ALT-0181 Times New RomanΩ Omega W ALT-087 Symbol


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1. Introduction........................................................................................................................................ 20

1.3 Normative references ................................................................................................................. 201.4 Definitions ................................................................................................................................. 211.5 Abbreviations............................................................................................................................. 22

4. Media Access Control........................................................................................................................ 23

4.4.2 MAC parameters............................................................................................................ 23

30. Management....................................................................................................................................... 25

30.2.5 Capabilities .................................................................................................................... 25

45. Management Data Input/Output (MDIO) Interface........................................................................... 27

45.2.1 PMA/PMD registers ...................................................................................................... 2745.2.3 PCS registers.................................................................................................................. 4845.2.7 Auto-Negotiation registers............................................................................................. 64

45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, MDIO inter-face 67

69. Introduction to Ethernet operation over electrical backplanes .......................................................... 69

69.1 Overview.................................................................................................................................... 6969.1.1 Scope.............................................................................................................................. 6969.1.2 Objectives ...................................................................................................................... 6969.1.3 Relationship of Backplane Ethernet to the ISO OSI reference model........................... 69

69.2 Summary of Backplane Ethernet Sublayers .............................................................................. 7069.2.1 Reconciliation sublayer and media independent interfaces ........................................... 7069.2.2 Physical Layer signaling systems .................................................................................. 7069.2.5 Management................................................................................................................... 71

69.3 Delay constraints........................................................................................................................ 71

73. Auto-Negotiation for Backplane Ethernet ........................................................................................ 73

73.3 Functional specifications ........................................................................................................... 7373.5.1 DME page encoding ...................................................................................................... 7373.6.4 Technology Ability Field............................................................................................... 7373.6.5 FEC capability ............................................................................................................... 74

73.7 Receive function requirements .................................................................................................. 7473.7.1 DME page reception ...................................................................................................... 7473.7.2 Receive Switch function ................................................................................................ 7473.7.6 Priority Resolution function........................................................................................... 7573.10.1State diagram variables .................................................................................................. 7573.10.2State diagram timers ...................................................................................................... 76

73.11Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negoti-ation for Backplane Ethernet78

74. Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs .................................................. 79

74.1 Overview.................................................................................................................................... 7974.4.1 Functional Block Diagram (single lane PHYs) ............................................................. 7974.4.2 Functional Block Diagram (single lane PHYs) ............................................................. 79


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74.8 FEC MDIO function mapping ................................................................................................... 8174.11Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error

Correction (FEC) sublayer for 10GBASE-R PHYs84

150. Introduction to 40 Gb/s and 100 Gb/s baseband network.................................................................. 85

150.1Overview................................................................................................................................... 85150.1.1Scope.............................................................................................................................. 85150.1.2Objectives ...................................................................................................................... 85150.1.3Relationship of 40 and 100 Gigabit Ethernet to the ISO OSI reference model............. 85

150.2Summary of 40 and 100 Gigabit Ethernet sublayers ................................................................ 87150.2.1Reconciliation Sublayer (RS) and Media Independent Interface (MII) ........................ 87150.2.2Management interface (MDIO/MDC) ........................................................................... 87150.2.3Physical Layer signaling systems .................................................................................. 87150.2.4Auto-Negotiation ........................................................................................................... 88150.2.5Management................................................................................................................... 89150.2.6Service Interface specification method and notation ..................................................... 89

150.3Delay constraints....................................................................................................................... 89150.4State diagrams........................................................................................................................... 90150.5Protocol implementation conformance statement (PICS) proforma......................................... 90150.11Protocol implementation conformance statement (PICS) proforma for Clause 150, 40 Gb/s and

100 Gb/s baseband network systems91

151. Reconciliation Sublayer (RS) and Media Independent Interface (MII) for 40 Gb/s and 100 Gb/s oper-ation 93

151.1Overview................................................................................................................................... 93151.1.1Summary of major concepts .......................................................................................... 94151.1.2Application..................................................................................................................... 94151.1.3Rate of operation............................................................................................................ 94151.1.4Delay constraints............................................................................................................ 94151.1.5Allocation of functions .................................................................................................. 95151.1.6MII structure .................................................................................................................. 95151.1.7Mapping of MII signals to PLS service primitives........................................................ 96

151.2MII data stream......................................................................................................................... 98151.2.1Inter-frame <inter-frame>.............................................................................................. 99151.2.2Preamble <preamble> and start of frame delimiter <sfd>............................................. 99151.2.3Data <data>.................................................................................................................. 100151.2.4End of frame delimiter <efd> ...................................................................................... 100151.2.5Definition of Start of Packet and End of Packet Delimiters ........................................ 100

151.3MII functional specifications .................................................................................................. 100151.3.1Transmit ....................................................................................................................... 100151.3.2Receive......................................................................................................................... 105151.3.3Error and fault handling ............................................................................................... 108151.3.4Link fault signaling...................................................................................................... 109151.3.5PCS MDIO function mapping ..................................................................................... 111

151.4Protocol implementation conformance statement (PICS) proforma for Clause 151, Reconcilia-tion Sublayer (RS) and Media Independent Interface (MII)112

151.4.1Introduction.................................................................................................................. 112

152. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R .................. 113

152.1Overview................................................................................................................................. 113152.1.1Scope............................................................................................................................ 113


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152.1.2Relationship of 40GBASE-R and 100GBASE-R to other standards .......................... 113152.1.3Summary of 10GBASE-R sublayer ............................................................................. 114152.1.4Inter-sublayer interfaces .............................................................................................. 115152.1.5Physical Medium Attachment (PMA) service interface .............................................. 115152.1.6Functional block diagram ............................................................................................ 115

152.2Physical Coding Sublayer (PCS) ............................................................................................ 116152.2.1PCS service interface (MII) ......................................................................................... 116152.2.2Functions within the PCS ............................................................................................ 117152.2.3Use of blocks ............................................................................................................... 117152.2.464B/66B transmission code ......................................................................................... 118152.2.5Transmit process .......................................................................................................... 124152.2.6Scrambler ..................................................................................................................... 124152.2.7Block distribution ........................................................................................................ 124152.2.8Alignment marker insertion ......................................................................................... 125152.2.9PMA Interface.............................................................................................................. 126152.2.10Test-pattern generators .............................................................................................. 127152.2.11Block synchronization ............................................................................................... 128152.2.12Lane deskew .............................................................................................................. 128152.2.13Alignment marker removal ........................................................................................ 128152.2.14Descrambler ............................................................................................................... 129152.2.15Receive process.......................................................................................................... 129152.2.16Test-pattern checker................................................................................................... 129152.2.17Detailed functions and state diagrams ....................................................................... 129152.2.18PCS Management ...................................................................................................... 134152.2.19Delay constraints........................................................................................................ 135152.2.20Auto-Negotiation ....................................................................................................... 135152.2.21PCS MDIO function mapping ................................................................................... 135

152.3Protocol implementation conformance statement (PICS) proforma for Clause 152, Physical Coding Sublayer (PCS) type 40GBASE-R and 100GBASE-R142

152.3.1Introduction.................................................................................................................. 142

153. Physical Medium Attachment (PMA) sub-layer, 40/100GBASE-R ............................................... 143

153.1Overview................................................................................................................................. 143153.1.1Scope............................................................................................................................ 143153.1.2Position of the PMA in the 40GBASE-R or 100GBASE-R sub-layers ...................... 143153.1.3Summary of functions.................................................................................................. 144153.1.4PMA context ................................................................................................................ 145

153.2PMA interfaces ....................................................................................................................... 147153.3PMA primitives....................................................................................................................... 148

153.3.1PMA_UNITDATA.inputx........................................................................................... 149153.3.2PMA_UNITDATA.outputy ......................................................................................... 150153.3.3PMA_SIGNAL.input ................................................................................................... 150153.3.4PMA_SIGNAL.output ................................................................................................. 151

153.4PMA service interface ............................................................................................................ 151153.5PMD service interface ............................................................................................................ 152153.6Functions within the PMA...................................................................................................... 152

153.6.1Per input-lane clock and data recovery........................................................................ 152153.6.2Bit level multiplexing/gearboxing ............................................................................... 152153.6.3Clocking architecture ................................................................................................... 153153.6.4Signal drivers ............................................................................................................... 154153.6.5Link status.................................................................................................................... 154153.6.6PMA loopback mode (optional) .................................................................................. 154153.6.7PMA test patterns......................................................................................................... 155


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153.7PMA MDIO function mapping............................................................................................... 156153.8Protocol implementation conformance statement (PICS) proforma for Clause 153, Physical Me-

dium Attachment (PMA) sub-layer, 40/100GBASE-R158153.8.1Introduction.................................................................................................................. 158153.8.2Identification ................................................................................................................ 158

154. Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-KR4................ 159

154.1Overview................................................................................................................................. 159154.2Physical Medium Dependent (PMD) service interface .......................................................... 160

154.2.1PMD_UNITDATA.request.......................................................................................... 161154.2.2Semantics of the service primitive............................................................................... 161154.2.3PMD_SIGNAL.indication ........................................................................................... 161

154.3PCS requirements for Auto-Negotiation (AN) service interface............................................ 162154.4Delay constraints..................................................................................................................... 162154.5Skew constraints ..................................................................................................................... 162154.6PMD MDIO function mapping............................................................................................... 162154.7PMD functional specifications................................................................................................ 162

154.7.1Link block diagram...................................................................................................... 162154.7.2PMD transmit function ................................................................................................ 164154.7.3PMD receive function .................................................................................................. 164154.7.4Global PMD signal detect function ............................................................................. 164154.7.5PMD transmit disable function .................................................................................... 165154.7.6Loopback mode............................................................................................................ 165154.7.7PMD_fault function ..................................................................................................... 165154.7.8PMD transmit fault function ........................................................................................ 165154.7.9PMD receive fault function.......................................................................................... 165154.7.10PMD control function ................................................................................................ 166

154.810GBASE-KR electrical characteristics ................................................................................. 166154.8.1Transmitter characteristics ........................................................................................... 166154.8.2Receiver characteristics ............................................................................................... 166

154.9Interconnect characteristics..................................................................................................... 167154.10Environmental specifications................................................................................................ 167

154.10.1General safety ............................................................................................................ 167154.10.2Network safety ........................................................................................................... 167154.10.3Installation and maintenance guidelines .................................................................... 167154.10.4Electromagnetic compatibility ................................................................................... 167154.10.5Temperature and humidity......................................................................................... 167

154.11Protocol implementation conformance statement (PICS) proforma for Clause 154, Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-KR4168

154.11.1Introduction................................................................................................................ 168154.11.2Identification .............................................................................................................. 168

155. Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-CR4 and 100GBASE-CR10171

155.1Overview................................................................................................................................. 171155.2Physical Medium Dependent (PMD) service interface .......................................................... 172

155.2.1PMD_UNITDATA.request.......................................................................................... 173155.2.2PMD_UNITDATA.indication ..................................................................................... 173155.2.3PMD_SIGNAL.indication ........................................................................................... 174

155.3PCS requirements for Auto-Negotiation (AN) service interface............................................ 174155.4Delay constraints..................................................................................................................... 174155.5Skew constraints ..................................................................................................................... 174


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155.6PMD MDIO function mapping............................................................................................... 174155.6.1Link block diagram...................................................................................................... 177155.6.2PMD Transmit function ............................................................................................... 177155.6.3PMD Receive function................................................................................................. 178155.6.4Global PMD signal detect function ............................................................................. 178155.6.5PMD lane-by-lane signal detect function .................................................................... 179155.6.6Global PMD transmit disable function ........................................................................ 179155.6.7PMD lane-by-lane transmit disable function ............................................................... 179155.6.8Loopback mode............................................................................................................ 179155.6.9PMD_fault function ..................................................................................................... 179155.6.10PMD transmit fault function ...................................................................................... 180155.6.11PMD receive fault function........................................................................................ 180155.6.12PMD control function ................................................................................................ 180

155.7MDI Electrical specifications for 40GBASE-CR4 and 100GBASE-CR10 ........................... 180155.7.1Signal levels ................................................................................................................. 180155.7.2Signal paths.................................................................................................................. 180155.7.3Transmitter characteristics ........................................................................................... 180155.7.4Receiver characteristics ............................................................................................... 182

155.8Cable assembly characteristics ............................................................................................... 183155.8.1Characteristic impedance and reference impedance .................................................... 185155.8.2Cable assembly insertion loss ...................................................................................... 185155.8.3Cable assembly return loss .......................................................................................... 186155.8.4Near-End Crosstalk (NEXT) ....................................................................................... 186155.8.5Far-End Crosstalk (FEXT)........................................................................................... 188155.8.6Shielding ...................................................................................................................... 190155.8.7Crossover function ....................................................................................................... 190

155.9Transmitter and receiver diferential printed circuit board trace loss ...................................... 191155.10MDI specification ................................................................................................................. 191

155.10.140GBASE-CR4 MDI connectors............................................................................... 191155.10.2100GBASE-CR10 MDI connectors........................................................................... 194

155.11Environmental specifications................................................................................................ 195155.12Protocol implementation conformance statement (PICS) proforma for Clause 155, Physical

Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10196

155.12.1Introduction................................................................................................................ 196

156. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10 197

156.1Overview................................................................................................................................. 197156.1.1Physical Medium Dependent (PMD) service interface ............................................... 197

156.2Delay and skew....................................................................................................................... 200156.2.1Delay constraints.......................................................................................................... 200156.2.2Skew constraints .......................................................................................................... 200

156.3PMD MDIO function mapping............................................................................................... 201156.4PMD functional specifications................................................................................................ 202

156.4.1PMD block diagram..................................................................................................... 202156.4.2PMD transmit function ................................................................................................ 202156.4.3PMD receive function .................................................................................................. 203156.4.4PMD global signal detect function .............................................................................. 203156.4.5PMD lane by lane signal detect function ..................................................................... 203156.4.6PMD reset function...................................................................................................... 204156.4.7PMD global transmit disable function ......................................................................... 204156.4.8PMD lane by lane transmit disable function................................................................ 204


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156.4.9PMD fault function ...................................................................................................... 204156.4.10PMD transmit fault function (optional) ..................................................................... 204156.4.11PMD receive fault function (optional)....................................................................... 204

156.5Lane assignments .................................................................................................................... 204156.6PMD to MDI optical specifications for 40GBASE–SR4 and 100GBASE-SR10 .................. 205

156.6.140GBASE–SR4 and 100GBASE-SR10 transmitter electrical specifications ............. 205156.6.2Transmitter optical specifications ................................................................................ 206156.6.3Characteristics of signal within, and at the receiving end of, a compliant optical channel

(informative)207156.6.440GBASE–SR4 or 100GBASE–SR10 receiver optical specifications ....................... 207156.6.5Receiver electrical specifications................................................................................. 207156.6.640GBASE–SR4 and 100GBASE–SR10 link power budget (informative) ................. 210

156.7Definitions of electrical and optical parameters and measurement methods.......................... 210156.7.1Test points and compliance boards .............................................................................. 210156.7.2Test patterns and related subclauses ............................................................................ 210156.7.3Electrical parameters.................................................................................................... 211156.7.4Optical parameter definitions....................................................................................... 213

156.8Safety, installation, environment, and labeling....................................................................... 214156.8.1General safety .............................................................................................................. 214156.8.2Installation ................................................................................................................... 215156.8.3Environment................................................................................................................. 215156.8.4PMD labeling ............................................................................................................... 215

156.9Recommended electrical channel (informative) ..................................................................... 215156.10Optical channel ..................................................................................................................... 216

156.10.1Fiber optic cabling model .......................................................................................... 216156.10.2Characteristics of the fiber optic cabling (channel) ................................................... 217

156.11Protocol implementation conformance statement (PICS) proforma for Clause 156, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10219


157. Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-LR? ....... 221

157.1Overview................................................................................................................................. 221157.2Protocol implementation conformance statement (PICS) proforma for Clause 157, Physical Me-

dium Dependent (PMD) sublayer and baseband medium, type 40GBASE-LRx222157.2.1Introduction.................................................................................................................. 222157.2.2Identification ................................................................................................................ 222

158. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4 225

158.1Overview................................................................................................................................. 225158.1.1Physical Medium Dependent (PMD) service interface ............................................... 225

158.2Delay and skew....................................................................................................................... 227158.2.1Delay constraints.......................................................................................................... 227158.2.2Skew constraints .......................................................................................................... 228

158.3PMD MDIO function mapping............................................................................................... 228158.4PMD functional specifications................................................................................................ 228

158.4.1PMD block diagram..................................................................................................... 228158.4.2PMD transmit function ................................................................................................ 229158.4.3PMD receive function .................................................................................................. 229158.4.4PMD global signal detect function .............................................................................. 230158.4.5PMD lane by lane signal detect function ..................................................................... 231


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158.4.6PMD reset function...................................................................................................... 231158.4.7PMD global transmit disable function ......................................................................... 231158.4.8PMD lane by lane transmit disable function................................................................ 231158.4.9PMD fault function ...................................................................................................... 231158.4.10PMD transmit fault function (optional) ..................................................................... 231158.4.11PMD receive fault function (optional)....................................................................... 232

158.5Wavelength-division-multiplexed lane assignments .............................................................. 232158.6PMD to MDI optical specifications for 100GBASE–LR4 ..................................................... 232

158.6.1100GBASE–LR4 transmitter optical specifications .................................................... 232158.6.2100GBASE–LR4 receive optical specifications.......................................................... 234158.6.3100GBASE–LR4 link power budget (informative)..................................................... 234

158.7PMD to MDI optical specifications for 100GBASE–ER4 ..................................................... 235158.7.1100GBASE–ER4 transmitter optical specifications .................................................... 235158.7.2100GBASE–ER4 receive optical specifications.......................................................... 236158.7.3100GBASE–ER4 link power budget (informative)..................................................... 237

158.8Definition of optical parameters and measurement methods.................................................. 238158.8.1Test patterns for optical parameters............................................................................. 238158.8.2Wavelength .................................................................................................................. 238158.8.3Average optical power ................................................................................................. 238158.8.4Optical Modulation Amplitude (OMA)....................................................................... 238158.8.5Transmitter and dispersion penalty (TDP)................................................................... 239158.8.6Extinction ratio ............................................................................................................ 241158.8.7Relative Intensity Noise (RIN12OMA)....................................................................... 241158.8.8Transmitter optical waveform (transmit eye) .............................................................. 241158.8.9Transmit jitter for each lane of 100GBASE–LR4 and 100GBASE–ER4 ................... 241158.8.10Receiver sensitivity.................................................................................................... 241158.8.11Stressed receiver sensitivity....................................................................................... 241158.8.12Receiver 3 dB electrical upper cutoff frequency ....................................................... 242

158.9Safety, installation, environment, and labeling....................................................................... 242158.9.1General safety .............................................................................................................. 242158.9.2Laser safety .................................................................................................................. 242158.9.3Installation ................................................................................................................... 242

158.10Environment.......................................................................................................................... 243158.10.1Electromagnetic emission .......................................................................................... 243158.10.2Temperature, humidity, and handling........................................................................ 243

158.11PMD labeling requirements .................................................................................................. 243158.12Fiber optic cabling model ..................................................................................................... 243158.13Characteristics of the fiber optic cabling (channel) .............................................................. 244

158.13.1Optical fiber and cable ............................................................................................... 244158.13.2Optical fiber connection............................................................................................. 245158.13.3Medium Dependent Interface (MDI) requirements ................................................... 245

158.14Protocol implementation conformance statement (PICS) proforma for Clause 158, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4246


Annex A ...................................................................................................................................................... 249

Bibliography ................................................................................................................................................ 249

Annex 4A .................................................................................................................................................... 251

Simplified full duplex media access control................................................................................................ 251


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Annex 30A .................................................................................................................................................. 253

GDMO specification for IEEE 802.3 managed object classes .................................................................... 253

Annex 30B .................................................................................................................................................. 254

GDMO and ASN.1 definitions for management ......................................................................................... 254

30B.2ASN.1 module for CSMA/CD managed objects ............................................................. 254Annex 69A .................................................................................................................................................. 255

Interference tolerance testing....................................................................................................................... 255

Annex 69B .................................................................................................................................................. 257

Interconnect characteristics.......................................................................................................................... 257

Annex 153A ................................................................................................................................................ 263

40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) .............................................................................................................. 263

153A.1Overview........................................................................................................................ 263153A.3.XLAUI/CAUI electrical characteristics........................................................................ 265153A.4Electrical measurement requirements ............................................................................ 274153A.5.Environmental specifications........................................................................................ 276153A.6.Protocol implementation conformance statement (PICS) proforma for Annex 153A, 40

Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI)277


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Draft Amendment of:

Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—

Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer SpecificationsAmendment: Media Access Control Parameters, Physical Layers and ManagementParameters for 40 Gb/s and 100 Gb/s Operation

[This amendment is part of IEEE Std 802.3™-2008]

NOTE– This amendment is described with reference to IEEE 802.3-2008. The editing instructions define how to mergethe material contained here into the base document set to form the new comprehensive standard as created by the addi-tion of IEEE Std 802.3ba-200X. When the source of the base text is other than IEEE Std 802.3-2008, the source is indi-cated in the change instruction.

Editing instructions are shown in bold italic. Four editing instructions are used: change, delete, insert, and replace.Change is used to make small corrections in existing text or tables. The editing instruction specifies the location of thechange and describes what is being changed either by using strikethrough (to remove old material) or underscore (to addnew material). Delete removes existing material. Insert adds new material without disturbing the existing material.Insertions may require renumbering. If so, renumbering instructions are given in the editing instruction. Replace is usedto make large changes in existing text, subclauses, tables, or figures by removing existing material and replacing it withnew material. Editorial notes will not be carried over into future editions because the changes will be incorporated intothe base standard


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1. Introduction

1.1.3.2 Compatibility interfaces

Insert the following new compatibility interfaces to the end of the list:

i) 40 Gigabit Media Independent Interface (XLGMII). The XLGMII is designed to connect a 40 Gb/scapable MAC to a 40 Gb/s PHY. While conformance with implementation of this interface is notnecessary to ensure communication, it allows maximum flexibility in intermixing PHYs and DTEsat 40 Gb/s speeds. The XLGMII is a logical interconnection intended for use as an intra-chip inter-face. No mechanical connector is specified for use with the XLGMII. The XLGMII is optional.

j) 40 Gigabit Attachment Unit Interface (XLAUI). The XLAUI is a PMA service interface designed toextend the connection between a 40 Gb/s capable MAC/PCS and a 40 Gb/s PMA/PMD. While con-formance with implementation of this interface is not necessary to ensure communication, it is rec-ommended, since it allows maximum flexibility in intermixing PHYs and DTEs at 40 Gb/s speeds.The XLAUI is intended for use as a chip-to-chip interface. No mechanical connector is specified foruse with the XLAUI. The XLAUI is optional.

k) 100 Gigabit Media Independent Interface (CGMII). The CGMII is designed to connect a 100 Gb/scapable MAC to a 100 Gb/s PHY. While conformance with implementation of this interface is notnecessary to ensure communication, it allows maximum flexibility in intermixing PHYs and DTEsat 100 Gb/s speeds. The CGMII is is a logical interconnection intended for use as an intra-chip inter-face. No mechanical connector is specified for use with the CGMII. The CGMII is optional.

l) 100 Gigabit Attachment Unit Interface (CAUI). The CAUI is a PMA service interface designed toextend the connection between a 100 Gb/s capable MAC/PCS and a 100 Gb/s PMA/PMD. Whileconformance with implementation of this interface is not necessary to ensure communication, it isrecommended, since it allows maximum flexibility in intermixing PHYs and DTEs at 100 Gb/sspeeds. The CAUI is intended for use as a chip-to-chip interface. No mechanical connector is speci-fied for use with the CAUI. The CAUI is optional.

1.3 Normative references

[Editor’s note (to be removed prior to publication) - Insert new references to this subclause]

Insert the following references in alphabetical order:

ITU-T Recommendation G.694.1, 2002—Spectral grids for WDM applications: DWDM frequency grid

ITU-T Recommendation G.695, 2006—Optical interfaces for coarse wavelength division multiplexing applications

Change the following reference in 1.3 and rearrange in alphabetical order:

ANSI/EIA/TIA-455-127-A-19912006, FOTP-127-A—Basic Spectral Characterization of Multimode LaserDiodes.


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1.4 Definitions

Insert the following new definitions into the definitions list, in alphanumeric order:

1.4.x 40 Gigabit Attachment Unit Interface (XLAUI): A 4 lane inter sublayer electrical interface used forchip-to-chip interconnections for 40 Gb/s operation. (See IEEE 802.3, Annex 153A.)

1.4.x 40 Gigabit Media Independent Interface (XLGMII): The interface between the Reconciliation Sub-layer (RS) and the Physical Coding Sublayer (PCS) for 40 Gb/s operation. (See IEEE 802.3, Clause 151.)

1.4.x 40GBASE-R: An IEEE 802.3 family of physical layer devices using physical coding sublayer for 40Gb/s operation over multiple lanes using 64B/66B block encoding. (See IEEE 802.3, Clause 152.)

1.4.x 40GBASE-CR4: IEEE 802.3 Physical Layer specification for 40 Gb/s using 40GBASE-R encodingover four lanes of shielded balanced copper cabling. (See IEEE 802.3, Clause 155.)

1.4.x 40GBASE-KR4: IEEE 802.3 Physical Layer specification for 40 Gb/s using 40GBASE-R encodingover four lanes of an electrical backplane. (See IEEE 802.3, Clause 154.)

1.4.x 40GBASE-SR4: IEEE 802.3 Physical Layer specification for 40 Gb/s using 40GBASE-R encodingover four lanes of, short reach, multi mode fiber. (See IEEE 802.3, Clause 156.)

1.4.x 100 Gigabit Attachment Unit Interface (CAUI): A 10 lane inter sublayer electrical interface usedfor chip-to-chip interconnections for 100 Gb/s operation. (See IEEE 802.3, Annex 153A.)

1.4.x 100 Gigabit Media Independent Interface (CGMII): The interface between the Reconciliation Sub-layer (RS) and the Physical Coding Sublayer (PCS) for 100 Gb/s operation. (See IEEE 802.3, Clause 151.)

1.4.x 100GBASE-R: An IEEE 802.3 family of physical layer devices using physical coding sublayer for100 Gb/s operation over multiple lanes using 64B/66B block encoding. (See IEEE 802.3, Clause 152)

1.4.x 100GBASE-CR10: IEEE 802.3 Physical Layer specification for 100 Gb/s using 100GBASE-R encod-ing over ten lanes of shielded balanced copper cabling. (See IEEE 802.3, Clause 155.)

1.4.x 100GBASE-ER4: IEEE 802.3 Physical Layer specification for 100 Gb/s using 100GBASE-R encod-ing over four LAN WDM lanes, extended long reach, single mode fiber. (See IEEE 802.3, Clause 158.)

1.4.x 100GBASE-LR4: IEEE 802.3 Physical Layer specification for 100 Gb/s using 100GBASE-R encod-ing over four LAN WDM lanes, long reach, single mode fiber. (See IEEE 802.3, Clause 158.)

1.4.x 100GBASE-SR10: IEEE 802.3 Physical Layer specification for 100 Gb/s using 100GBASE-R encod-ing over ten lanes of, short reach, multi mode fiber. (See IEEE 802.3, Clause 156.)

1.4.x Virtual Lane: In 40GBASE-R and 100GBASE-R, the PCS distributes encoded data to multiple logi-cal lanes, these logical lanes are called virtual lanes. They are called virtual lanes since one or more of PCSlanes can be multiplexed and carried on a physical lane together at the PMA interface.

Change 1.4.311 as follows:

1.4.311 RMS spectral width: A measure of the optical wavelength range as defined by ANSI/EIA/TIA 455-127-A-1991 (FOTP-127-A) [B8].


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1.5 Abbreviations

Insert the following new abbreviations into the definitions list, in alphanumeric order:

CAUI 100Gb/s attachment unit interfaceCGMII 100 Gigabit Media Independent InterfaceDIC Deficit idle counterLSB Least significant bitMSB Most significant bitOTN Optical Transport NetworkOPU3 Optical Payload Unit 3PPI Parallel Physical InterfaceXLAUI 40 Gigabit Attachment Unit InterfaceXLGMII 40 Gigabit Media Independent Interface


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4. Media Access Control

4.4.2 MAC parameters

Insert a new column to Table 4-2 for 40 Gb/s and 100Gb/s MAC data rates:

Table 4–2—MAC parameters

Insert the following note below Table 4-2 for 40 Gb/s and 100Gb/s MAC data rates, and renumber notesas appropriate:

NOTE 7—For 40 and 100 Gb/s operation, the spacing between two packets, from the last bit of the FCS field of the firstpacket to the first bit of the Preamble of the second packet, can have a minimum value of 8 BT (bit times), as measuredat the XLGMII or CGMII receive signals at the DTE. This interPacketGap shrinkage may be caused by variable networkdelays and clock tolerances.

.

Parameters

MAC data rate

Up to andincluding100 Mb/s

1 Gb/s 10 Gb/s 40 Gb/s and 100Gb/s

slotTime 512 bit times 4096 bit times not applicable not applicable

interPacketGapa

aReferences to interFrameGap or interFrameSpacing in other clauses (e.g., 13, 35, and 42) shall be interpreted as inter-PacketGap

96 bits 96 bits 96 bits 96 bits

attemptLimit 16 16 not applicable not applicable

backoffLimit 10 10 not applicable not applicable

jamSize 32 bits 32 bits not applicable not applicable

maxBasicFrameSize 1518 octets 1518 octets 1518 octets 1518 octets

maxEnvelopeFrameSize 2000 octets 2000 octets 2000 octets 2000 octets

minFrameSize 512 bits (64 octets) 512 bits (64 octets) 512 bits (64 octets) 512 bits (64 octets)

burstLimit not applicable 65 536 bits not applicable not applicable

ipgStretchRatio not applicable not applicable 104 bits not applicable

WARNING

Any deviation from the above specified values may affect proper operation of the network.


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30. Management

[Editor’s note (to be removed prior to publication) - Insert new capabilities, update table 30-1 or add newtables, change or insert objects for new PHY types for 40 Gb/s and 100 Gb/s operation]

[Editor’s note (to be removed prior to publication) - This clause will be will be filled in during Task Forcereview]

30.2.5 Capabilities

30.3.2.1.2 aPhyType

30.3.2.1.3 aPhyTypeList


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45. Management Data Input/Output (MDIO) Interface

[Editor’s note (to be removed prior to publication) - Insert new registers, or add bits to existing registers,or add new tables, for new PMA/PMD, PCS, and Auto-Neg for 40 Gb/s and 100 Gb/s operation]

45.2.1 PMA/PMD registers

Change Table 45-3 for 40 Gb/s and 100 Gb/s registers:

[Editor’s note (to be removed prior to publication) - The registers originally specified for 10GBASE-KRhave been renamed as “Backplane” registers although they are used for both BASE-KR and BASE-CRPHYs. Other suggestions for naming these registers will be considered after review by the Task Force.]

Table 45–3—PMA/PMD registers

Register address Register name

1.0 PMA/PMD control 1

1.1 PMA/PMD status 1

1.2, 1.3 PMA/PMD device identifier

1.4 PMA/PMD speed ability

1.5, 1.6 PMA/PMD devices in package

1.7 PMA/PMD control 2

1.8 10G PMA/PMD status 2

1.9 10G PMA/PMD transmit disable

1.10 10G PMD receive signal detect

1.11 10G PMA/PMD extended ability register

1.12 Reserved (802.3av)

1.13 40G/100G PMA/PMD extended ability register

1.12, 1.13 Reserved

1.14, 1.15 PMA/PMD package identifier

... ...

1.150 10GBASE-KR Backplanea PMD control

1.151 10GBASE-KR Backplane PMD status

1.152 10GBASE-KR Backplane LP coefficient update, lane 0

1.153 10GBASE-KR Backplane LP status report, lane 0

1.154 10GBASE-KR Backplane LD coefficient update, lane 0

1.155 10GBASE-KR Backplane LD status report, lane 0

1.156 Backplane PMD status 2

1.157 Backplane PMD status 3

1.1568 through 1.159 Reserved

1.160 1000BASE-KX control

1.161 1000BASE-KX status


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1.170 10GBASE-KR Backplane FEC ability

1.171 110GBASE-KR Backplane control

1.172 through 1.173 10GBASE-KR Backplane FEC corrected blocks counter, lane 0

1.174 through 1.175 10GBASE-KR Backplane FEC uncorrected blocks counter, lane 0

1.176 through 1.177 Backplane FEC corrected blocks counter, lane 1

1.178 through 1.179 Backplane FEC uncorrected blocks counter, lane 1

























1.228through 1.229 Backplane FEC corrected blocks counter, lane 14





Table 45–3—PMA/PMD registers (continued)



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1.270 Backplane LP coefficient update, lane 1

1.271 Backplane LP status report, lane 1

1.272 Backplane LD coefficient update, lane 1

1.273 Backplane LD status report, lane 1





























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Change Table 45-4 for 40 Gb/s and 100 Gb/s speed selection:

.

[Editor’s note (to be removed prior to publication) - 45.2.1.1.4 will need to be edited if PMA loopback ismandatory]

Change Table 45-6 for 40 Gb/s and 100 Gb/s speed ability:

Insert 45.2.1.4.7 and 45.2.1.4.8 as follows:









1.310 through 1.319 Reserved for 802.3av

1.176320 through 1.32 767 ReservedaThe name “Backplane” is used to denote PHYs that use the PMD described in Clause 72, in-

cluding PHYS designated as BASE-KR and BASE-CR

Table 45–4—PMA/PMD control 1 register bit definitions

Bit(s) Name Description R/Wa

aR/W = Read/Write, SC = Self-clearing

1.0.5:2 Speed selection 5 4 3 21 x x x = Reservedx 1 x x = Reservedx x 1 x = Reserved0 0 1 1 = 100 Gb/s0 0 1 0 = 40 Gb/s0 0 0 1 = 10PASS-TS/2BASE-TL0 0 0 0 = 10 Gb/s

R/W




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45.2.1.4.8 40G capable (1.4.8)

When read as a one, bit 1.4.8 indicates that the PMA/PMD is able to operate at a data rate of 40 Gb/s. Whenread as a zero, bit 1.4.8 indicates that the PMA/PMD is not able to operate at a data rate of 40 Gb/s.

45.2.1.4.9 100G capable (1.4.9)

When read as a one, bit 1.4.9 indicates that the PMA/PMD is able to operate at a data rate of 100 Gb/s.When read as a zero, bit 1.4.9 indicates that the PMA/PMD is not able to operate at a data rate of 100 Gb/s.

Change Table 45-7 for 40 Gb/s and 100 Gb/s PMA/PMD type selections:

Change 45.2.1.6.1 for 40 Gb/s and 100 Gb/s PMA/PMD type selections:

45.2.1.6.1 PMA/PMD type selection (1.7.34:0)

The PMA/PMD type of the PMA/PMD shall be selected using bits 34 through 0. The PMA/PMD type abili-ties of the PMA/PMD are advertised in bits 9 and 7 through 0 of the PMA/PMD status 2 register; and bits 8through 0 of the PMA/PMD extended ability register; and the 40G/100G PMA/PMD extended ability regis-ter 2. A PMA/PMD shall ignore writes to the PMA/PMD type selection bits that select PMA/PMD types ithas not advertised in the PMA/PMD status 2 register. It is the responsibility of the STA entity to ensure thatmutually acceptable MMD types are applied consistently across all the MMDs on a particular PHY.

The PMA/PMD type selection defaults to a supported ability.

[Editor’s note (to be removed prior to publication) - 45.2.1.7.4 & 45.2.1.7.5 will need to be edited if trans-mit and/or receive fault are supported by 40/100G PMA/PMD]

Change 45.2.1.8 for 40 Gb/s and 100 Gb/s PMA/PMD transmit disable:

45.2.1.8 10G PMD transmit disable register (Register 1.9)

The assignment of bits in the 10G PMD transmit disable register is shown in Table 45–9. The transmit dis-able functionality is optional and a PMD’s ability to perform the transmit disable functionality is advertisedin the PMD transmit disable ability bit 1.8.8. A PMD that does not implement the transmit disable function-ality shall ignore writes to the 10G PMD transmit disable register and may return a value of zero for all bits.

Table 45–6—PMA/PMD speed ability register bit definitions


1.4.15:71.4.15:10

Reserved for future speeds Value always 0, writes ignored RO

1.4.9 100G capable 1 = PMA/PMD is capable of operating at 100 Gb/s0 = PMA/PMD is not capable of operating as 100 Gb/s

RO

1.4.8 40G capable 1 = PMA/PMD is capable of operating at 40 Gb/s0 = PMA/PMD is not capable of operating as 40 Gb/s

RO

1.4.7 Reserved Reserved for 802.3av ROaRO = Read only


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A PMD device that operates using a single wavelength or lane and has implemented the transmit disablefunction shall use bit 1.9.0 to control the function. Such devices shall ignore writes to bits 1.9.410:1 andreturn a value of zero for those bits when they are read. The transmit disable function for the 10GBASE-KRPMD is described in 72.6.5, for 10GBASE-LRM serial PMDs in 68.4.7, and for other serial PMDs in 52.4.7.The transmit disable function for wide wavelength division multiplexing (WWDM) PMDs the 10GBASE-LX4 PMD is described in 53.4.7. The transmit disable function for the 10GBASE-CX4 PMD is described in54.5.6. The transmit disable function for 10GBASE-KX4 is described in 71.6.6. The transmit disable func-tion for the 10GBASE-T PMA is described in 55.4.2.3. The transmit disable function for 40GBASE-KR4 isdescribed in 154.7.5. The transmit disable function for 40GBASE-CR4 and 100GBASE-CR10 is describedin 155.6.6. The transmit disable function for 40GBASE-SR4 and 100GBASE-SR10 is described in 156.4.7.The transmit disable function for 40GBASE-LR? is described in 157.TBD. The transmit disable function for100GBASE-LR4 and 100GBASE-ER4 is described in 158.4.7.

Change Table 45-9 for 10 lane transmit disables:

Insert before 45.2.1.8.1 for 10 lane transmit disable:

Table 45–7—PMA/PMD control 2 register bit definitions


1.7.15:41.7.15:6

Reserved Value always 0, writes ignored R/W

1.7.3:01.7.5:0

PMA/PMD type selection 5 4 3 2 1 01 1 x x x x = reserved for future usee1 0 1 1 x x = reserved for future 100G PMA/PMD type1 0 1 0 1 1 = 100GBASE-ER4 PMA/PMD type1 0 1 0 1 0 = 100GBASE-LR4 PMA/PMD type1 0 1 0 0 1 = 100GBASE-SR10 PMA/PMD type1 0 1 0 0 0 = 100GBASE-CR10 PMA/PMD type1 0 0 1 x x = reserved for future 40G PMA/PMD type1 0 0 0 1 1 = 40GBASE-LR? PMA/PMD type1 0 0 0 1 0 = 40GBASE-SR4 PMA/PMD type1 0 0 0 0 1 = 40GBASE-CR4 PMA/PMD type1 0 0 0 0 0 = 40GBASE-KR4 PMA/PMD type0 1 x x x x = Reserved for 802.3av0 0 1 1 1 1 = 10BASE-T PMA/PMD type0 0 1 1 1 0 = 100BASE-TX PMA/PMD type0 0 1 1 0 1 = 1000BASE-KX PMA/PMD type0 0 1 1 0 0 = 1000BASE-T PMA/PMD type0 0 1 0 1 1 = 10GBASE-KR PMA/PMD type0 0 1 0 1 0 = 10GBASE-KX4 PMA/PMD type0 0 1 0 0 1 = 10GBASE-T PMA type0 0 1 0 0 0 = 10GBASE-LRM PMA/PMD type0 0 0 1 1 1 = 10GBASE-SR PMA/PMD type0 0 0 1 1 0 = 10GBASE-LR PMA/PMD type0 0 0 1 0 1 = 10GBASE-ER PMA/PMD type0 0 0 1 0 0 = 10GBASE-LX4 PMA/PMD type0 0 0 0 1 1 = 10GBASE-SW PMA/PMD type0 0 0 0 1 0 = 10GBASE-LW PMA/PMD type0 0 0 0 0 1 = 10GBASE-EW PMA/PMD type0 0 0 0 0 0 = 10GBASE-CX4 PMA/PMD type

R/W

aR/W = Read/Write


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45.2.1.8.1a PMD transmit disable 9 (1.9.10)

When bit 1.9.10 is set to a one, the PMD shall disable output on lane 9 of the transmit path. When bit 1.9.10is set to a zero, the PMD shall enable output on lane 9 of the transmit path.

The default value for bit 1.9.10 is zero.

NOTE—Transmission will not be enabled when this bit is set to a zero unless the global PMD transmit disable bit is alsozero.


When bit 1.9.9 is set to a one, the PMD shall disable output on lane 8 of the transmit path. When bit 1.9.9 isset to a zero, the PMD shall enable output on lane 8 of the transmit path.







Table 45–9—10G PMD transmit disable register bit definitions


1.9.15:511 Reserved Value always 0, writes ignored R/W

1.9.10 PMD transmit disable 9 1 = Disable output on transmit lane 90 = Enable output on transmit lane 9

R/W


R/W


R/W


R/W


R/W


R/W

aR/W = Read/Write


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Change 45.2.1.9 for 40 Gb/s and 100 Gb/s PMA/PMD signal detect:

45.2.1.9 10G PMD receive signal detect register (Register 1.10)

The assignment of bits in the 10G PMD receive signal detect register is shown in Table 45–10. The 10GPMD receive signal detect register is mandatory. PMD types that use only a single wavelength or lane indi-cate the status of the receive signal detect using bit 1.10.0 and return a value of zero for bits 1.10.4:1. PMDtypes that use multiple wavelengths or lanes indicate the status of each lane in bits 1.10.410:1 and the logicalAND of those bits in bit 1.10.0.

Change Table 45-10 for 10 lane signal detect:

Insert before 45.2.1.9.1 for 10 lane signal detect:

45.2.1.9.1a PMD receive signal detect 9 (1.10.10)

When bit 1.10.10 is read as a one, a signal has been detected on lane 9 of the PMD receive path. When bit1.10.10 is read as a zero, a signal has not been detected on lane 9 of the PMD receive path.




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Change Table 45-11 for 40G/100G extended abilities:

Table 45–10—10G PMD receive signal detect register bit definitions


1.10.15:511 Reserved Value always 0, writes ignored RO

1.10.10 PMD receive signal detect 9 1 = Signal detected on receive lane 90 = Signal not detected on receive lane 9

RO


RO


RO


RO


RO


RO

aRO = Read only


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.

Insert before 45.2.1.12 for 40G/100G extended abilities:

45.2.1.12a 40G/100G PMA/PMD extended ability register (Register 1.12)

The assignment of bits in the 40G/100G PMA/PMD extended ability register is shown in Table 45–12a. Allof the bits in the PMA/PMD extended ability register are read only; a write to the PMA/PMD extended abil-ity register shall have no effect.

Table 45–11—PMA/PMD Extended Ability register bit definitions


aRO = Read only

1.11.15 40G/100G Extended abilities 1 = PMA/PMD has 40G/100G extended abilities listed in register 1.120 = PMA/PMD does not have 40G/100G extended abili-ties

RO

1.11.154:9 Reserved Ignore on read RO

Table 45–12a—40G/100G PMA/PMD extended ability register bit definitions


aRO = Read only


1.12.11 100GBASE-ER4 ability 1 = PMA/PMD is able to perform 100GBASE-ER40 = PMA/PMD is not able to perform 100GBASE-ER4

RO

1.12.10 100GBASE-LR4 ability 1 = PMA/PMD is able to perform 100GBASE-LR40 = PMA/PMD is not able to perform 100GBASE-LR4

RO

1.12.9 100GBASE-SR10 ability 1 = PMA/PMD is able to perform 100GBASE-SR100 = PMA/PMD is not able to perform 100GBASE-SR10

RO

1.12.8 100GBASE-CR10 ability 1 = PMA/PMD is able to perform 100GBASE-CR100 = PMA/PMD is not able to perform 100GBASE-CR10

RO


1.12.3 40GBASE-LR? ability 1 = PMA/PMD is able to perform 40GBASE-LR?0 = PMA/PMD is not able to perform 40GBASE-LR?

RO

1.12.2 40GBASE-SR4 ability 1 = PMA/PMD is able to perform 40GBASE-SR40 = PMA/PMD is not able to perform 40GBASE-SR4

RO

1.12.1 40GBASE-CR4 ability 1 = PMA/PMD is able to perform 40GBASE-CR40 = PMA/PMD is not able to perform 40GBASE-CR4

RO

1.12.0 40GBASE-KR4 ability 1 = PMA/PMD is able to perform 40GBASE-KR40 = PMA/PMD is not able to perform 40GBASE-KR4

RO


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45.2.1.12a.1 100GBASE-ER4 ability (1.12.11)

When read as a one, bit 1.12.11 indicates that the PMA/PMD is able to operate as a 100GBASE-ER4 PMA/PMD type. When read as a zero, bit 1.12.11 indicates that the PMA/PMD is not able to operate as a100GBASE-ER4 PMA/PMD type.

45.2.1.12a.2 100GBASE-LR4 ability (1.12.10)

When read as a one, bit 1.12.10 indicates that the PMA/PMD is able to operate as a 100GBASE-LR4 PMA/PMD type. When read as a zero, bit 1.12.10 indicates that the PMA/PMD is not able to operate as a100GBASE-LR4 PMA/PMD type.

45.2.1.12a.3 100GBASE-SR10 ability (1.12.9)

When read as a one, bit 1.12.9 indicates that the PMA/PMD is able to operate as a 100GBASE-SR10 PMA/PMD type. When read as a zero, bit 1.12.9 indicates that the PMA/PMD is not able to operate as a100GBASE-SR10 PMA/PMD type.

45.2.1.12a.4 100GBASE-CR10 ability (1.12.8)

When read as a one, bit 1.12.8 indicates that the PMA/PMD is able to operate as a 100GBASE-CR10 PMA/PMD type. When read as a zero, bit 1.12.8 indicates that the PMA/PMD is not able to operate as a100GBASE-CR10 PMA/PMD type.

45.2.1.12a.5 40GBASE-LR? ability (1.12.3)

When read as a one, bit 1.12.3 indicates that the PMA/PMD is able to operate as a 100GBASE-LR? PMA/PMD type. When read as a zero, bit 1.12.3 indicates that the PMA/PMD is not able to operate as a100GBASE-LR? PMA/PMD type.

45.2.1.12a.6 40GBASE-SR4 ability (1.12.2)

When read as a one, bit 1.12.2 indicates that the PMA/PMD is able to operate as a 100GBASE-SR4 PMA/PMD type. When read as a zero, bit 1.12.2 indicates that the PMA/PMD is not able to operate as a100GBASE-SR4 PMA/PMD type.

45.2.1.12a.7 40GBASE-CR4 ability (1.12.1)

When read as a one, bit 1.12.1 indicates that the PMA/PMD is able to operate as a 100GBASE-CR4 PMA/PMD type. When read as a zero, bit 1.12.1 indicates that the PMA/PMD is not able to operate as a100GBASE-CR4 PMA/PMD type.

45.2.1.12a.8 40GBASE-KR4 ability (1.12.0)

When read as a one, bit 1.12.0 indicates that the PMA/PMD is able to operate as a 100GBASE-KR4 PMA/PMD type. When read as a zero, bit 1.12.0 indicates that the PMA/PMD is not able to operate as a100GBASE-KR4 PMA/PMD type.

Change 45.2.1.76 for register naming:


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45.2.1.76 10GBASE-KR Backplane PMD control register (Register 1.150)

The backplane PMD control register is used for 10GBASE-KR and other PHY types using the backplanePMD described in Clause 72 The assignment of bits in the backplane PMD control register is shown inTable 45–53.


Table 45–53—10GBASE-KR Backplane PMD control register


aR/W = Read/Write, SC = Self-clearing, RO = Read only

1.150.15:2 Reserved Value always zero, writes ignored RO

1.150.1 Training enable 1 = Enable the 10GBASE-KR backplane start-up protocol0 = Disable the 10GBASE-KR backplane start-up protocol R/W

1.150.0 Restart training 1 = Reset 10GBASE-KR backplane start-up protocol0 = Normal operation

R/WSC


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45.2.1.77 10GBASE-KR Backplane PMD status register (Register 1.151)

The backplane PMD status register is used for 10GBASE-KR and other PHY types using the backplanePMD described in Clause 72. The assignment of bits in the 10GBASE-KR backplane PMD status register isshown in Table 45–54..

Table 45–54—10GBASE-KR Backplane PMD status register


aRO = Read only


1.151.15 Training failure 3 1 = Training failure has been detected for lane 30 = Training failure has not been detected for lane 3 RO

1.151.14 Start-up protocol status 3 1 = Start-up protocol in progressfor lane 30 = Start-up protocol completefor lane 3 RO

1.151.13 Frame lock 3 1 = Training frame delineation detected for lane 30 = Training frame delineation not detected for lane 3 RO

1.151.12 Receiver status 3 1 = Receiver trained and ready to receive data for lane 30 = Receiver training for lane 3 RO


1.151.10 Start-up protocol status 2 1 = Start-up protocol in progress for lane 20 = Start-up protocol complete for lane 2 RO












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45.2.1.77.1 Receiver status 0 (1.151.0)

This bit maps to the state variable rx_trained as defined in 72.6.10.3.1.

45.2.1.77.2 Frame lock 0 (1.151.1)

This bit maps to the state variable frame_lock as defined in 72.6.10.3.1.

45.2.1.77.3 Start-up protocol status 0 (1.151.2)

This bit maps to the state variable training as defined in 72.6.10.3.1.

45.2.1.77.4 Training failure 0 (1.151.3)

This bit maps to the state variable training_failure as defined in 72.6.10.3.1.

45.2.1.77.5 Receiver status 1, 2, 3 (1.151.4, 1.151.8, 1.151.12)

These bits are defined identically to 1.151.0 for lanes 1, 2 and 3 respectively.

45.2.1.77.6 Frame lock 1, 2, 3 (1.151.5, 1.151.9, 1.151.13)


45.2.1.77.7 Start-up protocol status 1, 2, 3 (1.151.6, 1.151.10, 1.151.14)


45.2.1.77.8 Training failure 1, 2, 3 (1.151.7, 1.151.11, 1.151.15)


Change 45.2.1.78 through 81 for register naming and for multi-lane:

45.2.1.78 10GBASE-KR Backplane LP coefficient update register, lane 0 (Register 1.152)

The backplane LP coefficient update register, lane 0 is used for 10GBASE-KR and other PHY types usingthe backplane PMD described in Clause 72. The 10GBASE-KR backplane LP coefficient update register,lane 0 reflects the contents of the first 16-bit word of the training frame most recently received from the con-trol channel for lane 0 or for a single lane PHY.

The assignment of bits in the 10GBASE-KR backplane LP coefficient update register, lane 0 is shown inTable 45–55. Normally the bits in this register are read only; however, when training is disabled by settinglow bit 1 in the 10GBASE-KR backplane PMD control register, the 10GBASE-KR backplane LP coeffi-cient update register, lane 0 becomes writeable.

45.2.1.79 10GBASE-KR Backplane LP status report register, lane 0 (Register 1.153)

The backplane LP status report register, lane 0 is used for 10GBASE-KR and other PHY types using thebackplane PMD described in Clause 72. The 10GBASE-KR backplane LP status report register, lane 0reflects the contents of the second 16-bit word of the training frame most recently received from the controlchannel for lane 0 or for a single lane PHY.


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The assignment of bits in the 10GBASE-KR backplane LP status report register, lane 0 is shown in Table45-56.

45.2.1.80 10GBASE-KR Backplane LD coefficient update register, lane 0 (Register 1.154)

The backplane LD coefficient update register, lane 0 is used for 10GBASE-KR and other PHY types usingthe backplane PMD described in Clause 72. The 10GBASE-KR backplane LD coefficient update register,lane 0 reflects the contents of the first 16-bit word of the outgoing training frame as defined by the LDreceiver adaptation process in 72.6.10.2.5 for lane 0 or for a single lane PHY.

The assignment of bits in the 10GBASE-KR backplane LD coefficient update register, lane 0 is shown inTable 45-5645-57.

45.2.1.81 10GBASE-KR Backplane LD status report register, lane 0 (Register 1.155)

The backplane LD status report register, lane 0 is used for 10GBASE-KR and other PHY types using thebackplane PMD described in Clause 72. The 10GBASE-KR backplane LD status report register, lane 0reflects the contents of the second 16-bit word of the current outgoing training frame, as defined in the train-ing state diagram in Figure 72–5 for lane 0 or for a single lane PHY.

The assignment of bits in the 10GBASE-KR backplane LD status report register, lane 0 is shown in Table45-58.

Insert 45.2.1.81a and 45.2.1.81b for status register 2 & 3:


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45.2.1.81a Backplane PMD status register 2 (Register 1.156)

The backplane PMD status register 2 is used for 100GBASE-CR10 and other PHY types using the back-plane PMD described in Clause 72 over more than 4 lanes. The assignment of bits in the backplane PMDstatus register 2 is shown in Table 45–58a.

Table 45–58a—Backplane PMD status register 2


aRO = Read only


1.156.14 Start-up protocol status 7 1 = Start-up protocol in progressfor lane 70 = Start-up protocol completefor lane 7 RO
















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45.2.1.81a.1 Receiver status 4, 5, 6, 7 (1.156.0, 1.156.4, 1.156.8, 1.156.12)

These bits are defined identically to 1.151.0 for lanes 4, 5, 6 and 7 respectively.

45.2.1.81a.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13)


45.2.1.81a.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14)


45.2.1.81a.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15)


45.2.1.81b Backplane PMD status register 3 (Register 1.157)

The backplane PMD status register 3 is used for 100GBASE-CR10 and other PHY types using the back-plane PMD described in Clause 72 over more than 8 lanes. The assignment of bits in the backplane PMDstatus register 3 is shown in Table 45–58b..

45.2.1.81b.1 Receiver status 8, 9 (1.157.0, 1.157.4)

These bits are defined identically to 1.151.0 for lanes 8 and 9 respectively.

Table 45–58b—Backplane PMD status register 3


aRO = Read only











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45.2.1.81b.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13)


45.2.1.81b.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14)


45.2.1.81b.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15)



45.2.1.84 10GBASE-KR Backplane FEC ability register (Register 1.170)

The backplane FEC ability register is used for 10GBASE-KR and other PHY types using the backplanePMD described in Clause 72 with the FEC function described in Clause 74. The assignment of bits inthe 10GBASE-KR backplane FEC ability register is shown in Table 45–61.

45.2.1.84.1 10GBASE-R Backplane FEC ability (1.170.0)

When read as a one, this bit indicates that the 10GBASE-KR PHY sublayer supports forward error correc-tion (FEC). When read as a zero, the 10GBASE-KR PHY sublayer does not support forward error correc-tion.

45.2.1.84.2 10GBASE-R Backplane error indication ability (1.170.1)

When read as a one, this bit indicates that the 10GBASE-KR FEC sublayer is able to indicate decodingerrors to the PCS layer (see 74.8.3). When read as a zero, the 10GBASE-KR FEC sublayer is not able toindicate decoding errors to the PCS layer. 10GBASE-KR Backplane FEC error indication is controlled bythe FEC enable error indication bit in the FEC control register (see 45.2.1.85.2).


45.2.1.85 10GBASE-KR Backplane FEC control register (Register 1.171)

The backplane FEC control register is used for 10GBASE-KR and other PHY types using the back-

Table 45–61—10GBASE-KR Backplane FEC ability register bit definitions


aRO Read only


1.170.1 10GBASE-R Backplane FEC error indication ability

A read of 1 in this bit indicates that the 10GBASE-R PHY FEC sublayer is able to report FEC decod-ing errors to the PCS layer

RO

1.170.0 10GBASE-R Backplane FEC ability

A read of 1 in this bit indicates that the 10GBASE-R PHY sublayer supports FEC RO


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plane PMD described in Clause 72 with the FEC function described in Clause 74. The assignment ofbits in the 10GBASE-KR Backplane FEC control register is shown in Table 45–62.

45.2.1.85.1 FEC enable (1.171.0)

When written as a one, this bit enables FEC for the 10GBASE-KR Backplane PHY. When written as a zero,FEC is disabled in the 10GBASE-KR Backplane PHY. This bit shall be set to zero upon execution of PHYreset.

45.2.1.85.2 FEC enable error indication (1.171.1)

This bit enables the 10GBASE-KR Backplane FEC decoder to indicate decoding errors to the upper layers(PCS) through the sync bits for the 10GBASE-KR Backplane PHY in the Local Device. When written as aone, this bit enables indication of decoding errors through the sync bits to the PCS layer. When written aszero the error indication function is disabled. Writes to this bit are ignored and reads return a zero if the10GBASE-KR Backplane FEC does not have the ability to indicate decoding errors to the PCS layer (see45.2.1.84.2 and 74.8.3).

Change 45.2.1.86 and 87 for register naming and for multi-lane:

45.2.1.86 10GBASE-KR Backplane FEC corrected blocks counter, lane 0 (Register 1.172, 1.173)

The backplane FEC corrected blocks counter, lane 0 is used for 10GBASE-KR and other PHY types usingthe backplane PMD described in Clause 72 with the FEC function described in Clause 74. The assignmentof bits in the 10GBASE-KR Backplane FEC corrected blocks counter register, lane 0 is shown in Table45–63. See 74.8.4.1 for a definition of this register. These bits shall be reset to all zeroes when the register isread by the management function or upon PHY reset. These bits shall be held at all ones in the case of over-flow. Registers 1.172, 1.173 are used to read the value of a 32-bit counter. When registers 1.172 and 1.173are used to read the 32-bit counter value, the register 1.172 is read first, the value of the register 1.173 islatched when (and only when) register 1.172 is read and reads of register 1.173 returns the latched value

Table 45–62—10GBASE-KR Backplane FEC control register bit definitions


aR/W = Read/Write, RO Read only


1.171.1 FEC enable error indication A write of 1 to this bit configures the FEC decoder to indicate errors to the PCS layer R/W

1.171.0 FEC enable A write of 1 to this bit enables 10GBASE-R FEC A write of 0 to this bit disables 10GBASE-R FEC R/W


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rather than the current value of the counter. For a multi-lane PHY this register returns the corrected errorcount for lane 0..

45.2.1.87 10GBASE-KR Backplane FEC uncorrected blocks counter, lane 0 (Register1.174, 1.175)

The backplane FEC uncorrected blocks counter, lane 0 is used for 10GBASE-KR and other PHY typesusing the backplane PMD described in Clause 72 with the FEC function described in Clause 74. The assign-ment of bits in the 10GBASE-KR Backplane FEC uncorrected blocks counter register, lane 0 is shown inTable 45–64. See 74.8.4.2 for a definition of this register. These bits shall be reset to all zeroes when the reg-ister is read by the management function or upon PHY reset. These bits shall be held at all ones in the case ofoverflow. Registers 1.174, 1.175 are used to read the value of a 32-bit counter. When registers 1.174 and1.175 are used to read the 32-bit counter value, the register 1.174 is read first, the value of the register 1.175is latched when (and only when) register 1.174 is read and reads of register 1.175 returns the latched valuerather than the current value of the counter. For a multi-lane PHY this register returns the uncorrected errorcount for lane 0.

Insert 45.2.1.87a and 87b for multi-lane FEC:

45.2.1.87a Backplane FEC corrected blocks counter, lanes 1 through 19

(Register 1.176, 1.177, 1.180, 1.181, 1.184, 1.185, 1.188, 1.189, 1.192, 1.193, 1.196, 1.197, 1.200, 1.201,1.204, 1.205, 1.208, 1.209, 1.212, 1.213, 1.216, 1.217, 1.220, 1.221, 1.224, 1.225, 1.228, 1.229, 1.232,1.233, 1.236, 1.237, 1.240, 1.241, 1.244, 1.245, 1.248, 1.249)

The even-numbered registers in this set are defined similarly to register 1.172 (see 45.2.1.86) but for lanes 1through 19 respectively of multi-lane PHYs. The odd-numbered registers in this set are defined similarly to

Table 45–63—10GBASE-KR Backplane FEC corrected blocks counter, lane 0 register bit definitions


aRO = Read only, NR = Non Roll-over

1.172.15:0 FEC corrected blocks lower FEC_corrected_blocks_counter[15:0] RO, NR

1.173.15:0 FEC corrected blocks upper FEC_corrected_blocks_counter[31:16] RO, NR

Table 45–64—10GBASE-KR Backplane FEC uncorrected blocks counter register bit defini-tions


aRO = Read only, NR = Non Roll-over

1.174.15:0 FEC uncorrected blocks lower FEC_uncorrected_blocks_counter[15:0] RO, NR

1.175.15:0 FEC uncorrected blocks upper FEC_uncorrected_blocks_counter[31:16] RO, NR


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register 1.173 (see 45.2.1.86) but for lanes 1 through 19 respectively of multi-lane PHYs. Registers corre-sponding to lanes that are not used for the selected PHY shall return all zeros.

45.2.1.87b Backplane FEC uncorrected blocks counter, lanes 1 through 19

(Register 1.178, 1.179, 1.182, 1.183, 1.186, 1.187, 1.190, 1.191, 1.194, 1.195, 1.198, 1.199, 1.202, 1.203,1.206, 1.207, 1.210, 1.211, 1.214, 1.215, 1.218, 1.219, 1.222, 1.223, 1.226, 1.227, 1.230, 1.231, 1.234,1.235, 1.238, 1.239, 1.242, 1.243, 1.246, 1.247, 1.250, 1.251)

The even-numbered registers in this set are defined similarly to register 1.174 (see 45.2.1.87) but for lanes 1through 19 respectively of multi-lane PHYs. The odd-numbered registers in this set are defined similarly toregister 1.175 (see 45.2.1.87) but for lanes lanes 1 through 19 respectively of multi-lane PHYs. Registerscorresponding to lanes that are not used for the selected PHY shall return all zeros.

Insert 45.2.1.87c, d, e and f for multi-lane coefficient exchange:

45.2.1.87c Backplane LP coefficient update register, lanes 1 through 9

(Register 1.230, 1.234, 1.238, 1.242, 1.246, 1.250, 1.254, 1.258, 1.262)

These registers are defined similarly to register 1.152 (see 45.2.1.78) but for lanes 1 through 9 respectivelyof multi-lane PHYs. Registers corresponding to lanes that are not used for the selected PHY shall return allzeros.

45.2.1.87d Backplane LP status report register, lanes 1 through 9

(Register 1.231, 1.235, 1.239, 1.243, 1.247, 1.251, 1.255, 1.259, 1.263)


45.2.1.87e Backplane LD coefficient update register, lanes 1 through 9

(Register 1.232, 1.236, 1.240, 1.244, 1.248, 1.252, 1.256, 1.260, 1.264)


45.2.1.87f Backplane LD status report register, lanes 1 through 9

(Register 1.233, 1.237, 1.241, 1.245, 1.249, 1.253, 1.257, 1.261, 1.265)



47


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45.2.3 PCS registers

Change Table 45-82 for 40 Gb/s and 100 Gb/s PCS registers:

Change Table 45-83 for 40 Gb/s and 100 Gb/s speed selection:

.

Table 45–82—PCS registers


3.7 10G PCS control 2

3.8 10G PCS status 2

3.32 10G/40G/100GBASE-R and 10GBASE-T PCS status 1

3.33 10G/40G/100GBASE-R and 10GBASE-T PCS status 2

3.34 through 3.37 10G/40G/100GBASE-R PCS test pattern seed A

3.38 through 3.41 10GBASE-R PCS test pattern seed B

3.42 10G/40G/100GBASE-R PCS test pattern control

3.43 10G/40G/100GBASE-R PCS test pattern error counter


3.50 Multi-lane BASE-R PCS alignment status 1





Table 45–83—PCS control 1 register bit definitions


aR/W = Read/Write, SC = Self-clearing

3.0.5:2 Speed selection 5 4 3 21 x x x = Reservedx 1 1 x = Reservedx 1 0 1 = Reservedx x 1 x = Reserved0 1 0 0 = 100 Gb/s0 0 1 1 = 40 Gb/s0 0 1 0 = Reserved for 802.3av0 0 0 1 = 10PASS-TS/2BASE-TL0 0 0 0 = 10 Gb/s

R/W


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Change Table 45-85 for 40 Gb/s and 100 Gb/s speed ability:

Insert 45.2.3.4.3 and 45.2.3.4.4 as follows:

45.2.3.4.3 40G capable (3.4.7)

When read as a one, bit 3.4.7 indicates that the PCS is able to operate at a data rate of 40 Gb/s. When read asa zero, bit 3.4.7 indicates that the PCS is not able to operate at a data rate of 40 Gb/s.

45.2.3.4.4 100G capable (3.4.8)

When read as a one, bit 1.4.8 indicates that the PCS is able to operate at a data rate of 100 Gb/s. When readas a zero, bit 1.4.8 indicates that the PCS is not able to operate at a data rate of 100 Gb/s.

Change 45.2.3.6 for 40 Gb/s and 100 Gb/s PCS type select:

45.2.3.6 10G PCS control 2 register (Register 3.7)

The assignment of bits in the 10G PCS control 2 register is shown in Table 45–86. The default value for eachbit of the 10G PCS control 2 register should be chosen so that the initial state of the device upon power up orreset is a normal operational state without management intervention.

45.2.3.6.1 PCS type selection (3.7.1:0)

The PCS type shall be selected using bits 12 through 0. The PCS type abilities of the 10G PCS are advertisedin bits 3.8.32:0. A 10G PCS shall ignore writes to the PCS type selection bits that select PCS types it has notadvertised in the 10G PCS status 2 register. It is the responsibility of the STA entity to ensure that mutuallyacceptable MMD types are applied consistently across all the MMDs on a particular PHY. The PCS typeselection defaults to a supported ability.

Change 45.2.3.7 for 40 Gb/s and 100 Gb/s PCS type capability:

Table 45–85—PCS speed ability register bit definitions


aRO = Read only

3.4.15:13.4.15:9

Reserved for future speeds Value always 0, writes ignored RO

3.4.8 100G capable 1 = PCS is capable of operating at 100 Gb/s0 = PCS is not capable of operating at 100 Gb/s

RO

3.4.7 40G capable 1 = PCS is capable of operating at 40 Gb/s0 = PCS is not capable of operating at 40 Gb/s

RO

3.4.6:2 Reserved for future speeds Value always 0, writes ignored RO


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45.2.3.7 10G PCS status 2 register (Register 3.8)

The assignment of bits in the 10G PCS status 2 register is shown in Table 45–87. All the bits in the 10G PCSstatus 2 register are read only; a write to the 10G PCS status 2 register shall have no effect

Change Table 45-87 for 40 Gb/s and 100 Gb/s PCS ability:

Insert before 45.2.3.7.4 for 40G/100G PCS abilities:

45.2.3.7.4 100GBASE-R capable (3.8.5)

When read as a one, bit 3.8.5 indicates that the PCS is able to support the 100GBASE-R PCS type. Whenread as a zero, bit 3.8.5 indicates that the PCS is not able to support the 100GBASE-R PCS type.

45.2.3.7.5 40GBASE-R capable (3.8.4)

When read as a one, bit 3.8.4 indicates that the PCS is able to support the 40GBASE-R PCS type. When readas a zero, bit 3.8.4 indicates that the PCS is not able to support the 40GBASE-R PCS type.

Change 45.2.3.11, 12, 13 for naming:

Table 45–86—10G PCS control 2 register bit definitions



3.7.12:0 PCS type selection 2 1 01 1 x = reserved1 0 1 = Select 100GBASE-R PCS type1 0 0 = Select 40GBASE-R PCS type0 1 1 = Select 10GBASE-T PCS type0 1 0 = Select 10GBASE-W PCS type0 0 1 = Select 10GBASE-X PCS type0 0 0 = Select 10GBASE-R PCS type

R/W

aR/W = Read/Write

Table 45–87—10G PCS status 2 register bit definitions


aRO = Read only, LH = Latching high

3.8.9:46 Reserved Ignore when read RO

3.8.5 100GBASE-R capable 1 = PCS is able to support 100GBASE-R PCS type0 = PCS is not able to support 100GBASE-R PCS type

RO

3.8.4 40GBASE-R capable 1 = PCS is able to support 40GBASE-R PCS type0 = PCS is not able to support 40GBASE-R PCS type

RO


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45.2.3.11 10/40/100GBASE-R PCS and 10GBASE-T PCS status 1 register (Register 3.32)

The assignment of bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 1 register is shown in Table45–90. All the bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 1 register are read only; a writeto the 10/40/100GBASE-R and 10GBASE-T PCS status 1 register shall have no effect. A PCS device thatdoes not implement 10/40/100GBASE-R or the 10GBASE-T shall return a zero for all bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 1 register. It is the responsibility of the STA management entityto ensure that a port type is supported by all MMDs before interrogating any of its status bits. The contentsof register 3.32 are undefined when the 10/40/100GBASE-R PCS or the 10GBASE-T PCS is operating inseed test-pattern mode, PRBS31 test-pattern mode, or PRBS9 test-pattern mode.

45.2.3.11.1 10/40/100GBASE-R and 10GBASE-T receive link status (3.32.12)

When read as a one, bit 3.32.12 indicates that the PCS is in a fully operational state. When read as a zero, bit3.32.12 indicates that the PCS is not fully operational. This bit is a reflection of the PCS_status variabledefined in 49.2.14.1 for 10GBASE-R, and in 55.3.6.1 for 10GBASE-T and in 152.2.18.1 for 40/100GBASE-R.

45.2.3.11.2 PRBS9 pattern testing ability (3.32.3)

When read as a one, bit 3.32.3 indicates that the PCS is able to support PRBS9 pattern testing of its transmit-ter. When read as a zero, bit 3.32.3 indicates that the PCS is not able to support PRBS9 pattern testing of itstransmitter. If the PCS is able to support PRBS9 pattern testing of its transmitter then the pattern generationis controlled using bit 3.42.6.

Table 45–90—10/40/100GBASE-R and 10GBASE-T PCS status 1 register bit definitions


aRO = Read only

3.32.15:13 Reserved Value always 0, writes ignored RO

3.32.12 10/40/100GBASE-R and 10GBASE-T receive link status

1 = 10/40/100GBASE-R or 10GBASE-T PCS receive link up0 = 10/40/100GBASE-R or 10GBASE-T PCS receive link down

RO


3.32.3 PRBS9 pattern testing ability

1 = PCS is able to support PRBS9 pattern testing0 = PCS is not able to support PRBS9 pattern testing

RO

3.32.2 PRBS31 pattern testing ability

1 = PCS is able to support PRBS31 pattern testing0 = PCS is not able to support PRBS31 pattern testing

RO

3.32.1 10/40/100GBASE-R and 10GBASE-T PCS high BER

1 = 10/40/100GBASE-R or 10GBASE-T PCS reporting a high BER0 = 10/40/100GBASE-R or 10GBASE-T PCS not reporting a high BER

RO

3.32.0 10/40/100GBASE-R and 10GBASE-T PCS block lock

1 = 10/40/100GBASE-R or 10GBASE-T PCS locked to received blocks0 = 10/40/100GBASE-R or 10GBASE-T PCS not locked to received blocks

RO


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45.2.3.11.3 PRBS31 pattern testing ability (3.32.2)

When read as a one, bit 3.32.2 indicates that the PCS is able to support PRBS31 pattern testing. When readas a zero, bit 3.32.2 indicates that the PCS is not able to support PRBS31 pattern testing. If the PCS is able tosupport PRBS31 pattern testing then the pattern generation and checking is controlled using bits 3.42.5:4.

45.2.3.11.4 10/40/100GBASE-R and 10GBASE-T PCS high BER (3.32.1)

For 10/40/100GBASE-R, when read as a one, bit 3.32.1 indicates that the 64B/66B receiver is detecting aBER of ≥ 10–4. When read as a zero, bit 3.32.1 indicates that the 64B/66B receiver is detecting a BER of< 10–4. This bit is a direct reflection of the state of the hi_ber variable in the 64B/66B state diagram and isdefined in 49.2.13.2.2.

For 10GBASE-T, when read as a one, bit 3.32.1 indicates that the 64B/65B receiver is detecting a BERof ≥ 10–4. When read as a zero, bit 3.32.1 indicates that the 64B/65B receiver is detecting a BER of < 10–4.This bit is a direct reflection of the state of the hi_lfer variable in the 64B/65B state diagram and is defined in55.3.6.1.

45.2.3.11.5 10/40/100GBASE-R and 10GBASE-T PCS block lock (3.32.0)

When read as a one, bit 3.32.0 indicates that the 64B/66B receiver for 10/40/100GBASE-R or the 64B/65Breceiver for the 10GBASE-T has block lock. When read as a zero, bit 3.32.0 indicates that the 64B/66Breceiver for 10/40/100GBASE-R or the 64B/65B receiver for the 10GBASE-T has not got achieved blocklock. This bit is a direct reflection of the state of the block_lock variable in the 64B/66B state diagram and isdefined in 49.2.13.2.2 for 10GBASE-R PCS. For the 10GBASE-T PCS the block_lock variable in the 64B/65B state diagram is defined in 55.3.2.3. For a multi-lane PCS this bit indicates that the receiver has bothblock lock and alignment for all lanes and is identical to 3.50.12 (see 45.2.3.17a.1).

45.2.3.12 10/40/100GBASE-R and 10GBASE-T PCS status 2 register (Register 3.33)

The assignment of bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 2 register is shown inTable 45–91. All the bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 2 register are read only; awrite to the 10/40/100GBASE-R and 10GBASE-T PCS status 2 register shall have no effect. A PCS devicethat does not implement 10/40/100GBASE-R or 10GBASE-T shall return a zero for all bits in the 10/40/100GBASE-R and 10GBASE-T PCS status 2 register. It is the responsibility of the STA management entityto ensure that a port type is supported by all MMDs before interrogating any of its status bits. The contentsof register 3.33 are undefined when the 10/40/100GBASE-R or the 10GBASE-T PCS is operating seed test-pattern mode, PRBS31 test-pattern mode, or PRBS9 test-pattern mode.

Table 45–91—10/40/100GBASE-R and 10GBASE-T PCS status 2 register bit definitions


3.33.15 Latched block lock 1 = 10/40/100GBASE-R or 10GBASE-T PCS has block lock0 = 10/40/100GBASE-R or 10GBASE-T PCS does not have block lock

RO/LL

3.33.14 Latched high BER 1 = 10/40/100GBASE-R or 10GBASE-T PCS has reported a high BER0 = 10/40/100GBASE-R or 10GBASE-T PCS has not reported a high BER

RO/LH

3.33.13:8 BER BER counter RO/NR

3.33.7:0 Errored blocks Errored blocks counter RO/NR


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45.2.3.12.1 Latched block lock (3.33.15)

When read as a one, bit 3.33.15 indicates that the 10/40/100GBASE-R or the 10GBASE-T PCS hasachieved block lock. When read as a zero, bit 3.33.15 indicates that the 10/40/100GBASE-R or the10GBASE-T PCS has lost block lock.

The latched block lock bit shall be implemented with latching low behavior.

This bit is a latching low version of the 10/40/100GBASE-R and 10GBASE-T PCS block lock status bit(3.32.0).

45.2.3.12.2 Latched high BER (3.33.14)

When read as a one, bit 3.33.14 indicates that the 10/40/100GBASE-R or the 10GBASE-T PCS has detecteda high BER. When read as a zero, bit 3.33.14 indicates that the 10/40/100GBASE-R or the 10GBASE-TPCS has not detected a high BER.

The latched high BER bit shall be implemented with latching high behavior.

This bit is a latching high version of the 10/40/100GBASE-R and 10GBASE-T PCS high BER status bit(3.32.1).

45.2.3.12.3 BER(3.33.13:8)

The BER counter is a six bit count as defined by the ber_count variable in 49.2.14.2 for 10/40/100GBASE-R and defined by the lfer_count variable in 55.3.6.2 for 10GBASE-T. These bits shall be reset to all zeroswhen the 10/40/100GBASE-R and 10GBASE-T PCS status 2 register is read by the management function orupon execution of the PCS reset. These bits shall be held at all ones in the case of overflow.

45.2.3.12.4 Errored blocks (3.33.7:0)

The errored blocks counter is an eight bit count defined by the errored_block_count counter specified in49.2.14.2 for 10/40/100GBASE-R and defined by the errored_block_count variable in 55.3.6.2 for10GBASE-T. These bits shall be reset to all zeros when the errored blocks count is read by the managementfunction or upon execution of the PCS reset. These bits shall be held at all ones in the case of overflow.

45.2.3.13 10/40/100GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37)

The assignment of bits in the 10/40/100GBASE-R PCS test pattern seed A registers is shown in Table45–92. This register is only required when the 10/40/100GBASE-R capability is supported. If both 10/40/100GBASE-R and 10GBASE-W capability is supported, then this register may either ignore writes andreturn zeros for reads when in 10GBASE-W mode or may function as defined for 10/40/100GBASE-R. Foreach seed register, seed bits are assigned to register bits in order with the lowest numbered seed bit for thatregister being assigned to register bit 0.

The A seed for the pseudo random test pattern is held in registers 3.34 through 3.37. The test-pattern meth-odology is described in 49.2.8.

aRO = Read only, LL = Latching low, LH = Latching high, NR = Non Roll-over


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Change 45.2.3.15, 16 for naming:

45.2.3.15 10/40/100GBASE-R PCS test-pattern control register (Register 3.42)

The assignment of bits in the 10/40/100GBASE-R PCS test-pattern control register is shown in Table 45–94.This register is only required when the 10/40/100GBASE-R capability is supported. If both 10/40/100GBASE-R and 10GBASE-W capability is supported, then this register may either ignore writes andreturn zeros for reads when in 10GBASE-W mode or may function as defined for 10/40/100GBASE-R. Thetest-pattern methodology is described in 49.2.8.

Table 45–92—10GBASE-R PCS test pattern seed A 0-3 register bit definitions



3.37.9:0 Test pattern seed A 3 Test pattern seed A bits 48-57 R/W




aR/W = Read/Write

Table 45–94—10/40/100GBASE-R PCS test-pattern control register bit definitions


aR/W = Read/Write


3.42.6 PRBS9 transmit test-pat-tern enable

1 = Enable PRBS9 test-pattern mode on the transmit path0 = Disable PRBS9 test-pattern mode on the transmit path

R/W

3.42.5 PRBS31 receive test-pat-tern enable

1 = Enable PRBS31 test-pattern mode on the receive path0 = Disable PRBS31 test-pattern mode on the receive path

R/W

3.42.4 PRBS31 transmit test-pat-tern enable

1 = Enable PRBS31 test-pattern mode on the transmit path0 = Disable PRBS31 test-pattern mode on the transmit path

R/W

3.42.3 Transmit test-pattern enable

1 = Enable transmit test pattern0 = Disable transmit test pattern

R/W

3.42.2 Receive test-pattern enable 1 = Enable receive test-pattern testing0 = Disable receive test-pattern testing

R/W

3.42.1 Test-pattern select 1 = Square wave test pattern0 = Pseudo random test pattern

R/W

3.42.0 Data pattern select 1 = Zeros data pattern0 = LF data pattern

R/W


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45.2.3.15.1 PRBS9 transmit test-pattern enable (3.42.6)

If the PCS supports the optional PRBS9 pattern testing (indicated by bit 3.32.3), the mandatory transmit test-pattern enable bit (3.42.3) is not one, and the optional PRBS31 transmit test-pattern enable bit (3.42.4) is notone, then when bit 3.42.6 is set to one the PCS shall transmit PRBS9. When bit 3.42.6 is set to zero, the PCSshall not generate PRBS9. The PRBS9 test-pattern is specified in 68.6.1. The behavior of the PCS when inPRBS9 test-pattern mode is specified in Clause 49.

45.2.3.15.2 PRBS31 receive test-pattern enable (3.42.5)

If the PCS supports the optional PRBS31 pattern testing advertised in bit 3.32.2 and the mandatory receivetest-pattern enable bit (3.42.2) is not one, setting bit 3.42.5 to a one shall set the receive path of the PCS intothe PRBS31 test-pattern mode. The number of errors received during a PRBS31 pattern test are recorded inregister 3.43. Setting bit 3.42.5 to a zero shall disable the PRBS31 test-pattern mode on the receive path ofthe PCS. The behavior of the PCS when in PRBS31 test-pattern mode is specified in Clause 49

45.2.3.15.3 PRBS31 transmit test-pattern enable (3.42.4)

If the PCS supports the optional PRBS31 pattern testing advertised in bit 3.32.2 and the mandatory transmittest-pattern enable bit (3.42.3) is not one, then setting bit 3.42.4 to a one shall set the transmit path of thePCS into the PRBS31 test-pattern mode. Setting bit 3.42.4 to a zero shall disable the PRBS31 test-patternmode on the transmit path of the PCS. The behavior of the PCS when in PRBS31 test-pattern mode is speci-fied in Clause 49

45.2.3.15.4 Transmit test-pattern enable (3.42.3)

When bit 3.42.3 is set to a one, pattern testing is enabled on the transmit path. When bit 3.42.3 is set to azero, pattern testing is disabled on the transmit path.


45.2.3.15.5 Receive test-pattern enable (3.42.2)

When bit 3.42.2 is set to a one, pattern testing is enabled on the receive path. When bit 3.42.2 is set to a zero,pattern testing is disabled on the receive path.


45.2.3.15.6 Test-pattern select (3.42.1)

When bit 3.42.1 is set to a one, the square wave test pattern is used for pattern testing. When bit 3.42.1 is setto a zero, the pseudo random test pattern is used for pattern testing.


45.2.3.15.7 Data pattern select (3.42.0)

When bit 3.42.0 is set to a one, the zeros data pattern is used for pattern testing. When bit 3.42.0 is set to azero, the LF data pattern is used for pattern testing.



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45.2.3.16 10/40/100GBASE-R PCS test-pattern error counter register (Register 3.43)

The assignment of bits in the 10/40/100GBASE-R PCS test-pattern error counter register is shown in Table45–95. This register is only required when the 10/40/100GBASE-R capability is supported. If both 10/40/100GBASE-R and 10GBASE-W capability is supported, then this register may either ignore writes andreturn zeros for reads when in 10GBASE-W mode, or may function as defined for 10/40/100GBASE-R.

The test-pattern error counter is a sixteen bit counter that contains the number of errors received during apattern test. These bits shall be reset to all zeros when the test-pattern error counter is read by the manage-ment function or upon execution of the PCS reset. These bits shall be held at all ones in the case of overflow.The test-pattern methodology is described in 49.2.12. This counter will count either block errors or bit errorsdependent on the test mode (see 49.2.12).

Insert before 45.2.3.17 for PCS alignment status:

45.2.3.17a Multi-lane BASE-R PCS alignment status register 1 (Register 3.50)

The assignment of bits in the Multi-lane BASE-R PCS alignment status register 1 is shown in Table 45–96.All the bits in the Multi-lane BASE-R PCS alignment status register are read only; a write to the Multi-laneBASE-R PCS alignment status register shall have no effect. A PCS device that does not implement multi-lane BASE-R PCS shall return a zero for all bits in the BASE-R PCS alignment status register. A device thatimplements multi-lane BASE-R PCS shall return a zero for all bits in the Multi-lane BASE-R PCS align-ment status register that are not required for the PCS configuration. It is the responsibility of the STA man-agement entity to ensure that a port type is supported by all MMDs before interrogating any of its status bits.

45.2.3.17a.1 Multi-lane BASE-R PCS alignment status (3.50.12)

When read as a one, bit 3.50.12 indicates that the PCS has locked and aligned all receive lanes. When read asa zero, bit 3.50.12 indicates that the PCS has not locked and aligned all receive lanes.

45.2.3.17a.2 Lane 7 lock (3.50.7)

When read as a one, bit 3.50.7 indicates that the PCS receive lane 7 is locked. When read as a zero, bit 3.50.7indicates that the PCS receive lane 7 is not locked. This bit reflects the state of block_lock[7] (see152.2.17.2.2).

45.2.3.17a.3 Lane 6 lock (3.50.6)


Table 45–95—10GBASE-R PCS test-pattern error counter register bit definitions


aRO = Read only

3.43.15:0 Test-pattern error counter Error counter RO


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45.2.3.17a.4 Lane 5 lock (3.50.5)


45.2.3.17a.5 Lane 4 lock (3.50.4)


45.2.3.17a.6 Lane 3 lock (3.50.3)


Table 45–96a—Multi-lane BASE-R PCS alignment status register bit definitions



3.50.12 PCS lane alignment status 1 = PCS receive lanes locked and aligned0 = PCS receive lanes not locked and aligned

RO


3.50.7 Lane 7 lock 1 = Lane 7 is locked0 = Lane 7 is not locked

RO


RO


RO


RO


RO


RO


RO


RO

aRO = Read only


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45.2.3.17a.7 Lane 2 lock (3.50.2)


45.2.3.17a.8 Lane 1 lock (3.50.1)


45.2.3.17a.9 Lane 0 lock (3.50.0)



The assignment of bits in the Multi-lane BASE-R PCS alignment status register 2 is shown in Table 45–97.All the bits in the Multi-lane BASE-R PCS alignment status register are read only; a write to the Multi-laneBASE-R PCS alignment status register shall have no effect. A PCS device that does not implement multi-lane BASE-R PCS shall return a zero for all bits in the Multi-lane BASE-R PCS alignment status register. Adevice that implements multi-lane BASE-R PCS shall return a zero for all bits in the Multi-lane BASE-RPCS alignment status register that are not required for the PCS configuration. It is the responsibility of theSTA management entity to ensure that a port type is supported by all MMDs before interrogating any of itsstatus bits.

45.2.3.18a.1 Lane 19 lock (3.51.11)

When read as a one, bit 3.51.11 indicates that the PCS receive lane 19 is locked. When read as a zero, bit3.51.11 indicates that the PCS receive lane 19 is not locked. This bit reflects the state of block_lock[19] (see152.2.17.2.2).

45.2.3.18a.2 Lane 18 lock (3.51.10)


45.2.3.18a.3 Lane 17 lock (3.51.9)


45.2.3.18a.4 Lane 16 lock (3.51.9)



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45.2.3.18a.5 Lane 15 lock (3.51.3)


45.2.3.18a.6 Lane 14 lock (3.51.2)


Table 45–97a—Multi-lane BASE-R PCS alignment status register 2 bit definitions




RO


RO


RO


RO


RO


RO


RO


RO


RO


RO


RO


RO

aRO = Read only


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45.2.3.18a.7 Lane 13 lock (3.51.1)


45.2.3.18a.8 Lane 12 lock (3.51.0)


45.2.3.18a.9 Lane 11 lock (3.51.3)


45.2.3.18a.10 Lane 10 lock (3.51.2)


45.2.3.18a.11 Lane 9 lock (3.51.1)


45.2.3.18a.12 Lane 8 lock (3.51.0)



The assignment of bits in the Multi-lane BASE-R PCS alignment status register 3 is shown in Table 45–98.All the bits in the Multi-lane BASE-R PCS alignment status register 3 are read only; a write to the Multi-lane BASE-R PCS alignment status register 3 shall have no effect. A PCS device that does not implementmulti-lane BASE-R PCS shall return a zero for all bits in the Multi-lane BASE-R PCS alignment status reg-ister 3. A device that implements multi-lane BASE-R PCS shall return a zero for all bits in the Multi-laneBASE-R PCS alignment status register3 that are not required for the PCS configuration. It is the responsibil-ity of the STA management entity to ensure that a port type is supported by all MMDs before interrogatingany of its status bits.

45.2.3.19a.1 Lane 7 aligned (3.52.7)

When read as a one, bit 3.50.7 indicates that the PCS receive lane 7 alignment marker is locked. When readas a zero, bit 3.50.7 indicates that the PCS receive lane 7 alignment marker is not locked. This bit reflects thestate of am_lock[7] (see 152.2.17.2.2).


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45.2.3.19a.2 Lane 6 aligned (3.52.6)


45.2.3.19a.3 Lane 5 aligned (3.52.5)


45.2.3.19a.4 Lane 4 aligned (3.52.4)


45.2.3.19a.5 Lane 3 aligned (3.52.3)





3.52.7 Lane 7 aligned 1 = Lane 7 alignment marker is locked0 = Lane 7 alignment marker is not locked

RO


RO


RO


RO


RO


RO


RO


RO

aRO = Read only


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45.2.3.19a.6 Lane 2 aligned (3.52.2)


45.2.3.19a.7 Lane 1 aligned (3.52.1)


45.2.3.19a.8 Lane 0 aligned (3.52.0)



The assignment of bits in the Multi-lane BASE-R PCS alignment status register 4 is shown in Table 45–98.All the bits in the Multi-lane BASE-R PCS alignment status register 2 are read only; a write to the Multi-lane BASE-R PCS alignment status register 2 shall have no effect. A PCS device that does not implementmulti-lane BASE-R PCS shall return a zero for all bits in the Multi-lane BASE-R PCS alignment status reg-ister 2. A device that implements multi-lane BASE-R PCS shall return a zero for all bits in the Multi-laneBASE-R PCS alignment status register 2 that are not required for the PCS configuration. It is the responsi-bility of the STA management entity to ensure that a port type is supported by all MMDs before interrogat-ing any of its status bits.

45.2.3.20a.1 Lane 19 aligned (3.53.11)

When read as a one, bit 3.51.11 indicates that the PCS receive lane 19 alignment marker is locked. Whenread as a zero, bit 3.51.11 indicates that the PCS receive lane 19 alignment marker is not locked. This bitreflects the state of am_lock[19] (see 152.2.17.2.2).

45.2.3.20a.2 Lane 18 aligned (3.53.10)

When read as a one, bit 3.51.10 indicates that the PCS receive lane 18 alignment marker is locked. Whenread as a zero, bit 3.51.10 indicates that the PCS receive lane 18 alignment marker is not locked. This bitreflects the state of am_lock[18] (see 152.2.17.2.2).

45.2.3.20a.3 Lane 17 aligned (3.53.9)

When read as a one, bit 3.51.9 indicates that the PCS receive lane 17 alignment marker is locked. When readas a zero, bit 3.51.9 indicates that the PCS receive lane 17 alignment marker is not locked. This bit reflectsthe state of am_lock[17] (see 152.2.17.2.2).

45.2.3.20a.4 Lane 16 aligned (3.53.9)



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45.2.3.20a.5 Lane 15 aligned (3.53.3)


45.2.3.20a.6 Lane 14 aligned (3.53.2)






RO


RO


RO


RO


RO


RO


RO


RO


RO


RO


RO


RO

aRO = Read only


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45.2.3.20a.7 Lane 13 aligned (3.53.1)


45.2.3.20a.8 Lane 12 aligned (3.53.0)


45.2.3.20a.9 Lane 11 aligned (3.53.3)


45.2.3.20a.10 Lane 10 aligned (3.53.2)


45.2.3.20a.11 Lane 9 aligned (3.53.1)


45.2.3.20a.12 Lane 8 aligned (3.53.0)


45.2.7 Auto-Negotiation registers

Change 45.2.7.12 for backplane 40 Gb/s and naming:


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45.2.7.12 Backplane Ethernet status (Register 7.48)

The assignment of bits in the Backplane Ethernet status register is shown in Table 45–142.

45.2.7.12.1 10GBASE-KR Backplane FEC negotiated (7.48.4)

When the Auto-Negotiation process has completed as indicated by the AN complete bit (7.1.5), bit 7.48.4indicates that 10GBASE-KR backplane FEC operation has been negotiated. This bit is set only if10GBASE-KR a backplane PHY supporting FEC operation has also been negotiated.

45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8)

When the AN process has been completed as indicated by the AN complete bit, one of the three these bits(1000BASE-KX, 10GBASE-KX4, 10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4, 100GBASE-CR10)indicates the negotiated port type. Only one of the three these bits is set depending on the priority resolutionfunction.

45.2.7.12.3 Backplane Ethernet AN ability (7.48.0)

If a 1000BASE-KX, 10GBASE-KX4 or 10GBASE-KR PHY backplane type is implemented, this bit shallbe set to 1.

Table 45–142—Backplane Ethernet status register (Register 7.48) bit definitions

Bit(s) Name Description ROa

aRO = Read only


7.48.8 100GBASE-CR10 1 = PMA/PMD is negotiated to perform 100GBASE-CR100 = PMA/PMD is not negotiated to perform 100GBASE-CR10 RO

7.48.7 Reserved Ignore on read RO

7.48.6 40GBASE-CR4 1 = PMA/PMD is negotiated to perform 40GBASE-CR40 = PMA/PMD is not negotiated to perform 40GBASE-CR4 RO

7.48.5 40GBASE-KR4 1 = PMA/PMD is negotiated to perform 40GBASE-KR40 = PMA/PMD is not negotiated to perform 40GBASE-KR4 RO

7.48.4 10GBASE-KR Back-plane FEC negotiated

1 = PMA/PMD is negotiated to perform 10GBASE-KR Back-plane FEC0 = PMA/PMD is not negotiated to perform 10GBASE-KR Backplane FEC

RO

7.48.3 10GBASE-KR 1 = PMA/PMD is negotiated to perform 10GBASE-KR0 = PMA/PMD is not negotiated to perform 10GBASE-KR RO

7.48.2 10GBASE-KX4 1 = PMA/PMD is negotiated to perform 10GBASE-KX40 = PMA/PMD is not negotiated to perform 10GBASE-KX4 RO

7.48.1 1000BASE-KX 1 = PMA/PMD is negotiated to perform 1000BASE-KX0 = PMA/PMD is not negotiated to perform 1000BASE-KX RO

7.48.0 BP AN ability If a 1000BASE-KX, 10GBASE-KX4 or 10GBASE-KR back-plane PHY type is implemented, this bit is set to 1 RO


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When read as a one, bit 7.48.0 indicates that the PMA/PMD has the ability to perform Backplane EthernetAN. When read as a zero, bit 7.48.0 indicates that the PMA/PMD lacks the ability to perform BackplaneEthernet AN.


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45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, MDIO interface1

[Editor’s note (to be removed prior to publication) - Insert corresponding PICS, for new PMA/PMD,PCS, and Auto-Neg for 40 Gb/s and 100 Gb/s]

45.5.3.2 PMA/PMD MMD options

45.5.3.6 PCS options

45.5.3.8 Auto-Negotiation options

1Copyright release for PICS proformas: Users of this standard may freely reproduce the PICS proforma in this subclause so that it canbe used for its intended purpose and may further publish the completed PICS.


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68

Draft Revision to IEEE Std 802.3-2005 IEEE Draft P802.3/D2.1 - Section 5IEEE 802.3ay Maintenance 9 (Revision) Task Force 18th February 2008

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69. Introduction to Ethernet operation over electrical backplanes

69.1 Overview

69.1.1 Scope

Change second paragraph as follows:

Backplane Ethernet supports the IEEE 802.3 MAC operating at 1000 Mb/s, or 10 Gb/s or 40 Gb/s. For 1000Mb/s operation, the family of 1000BASE-X Physical Layer signaling systems is extended to include1000BASE-KX. For 10 Gb/s operation, two Physical Layer signaling systems are defined. For operationover four logical lanes, the 10GBASE-X family is extended to include 10GBASE-KX4. For serial operation,the 10GBASE-R family is extended to include 10GBASE-KR. For 40 Gb/s operation, there is40GBASE-KR4 which operates over four lanes.

69.1.2 Objectives

Change d) as follows:

d) Support operation of the following PHY over differential, controlled impedance traces on a printedcircuit board with 2 connectors and total length up to at least 1 m consistent with the guidelines ofAnnex 69B.

i) a 1 Gb/s PHYii) a 4-lane 10 Gb/s PHYiii) single-lane 10 Gb/s PHYiv) a 4-lane 40 Gb/s PHY

69.1.3 Relationship of Backplane Ethernet to the ISO OSI reference model

Change Figure 69-1 as follows:


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.

69.2 Summary of Backplane Ethernet Sublayers

69.2.1 Reconciliation sublayer and media independent interfaces

Change paragraph as follows:

The Clause 35 RS and GMII, and the Clause 46 RS and XGMII, and the Clause 151 RS and XLGMII areboth employed for the same purpose in Backplane Ethernet, that being the interconnection between theMAC sublayer and the PHY.

69.2.2 Physical Layer signaling systems

Change first sentence of third paragraph as follows:

Finally, Backplane Ethernet also extends the family of 10GBASE-R Physical Layer signaling systems toinclude the 10GBASE-KR.

Insert paragraph after third paragraph of subclause as follows:

Backplane Ethernet also specifies 40GBASE-KR4. This embodiment employs the PCS defined in Clause152, the PMA defined in Clause 153 and the PMD defined in Clause 154 and specifies 40 Gb/s operationover four differential paths in each direction for a total of eight pairs.

Figure 69–1—Architectural positioning of Backplane Ethernet

APPLICATION

PRESENTATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LLC (LOGICAL LINK CONTROL) OR OTHER MAC CLIENT

MAC CONTROL (OPTIONAL)

MAC — MEDIA ACCESS CONTROL

HIGHER LAYERS

LANCSMA/CDLAYERS

RECONCILIATION

8B/10B PCS

PMA

PMD

MDI

GMII

MEDIUM

8B/10B PCS

PMA

PMD

MDI

XGMII

MEDIUM

64B/66B PCS

PMA

PMD

MDI

XGMII

MEDIUM

1000BASE-KX 10GBASE-KX4 10GBASE-KR

GMII = GIGABIT MEDIA INDEPENDENT INTERFACEMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYER

PMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXGMII = 10 GIGABIT MEDIA INDEPENDENT INTERFACE

PHY = PHYSICAL LAYER DEVICE

AN AN AN

AN = AUTO-NEGOTIATION

FEC

FEC = FORWARD ERROR CORRECTION

MDI

XLGMII

MEDIUM

40GBASE-KR4

40GBASE-R PCS

PMA

PMD

AN

FEC

PHY

XLGMII = 40 GIGABIT MEDIA INDEPENDENT INTERFACE

PH

Y

PH

Y

PHY


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Replace Table 69-1 with the following:

69.2.5 Management

Change text as follows:

Managed objects, attributes, and actions are defined for all Backplane Ethernet components. Clause 30 con-solidates all IEEE 802.3 management specifications so that 10 Mb/s, 100 Mb/s, 1000 Mb/s and 10 Gb/sagents of different speed can be managed by existing network management stations with little or no modifi-cation to the agent code.

69.3 Delay constraints

Add paragraph at end of subclause as follows:

For 40GBASE-KR4 delay constraints are specified in Clauses 150, 152, 153 and 154.

Table 69–1—Nomenclature and clause correlation

Nomenclature

Clause

36 48 49 51 70 71 72 73 74 152 153 154

1000

BA

SE-X

PC

S/PM

A

10G

BA

SE-X

PC

S/PM

A

10G

BA

SE-R

PC

S

Seri

al P

MA

1000

BA

SE-K

X

PMD

10G

BA

SE-K

X4

PMD

10G

BA

SE-K

R

PMD

AU

TO-

NE

GO

TIA

TIO

N

BA

SE-R

FE

C

40G

BA

SE-K

R4

PCS

40G

BA

SE-K

R4

PMA

40G

BA

SE-K

R4

PMD

1000BASE-KX Ma

aO = Optional, M = Mandatory

M M

10GBASE-KX4 M M M

10GBASE-KR M M M M O

40GBASE-KR4 M O M M M


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73. Auto-Negotiation for Backplane Ethernet

Add a note under the Clause title:

Note that the Auto-Negotiation defined in this clause was originally intended for use with Backplane Ethernet PHYs.The use is not restricted to Backplane Ethernet PHYs and it may be specified for use with any compatible media andPHY configuration.

73.3 Functional specifications

Change third paragraph as follows:

These functions shall comply with the state diagrams from Figure 73-9 through Figure 73-11. The Auto-Negotiation functions shall interact with the technology-dependent PHYs through the Technology-Depen-dent interface (see 73.9). Technology-Dependent PHYs include 1000BASE-KX, 10GBASE-KX4, and10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4 and 100GBASE-CR10.

73.5.1 DME page encoding


DME pages can be transmitted by local devices capable of operating in 1 Gb/s (1000BASE-KX) mode,10 Gb/s over 4 lane (10GBASE-KX4) mode or 10 Gb/s over 1 lane (10GBASE-KR) mode and by devicescapable of operating at higher speeds.

73.6.4 Technology Ability Field

Change Table 73-4 as follows:

.

Change last sentence as follows:

Table 73–1—Technology Ability Field encoding

Bit Technology

A0 1000BASE-KX

A1 10GBASE-KX4

A2 10GBASE-KR

A3 40GBASE-KR4

A4 40GBASE-CR4

A5 100GBASE-CR10

A3 A6 through A24 Reserved for future technology


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The fields A[24:3 6] are reserved for future use. Reserved fields shall be sent as zero and ignored on receive.

73.6.5 FEC capability


FEC (F0:F1) is encoded in bits D46:D47 of the base link codeword. The two FEC bits are used as follows:

a) F0 is FEC ability.b) F1 is FEC requested.

When the FEC ability bit is set to logical one, it indicates that the 10GBASE-KR PHY has FEC ability (seeClause 74). When the FEC requested bit is set to logical one, it indicates a request to enable FEC on the link.

Since the local device and the link partner may have set the FEC capability bits differently and this FECcapability is only used with 10GBASE-KR, the priority resolution function is used to enable FEC in therespective PHYs. The FEC function shall be enabled on the link if 10GBASE-KR, 40GBASE-KR4,40GBASE-CR4 or 100GBASE-CR10 is the HCD technology (see 73.7.6), both devices advertise FEC abil-ity on the F0 bits, and at least one device requests FEC on the F1 bits. If 10GBASE-KR is not the HCD tech-nology, FEC shall not be enabled. If either device does not have FEC ability, FEC shall not be enabled. Ifneither device requests FEC, FEC shall not be enabled even if both devices have FEC ability.

73.7 Receive function requirements


The Receive function detects the DME page sequence, decodes the information contained within, and storesthe data in rx_link_code_word[48:1]. The receive function incorporates a receive switch to control connec-tion to the 1000BASE-KX, 10GBASE-KX4, or 10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4 or100GBASE-CR10 PHYs.

73.7.1 DME page reception


To be able to detect the DME bits, the receiver should have the capability to receive DME signals sent withthe electrical specifications of any IEEE 802.3 Backplane Ethernet the PHY (1000BASE-KX, 10GBASE-KX4, or 10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4 or 100GBASE-CR10). The DME transmit signallevel and receive sensitivity are specified in 73.5.1.1.

73.7.2 Receive Switch function


The Receive Switch function shall enable the receive path from the MDI to a single technology-dependentPHY once a highest common denominator choice has been made and Auto-Negotiation has completed.


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During Auto-Negotiation, the Receive Switch function shall connect the DME page receiver controlled bythe Receive state diagram to the MDI and the Receive Switch function shall also connect the 1000BASE-KX, 10GBASE-KX4, and 10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4 and 100GBASE-CR10 PMAreceivers to the MDI if the PMAs are present.

73.7.4.1 Parallel Detection function


A local device shall provide Parallel Detection for 1000BASE-KX and 10GBASE-KX4 if it supports thosePHYs. Parallel Detection is not performed for 10GBASE-KR. Additionally, parallel detection may be usedfor 10GBASE-CX4. System developers should distinguish between parallel detection of 10GBASE-KX4and 10GBASE-CX4 based on the MDI and media type present. Parallel Detection shall be performed bydirecting the MDI receive activity to the PHY. This detection may be done in sequence between detection ofDME pages and detection of each supported PHY. If at least one of the 1000BASE-KX, or 10GBASE-KX4establishes link_status=OK, the LINK STATUS CHECK state is entered and the autoneg_wait_timer isstarted. If exactly one link_status=OK indication is present when the autoneg_wait_timer expires, thenAuto-Negotiation shall set link_control=ENABLE for the PHY indicating link_status=OK. If a PHY isenabled, the Arbitration function shall set link_control=DISABLE to all other PHYs and indicate that Auto-Negotiation has completed. On transition to the AN GOOD CHECK state from the LINK STATUS CHECKstate, the Parallel Detection function shall set the bit in the AN LP base page ability registers (See 45.2.7.7)corresponding to the technology detected by the Parallel Detection function.

73.7.6 Priority Resolution function

Change Table 73-2 as follows:.

73.10.1 State diagram variables


Table 73–2—Priority Resolution

Priority Technology Capability

1 100GBASE-CR10 100 Gb/s 10 lane, highest priority

2 40GBASE-CR4 40 Gb/s 4 lane

3 40GBASE-KR4 40 Gb/s 4 lane

14 10GBASE-KR 10 Gb/s 1 lane, highest priority

25 10GBASE-KX4 10 Gb/s 4 lane, second highest priority

6 10GBASE-CX4 10 Gb/s 4 lane

37 1000BASE-KX 1 Gb/s 1 lane, third highest lowest priority


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A variable with “_[x]” appended to the end of the variable name indicates a variable or set of variables asdefined by “x”. “x” may be as follows:

all; represents all specific technology-dependent PMAs supported in the local device.

1GKX; represents that the 1000BASE-KX PMA is the signal source.

10GKR; represents that the 10GBASE-KR PMA is the signal source.

10GCX4; represents that the 10GBASE-CX4 PMA is the signal source.

10GKX4; represents that the 10GBASE-KX4 PMA is the signal source.

40GKR4; represents that the 40GBASE-KR4 PMA is the signal source.

40GCR4; represents that the 40GBASE-CR4 PMA is the signal source.

100GCR10;represents that the 100GBASE-CR10 PMA is the signal source.

HCD; represents the single technology-dependent PMA chosen by Auto-Negotiation as the highest common denominator technology through the Priority Resolution or parallel detection function.

notHCD; represents all technology-dependent PMAs not chosen by Auto-Negotiation as the highest common denominator technology through the Priority Resolution or parallel detection function.

PD; represents all of the following that are present: 1000BASE-KX PMA, 10GBASE-CX4, 10GBASE-KX4 PMA, and 10GBASE-KR PMA, 40GBASE-KR4, 40GBASE-CR4, 100GBASE-CR10.

Change single_link_ready as follows:

single_link_readyStatus indicating that DME_receive_idle = true and only one the of the following indications is being received:

1) link_status_[1GKX] = OK2) link_status_[10GKX4] = OK3) link_status_[10GKR] = OK4) link_status_[10GCX4] = OK5) link_status_[40GKR4] = OK6) link_status_[40GCR4] = OK7) link_status_[100GCR10] = OK

Values: false; either zero or more than one of the above three indications are true or an_receive_idle = false.true; Exactly one of the above three indications is true and an_receive_idle = true.

NOTE—This variable is set by this variable definition; it is not set explicitly in the state diagrams.

73.10.2 State diagram timers

Change autoneg_wait_timer as follows:autoneg_wait_timer


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Timer for the amount of time to wait before evaluating the number of link integrity test functions with link_status=OK asserted. The autoneg_wait_timer shall expire 25 ms to 50 ms from the assertion of link_status=OK from the 1000BASE-KX PCS, 10GBASE-KX4 PCS, or 10GBASE-KR PCS.

Change link_fail_inhibit_timer as follows:link_fail_inhibit_timer

Timer for qualifying a link_status=FAIL indication or a link_status=OK indication when a specific technology link is first being established. A link will only be considered “failed” if the link_fail_inhibit_timer has expired and the link has still not gone into the link_status=OK state. The link_fail_inhibit_timer shall expire 40 ms to 50 ms after entering the AN LINK GOOD CHECK state when the link is not 10GBASE-KR 1000BASE-KX or 10GBASE-KX4. Otherwise the The link_fail_inhibit_timer shall expire 500 ms to 510 ms after entering the AN LINK GOOD CHECK state when the link is 10GBASE-KR.

Change Table 73-7 as follows:

Table 73–7—Timer min/max value summary

Parameter Min Value and tolerance Max Units

autoneg_wait_timer 25 50 ms

break_link_timer 60 75 ms

clock_detect_min_timer 4.8 6.2 ns

clock_detect_max_timer 6.6 8.0 ns

data_detect_min_timer 1.6 3.0 ns

data_detect_max_timer 3.4 4.8 ns

interval_timer 3.2 ± 0.01% ns

link_fail_inhibit_timer (when the link is 10GBASE-KR neither 1000BASE-KX nor 10GBASE-KX4)

500 510 ms

link_fail_inhibit_timer(when the link is not 10GBASE-KR 1000BASE-KX or 10GBASE-KX4)

40 50 ms

page_test_min_timer 305 330 ns

page_test_max_timer 350 375 ns


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73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negotiation for Backplane Ethernet2

[Editor’s note (to be removed prior to publication) - Insert corresponding PICS, if any, for Auto-Neg for40 Gb/s backplane PHY]



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74. Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs

[Editor’s note (to be removed prior to publication) - This Clause has been updated to provide generic cov-erage to all BASE-R PHYs including multilane operation for 40 and 100 Gb/s].

Change 74.1 to describe multi-lane operation:

74.1 Overview

This clause specifies an optional Forward Error Correction (FEC) sublayer for 10GBASE-R and otherBASE-R PHYs. The FEC sublayer can be placed in between the PCS and PMA sublayers of the 10GBASE-R and other BASE-R Physical Layer implementations as shown in Figure 74–2 and Figure 74-2a. For amulti-lane BASE-R PHY the FEC sublayer is instantiated for each lane and operates autonomously on a per-lane basis. The FEC provides coding gain to increase the link budget and BER performance. The 10GBASE-KR PHY described in Clause 72 optionally uses the FEC sublayer to increase the performance on a broaderset of backplane channels as defined in Clause 69. The FEC sublayer provides additional margin to accountfor variations in manufacturing and environmental conditions.

Change 74.4.1 to explicitly specify serial BASE-R:

74.4.1 Functional Block Diagram (single lane PHYs)

Figure 74–2 shows the functional block diagram of FEC for 10GBASE-R PHY or single lane BASE-RPHYs and the relationship between the PCS and PMA sublayers.

Add 74.4.2 to show the block diagram for multi lane PHYs:

74.4.2 Functional Block Diagram (single lane PHYs)

Figure 74–2a shows the functional block diagram of FEC for multi-lane BASE-R PHYs and the relationshipbetween the PCS and PMA sublayers.

[Add diagram - based on source from REVay, to be shown in the next draft]

Change 74.7.4.5 to cover error marking for multi-lane implementations:

[Note that terminology to distinguish virtual lanes from physical lanes has not been finalized]

74.7.4.5 FEC decoder

The FEC decoder establishes FEC block synchronization based on repeated decoding of the receivedsequence. Decoding and error correction is performed after FEC synchronization is achieved. There is anoption for the FEC decoder to indicate any decoding errors to the upper layer.

The FEC decoder recovers and extracts the information bits using the parity-check data. In case of success-ful decoding the decoder restores the sync bits in each of the 64B/66B blocks sent to the PCS function, byfirst performing an XOR operation of the received transcode bit with the associated data bit 8 and then gen-erating the two sync bits. When the decoder is configured to indicate decoding error, the decoder indicateserror to the PCS by means of setting both sync bits to the value 11 in the 1st, 9th, 17th, 25th, and 32nd of the32 decoded 64B/66B blocks from the corresponding errored FEC block, thus forcing the PCS sublayer toconsider this block as invalid for a single lane PHY. Multi-lane PHYs require errors to be marked in more ofthe 64B/66B blocks to ensure that detected errors are signaled to the MAC for every frame containing anerror. As the single lane PHY marks each 8th 64B/66B block, so a two lane PHY marks every 4th 64B/66B


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block, a four lane PHY marks every second 64B/66B block and a PHY with 8 or more lanes marks every64B/66B block

The FEC Synchronization process continuously monitors PMA_SIGNAL.indication(SIGNAL_OK). WhenSIGNAL_OK indicates OK, the FEC Synchronization process accepts data units via thePMA_UNITDATA.indication primitive. It attains block synchronization based on the decoding of FECblocks and conveys received 64B/66B blocks to the PCS Receive process. The FEC Synchronization pro-cess sets the sync_status flag to the PCS function to indicate whether the FEC has obtained synchronization.

Change 74.7.4.5.1 to cover error marking for multi-lane implementations:

74.7.4.5.1 FEC (2112,2080) decoding

The FEC decoding function block diagram is shown in Figure 74–6. The decoder processes the 16-bitrx_data-group stream received from the PMA sublayer and descrambles the data using the PN-2112 pseudo-noise sequence as described in 74.7.4.4.1.

The synchronization of the 2112 bit FEC block is established using FEC decoding as described in 74.7.4.7.Each of the 32 65-bit data words is extracted from the recovered FEC block and the 2-bit sync is recon-structed for the 64B/66B codes from the transcode bit as shown in Figure 74–7. The FEC decoder providesan option to indicate decoding errors in the reconstructed sync bits. The sync bits {SH.0, SH.1} take thevalue as described in the following:

a) If decoding is successful (by either the parity match or the FEC block is correctable) and thedescrambled received transcode bit (T) is 1 then the sync bits take a value of {SH.0,SH.1} = 01 or ifthe descrambled received transcode bit (T) is 0 then the sync bits take a value of {SH.0,SH.1} = 10.

b) If the variable FEC_Enable_Error_to_PCS is set to 1 to indicate error to PCS layer and the receivedFEC block has uncorrectable errors then the sync bits for the 1st, 9th, 17th, 25th, and 32nd of the 32decoded 64B/66B blocks take a value of {SH.0,SH.1} = 11 for single lane PHYs. Multi-lane PHYsrequire errors to be marked in more of the 64B/66B blocks. As the single lane PHY marks each 8th64B/66B block, so a two lane PHY marks every 4th 64B/66B block, a four lane PHY marks everysecond 64B/66B block and a PHY with 8 or more lanes marks every 64B/66B block. The sync bitsfor all other 64B/66B blocks take a value as described in item a) above.

c) If the variable FEC_Enable_Error_to_PCS is set to 0 and the received FEC block has uncorrectableerrors then the sync bits take a value as described in item a) above.

This information corresponds to one complete (2112,2080) FEC block that is equal to 32 64B/66B codeblocks. The FEC code (2112, 2080) and its performance is specified in 74.7.1. The FEC (2112, 2080)decoder implementations shall be able to correct up to a minimum of 11-bit burst errors per FEC block.


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74.8 FEC MDIO function mapping

Change Table 74-2 to add extra FEC counter registers:.

Table 74–1—MDIO/FEC variable mapping

MDIO variable PMA/PMD register name Register/ bit number FEC variable

Backplane FEC ability Backplane FEC ability regis-ter 1.170.0 FEC_ability

Backplane FEC Error Indi-cation ability

Backplane FEC ability regis-ter 1.170.1 FEC_Error_Indication_ability

FEC Enable Backplane FEC control reg-ister 1.171.0 FEC_Enable

FEC Enable Error Indication Backplane FEC control reg-ister 1.171.1 FEC_Enable_Error_to_PCS

FEC corrected blocks 0 Backplane FEC corrected blocks counter register lane 0 1.172, 1.173 FEC_corrected_blocks_counter 0

FEC uncorrected blocks 0 Backplane FEC uncorrected blocks counter register lane 0 1.174, 1.175 FEC_uncorrected_blocks_counter

0



1



2



3



4



5



6



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7



8



9

FEC corrected blocks 10Backplane FEC corrected

blocks counter register lane 10

1.212, 1.213 FEC_corrected_blocks_counter 10

FEC uncorrected blocks 10Backplane FEC uncorrected blocks counter register lane

101.214, 1.215 FEC_uncorrected_blocks_counter

10






11






12






13






14




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15






16






17






18






19




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74.11 Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs3

[Editor’s note (to be removed prior to publication) - Insert corresponding PICS, if any, for FEC for 40Gb/s and 100 Gb/s BASE-R PHYs]

3Copyright release for PICS proformas: Users of this standard may freely reproduce the PICS proforma in this subclause so that it can be used for its intended purpose and may further publish the completed PICS.


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150. Introduction to 40 Gb/s and 100 Gb/s baseband network

150.1 Overview

40 and 100 Gigabit Ethernet defines IEEE 802.3 Media Access Control (MAC) parameters, physical layerspecifications, and management parameters for the transfer of IEEE 802.3 format frames at 40 and 100 Gb/s.

150.1.1 Scope

The 40 and 100 Gigabit Ethernet uses the IEEE 802.3 MAC sublayer, connected through a Media Indepen-dent Interface to 40 and 100 Gb/s Physical Layer entities such as 40GBASE-KR4, 40GBASE-CR4,40GBASE-SR4, 40GBASE-LR?, 100GBASE-CR10, 100GBASE-SR10, 100GBASE-LR4, and100GBASE-ER4.

The 40 and 100 Gigabit Ethernet extends the IEEE 802.3 protocol to operating speeds of 40 and 100 Gb/s.The bit rate is faster and the bit times are shorter—both in proportion to the change in bandwidth whilemaintaining maximum compatibility with the installed based of IEEE 802.3 interfaces. The minimum packettransmission time has been reduced by a factor of four for 40 Gb/s and ten for 100 Gb/s.

40 and 100 Gigabit Ethernet is defined for full duplex mode of operation only.

150.1.2 Objectives

The following are the objectives of 40 and 100 Gigabit Ethernet:

a) Support the full duplex Ethernet MAC.b) Preserve the IEEE 802.3 Ethernet frame format utilizing the 802.3 MAC.c) Preserve minimum and maximum frame size of IEEE 802.3 standard.d) Support a BER better than or equal to 10–12 at the MAC/PLS service interface.e) Provide appropriate support for Optical Transport Network (OTN). f) Support a MAC data rate of 40 Gb/s.g) Provide Physical Layer specifications which support 40 Gb/s operation over:

1) at least 10 Km on single mode fiber (SMF) [Editor’s note (to be removed prior to publication)- No baseline has been adopted for this objective.]

2) at least 100 m on OM3 multi mode fiber (MMF)3) at least 10 m over a copper cable assembly4) at least 1 m over a backplane

h) Support a MAC data rate of 100 Gb/s.i) Provide Physical layer specifications which support 100 Gb/s operation over:

5) at least 40 Km on single mode fiber (SMF)6) at least 10 Km on single mode fiber (SMF)7) at least 100 m on OM3 multi mode fiber (MMF)8) at least 10 m over a copper cable assembly

150.1.3 Relationship of 40 and 100 Gigabit Ethernet to the ISO OSI reference model

40 and 100 Gigabit Ethernet couples the IEEE 802.3 (CSMA/CD) MAC to a family of 40 and 100 Gb/sPhysical Layers respectively. The relationships among 40 and 100 Gigabit Ethernet, the IEEE 802.3


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(CSMA/CD) MAC, and the ISO Open System Interconnection (OSI) reference model are shown in Figure150–1.

It is important to note that, while this specification defines interfaces in terms of bits, octets, and frames,implementations may choose other data-path widths for implementation convenience. The only exceptionsare as follows:

a) The XLGMII and CGMII, which, when implemented as a logical interconnection port between theMedia Access Control (MAC) sublayer and the Physical Layer (PHY), uses a 64-bit wide data pathas specified in Clause 151.

b) The management interface, which, when physically implemented as the MDIO/MDC (ManagementData Input/Output and Management Data Clock) at an observable interconnection port, uses a bit-wide data path as specified in Clause 45.

c) The PMA Service Interface, which, when physically implemented as XLAUI (40 Gigabit Attach-ment Unit Interface) at an observable interconnection port, uses a 4 lane data path as specified inAnnex 153A.

d) The PMA Service Interface, which, when physically implemented as CAUI (100 Gigabit Attach-ment Unit Interface) at an observable interconnection port, uses a 10 lane data path as specified inAnnex 153A.

e) The PMD Service Interface, which, when physically implemented at an observable interconnectionport, uses a 4 or 10 lane data path as specified in Clause 156.

Figure 150–1—Architectural positioning of 40 and 100 Gigabit Ethernet

LANCSMA/CD

LAYERS


MAC—MEDIA ACCESS CONTROL

RECONCILIATION

HIGHER LAYERS


PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSI REFERENCE

MODELLAYERS

MDIMEDIUM

PMDPMA

MDIMEDIUM

PMDPMA

XLGMII CGMII

FEC140GBASE-R PCS

FEC1100GBASE-R PCS

40GBASE-R 100GBASE-R

AN1 AN1

PHY PHY

PMD TYPES:MEDIUM:

C = PMD FOR COPPER— 10 m E = PMD FOR FIBER— 40 Km SINGLE MODE FIBERK = PMD FOR BACKPLANES — 1 mL = PMD FOR FIBER—10 Km SINGLE MODE FIBERS = PMD FOR FIBER — 100 m MULTIMODE FIBER

ENCODING:R = 64B/66B ENCODED

NOTE:1 = CONDITIONAL BASED ON PHY TYPE

AN = AUTO-NEGOTIATION SUBLAYERCGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEFEC = FORWARD ERROR CORRECTION SUBLAYERMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE


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f) The MDI as specified in Clause 154 for 40GBASE-KR4, in Clause 155 for 40GBASE-CR4 and100GBASE-CR10, in Clause 156 for 40GBASE-SR4 and 100GBASE-SR10, Clause 157 for40GBASE-LR? and in Clause 158 for 100GBASE-LR4 and 100GBASE-ER4.

150.2 Summary of 40 and 100 Gigabit Ethernet sublayers

150.2.1 Reconciliation Sublayer (RS) and Media Independent Interface (MII)

The Media Independent Interface (Clause 151) provides a logical interconnection between the Media AccessControl (MAC) sublayer and Physical Layer entities (PHY). The MII is not intended to be electricallyinstantiated, rather it can logically connect layers within a device.

The XLGMII supports 40 Gb/s and CGMII supports 100 Gb/s operation through its 64-bit-wide transmit andreceive data paths. The Reconciliation Sublayer provides a mapping between the signals provided at the MII(XLGMII and CGMII) and the MAC/PLS service definition.

While the MII is an optional interface, it is used extensively in this standard as a basis for functional specifi-cation and provides a common service interface for the physical coding sublayers defined in Clause 152.

150.2.2 Management interface (MDIO/MDC)

The MDIO/MDC management interface (Clause 45) provides an interconnection between MDIO Manage-able Devices (MMD) and Station Management (STA) entities.

150.2.3 Physical Layer signaling systems

This standard specifies a family of Physical Layer implementations. The generic term 40 and 100 GigabitEthernet refers to any use of the 40 and 100Gb/s IEEE 802.3 MAC (the 40 and 100 Gigabit Ethernet MAC)coupled with any IEEE 802.3 40GBASE or 100GBASE Physical Layer implementations and the


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Table 150–1 specifies the correlation between nomenclature and clauses. Implementations conforming toone or more nomenclatures shall meet the requirements of the corresponding clauses.

The terms 40GBASE-R and 100GBASE-R refers to a specific family of Physical Layer implementationsbased upon 64B/66B data coding method specified in Clause 152. The term 40GBASE-R refers to a specificfamily of Physical Layer implementations for 40 Gb/s such as 40GBASE-KR4, 40GBASE-CR4 and40GBASE-SR4. The term 100GBASE-R refers to a specific family of Physical Layer implementations for100 Gb/s such as 100GBASE-CR10, 100GBASE-SR10, 100GBASE-LR4 and 100GBASE-ER4.

All 40GBASE-R and 100GBASE-R PHY devices share a common PCS specification defined in Clause 152,and PMA specification defined in Clause 153.

Physical Layer device specifications are contained in Clause 154, Clause 155, Clause 156, and Clause 158.

150.2.4 Auto-Negotiation

Auto-Negotiation provides a linked device with the capability to detect the abilities (modes of operation)supported by the device at the other end of the link, determine common abilities, and configure for jointoperation.

Table 150–1—Nomenclature and clause correlation

Nomenclature

Clause

151 152 153 154 155 156 157 158 73 74R

S / X

LG

MII

RS

/ CG

MII

40G

BA

SE-R

PC

S

100G

BA

SE-R

PC

S

40G

BA

SE-R

PM

A

100G

BA

SE-R

PM

A

40G

BA

SE-K

R4

PMD

40G

BA

SE-C

R4

PMD

100G

BA

SE-C

R10

PM

D

40G

BA

SE-S

R4

PMD

100G

BA

SE-S

R10

PM

D

40G

BA

SE-L

R?

PMD

100G

BA

SE-L

R4

PMD

100G

BA

SE-E

R4

PMD

AU

TO-N

EG

OT

IAT

ION

10G

BA

SE-R

FE

C

40GBASE-KR4 M/O

Ma

aO = Optional, M = Mandatory

M M M O

40GBASE-CR4 M/O M M M M O

40GBASE-SR4 M/O M M M

40GBASE-LR? M/O M M M

100GBASE-CR10 M/O M M M M O

100GBASE-SR10 M/O M M M

100GBASE-LR4 M/O M M M

100GBASE-ER4 M/O M M M


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Clause 73 Auto-Negotiation is used by 40 Gb/s backplane PHY (40GBASE-KR4, see Clause 154) and, 40and 100 Gb/s copper PHYs (40GBASE-CR4 and 100GBASE-CR10, see Clause 155).

150.2.5 Management

Managed objects, attributes, and actions are defined for all 40 and 100 Gigabit Ethernet components.Clause 30 consolidates all IEEE 802.3 management specifications so that 10/100/1000 Mb/s, 10 Gb/s, 40Gb/s and 100 Gb/s agents can be managed by existing network management stations with little or no modifi-cation to the agent code.

150.2.6 Service Interface specification method and notation

[Editor’s note (to be removed prior to publication) - The service interface notation used in 802.3ba PMDPMA clauses have some differences from the notations used for10GbE sublayer interfaces. The differ-ences need to be explained in the introductory Clause 150

The definitions and notation for service interfaces in 802.3ba PMD/PMA will be reconciled, during TFreview, as per the service interface definitions specified in 1.2.2 ].


Predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B) demands that there bean upper bound on the propagation delays through the network. This implies that MAC, MAC Control sub-layer, and PHY implementors must conform to certain delay maxima, and that network planners and admin-istrators conform to constraints regarding the cable topology and concatenation of devices. Table 150–1contains the values of maximum sublayer round-trip (sum of transmit and receive) delay in bit time as spec-ified in 1.4 and pause_quanta as specified in 31B.2.

Table 150–1—Round-trip delay constraints (informative)

Sublayer Maximum(bit time)

Maximum(pause_quanta) Notes

MAC, RS, and MAC Control 8192 16 See 151.1.4.

40GBASE-R PCS TBD TBD See 152.2.19

100GBASE-R PCS TBD TBD See 152.2.19.

40GBASE-R PMA TBD TBD See 153.

40GBASE-KR4 PMD 1024 2 Includes delay associated with backplane medium. See 154.4.

40GBASE-CR4 PMD 2560 5 Includes delay associated with cable medium. See 155.4.

40GBASE-SR4 PMD 1024 2 Includes 2 meters of fiber. See 156.2.1.

40GBASE-LR? PMD TBD TBD Includes 2 meters of fiber. See 157.

100GBASE-CR10 PMD 2560 5 Includes delay associated with cable medium. See 155.4.

100GBASE-SR10 PMD 2048 4 Includes 2 meters of fiber. See 156.2.1.

100GBASE-LR4 PMD 1536 3 Includes 2 meters of fiber. See 158.2.1.

100GBASE-ER4 PMD 1536 3 Includes 2 meters of fiber. See 158.2.1.


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See 44.3 for the calculation of bit time per meter of fiber or electrical cable.

150.4 State diagrams

State diagrams take precedence over text.

The conventions of 1.2 are adopted, along with the extensions listed in 21.5.

150.5 Protocol implementation conformance statement (PICS) proforma

The supplier of a protocol implementation that is claimed to conform to any part of IEEE Std 802.3,Clause 45, Clause 73, Clause 74, Clause 151 through Clause 158, and related Annexes demonstrates com-pliance by completing a protocol implementation conformance statement (PICS) proforma.

A completed PICS proforma is the PICS for the implementation in question. The PICS is a statement ofwhich capabilities and options of the protocol have been implemented. A PICS is included at the end of eachclause as appropriate. Each of the 40 and 100 Gigabit Ethernet PICS conforms to the same notation and con-ventions used in 21.6.


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150.11 Protocol implementation conformance statement (PICS) proforma for Clause 150, 40 Gb/s and 100 Gb/s baseband network systems4

[Editor’s note (to be removed prior to publication) - If appropriate, Insert System PICS, for 40 Gb/s and100Gb/s baseband network systems]



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151. Reconciliation Sublayer (RS) and Media Independent Interface (MII) for 40 Gb/s and 100 Gb/s operation

151.1 Overview

This clause defines the logical and electrical characteristics for the Reconciliation Sublayer (RS) and theMedia Independent Interface (MII) between CSMA/CD media access controllers and various PHYs. Figure151–1 shows the relationship of the RS and MII to the ISO/IEC (IEEE) OSI reference model. Note that thereare two instantiations of the MII in this clause, the 100 Gb/s Media Independent Interface (CGMII) and the40 Gb/s Media Independent Interface (XLGMII).

The purpose of the MII is to provide a simple and easy-to-implement logical interconnection between theMedia Access Control (MAC) sublayer and the Physical Layer (PHY). The MII is not intended to be electri-cally instantiated, rather it can logically connect layers within a device.

The RS adapts the bit serial protocols of the MAC to the parallel serial encodings of the PHYs. Though theMII is an optional interface, it is used in this standard as a basis for specification. The Physical Coding Sub-layer (PCS) is specified to the MII, so if not implemented, a conforming implementation shall behave func-tionally as if the RS and MII were implemented.

The MII has the following characteristics:

a) The MII is scalable and capable of supporting any speed of operation.b) Data and delimiters are synchronous to a clock reference.

Figure 151–1—RS and MII relationship to the ISO/IEC Open Systems Interconnection (OSI)reference model and the IEEE 802.3 CSMA/CD LAN model

CGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

MDIMEDIUM

HIGHER LAYERS

LOGICAL LINK CONTROL OR OTHER MAC CLIENT


MAC

XLGMII

40GBASE-R PCS

MDIMEDIUM

CGMII

100GBASE-R PCS

PMDPMA

PMDPMA

RECONCILIATION

ENCODING: R = 64B/66B ENCODED


PHYPHY


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c) It provides independent 64-bit-wide transmit and receive data paths.d) It provides for full duplex operation only.

151.1.1 Summary of major concepts

The following are the major concepts of MII:

a) The MII is functionally similar to other media independent interfaces that have been defined forlower speeds, as they all define an interface allowing independent development of MAC and PHYlogic.

b) The RS converts between the MAC serial data stream and the parallel data paths of the MII.c) The RS maps the signal set provided at the MII to the PLS service primitives provided at the MAC.d) Each direction of data transfer is independent and serviced by data, control, and clock signals.e) The RS generates continuous data or control characters on the transmit path and expects continuous

data or control characters on the receive path.f) The RS participates in link fault detection and reporting by monitoring the receive path for status

reports that indicate an unreliable link, and generating status reports on the transmit path to reportdetected link faults to the DTE on the remote end of the connecting link.

151.1.2 Application

This clause applies to the interface between the MAC and PHY. This logical interface is used to providemedia independence so that an identical media access controller may be used with all PHY types.

151.1.3 Rate of operation

The MII has been specified to support 40G b/s and 100 Gb/s.

151.1.4 Delay constraints

Predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B) demands that there bean upper bound on the propagation delays through the network. This implies that MAC, MAC Controlsublayer, and PHY implementers must conform to certain delay maxima, and that network planners andadministrators conform to constraints regarding the cable topology and concatenation of devices. The maxi-mum cumulative MAC Control, MAC and RS round-trip (sum of transmit and receive) delay shall meet thevalues specified in Table 151–1. Bit time is specified in 1.4. One pause_quantum is specified as 512 bittimes in 31B.2.

[Editor’s note (to be removed prior to publication) - The above delay constraints are based on XGMII andneed updating for 40 Gb/s and 100 Gb/s.]

Table 151–1—Round-trip delay constraints

Sublayer Maximum(bit time)

Maximum(pause_quanta)

40 Gb/s MAC, RS, and MAC Control 8192 16

100 Gb/s MAC, RS, and MAC Control 8192 16


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151.1.5 Allocation of functions

The allocation of functions at the MII balances the need for media independence with the need for a simpleinterface. This MII (like the original MII, GMII and XGMII) maximizes media independence by cleanlyseparating the Data Link and Physical Layers of the ISO (IEEE) seven-layer reference model.

151.1.6 MII structure

The MII is composed of independent transmit and receive paths. Each direction uses 64 data signals(TXD<63:0> and RXD<63:0>), eight control signals (TXC<7:0> and RXC<7:0>), and a clock (TX_CLKand RX_CLK). Figure 151–2 depicts a schematic view of the RS inputs and outputs.

The 64 TXD and eight TXC signals shall be organized into eight data lanes, as shall the 64 RXD and eightRXC signals (see Table 151–2). The eight lanes in each direction share a common clock, TX_CLK for trans-mit and RX_CLK for receive. The eight lanes are used in round-robin sequence to carry an octet stream. Ontransmit, each eight PLS_DATA.request transactions represent an octet transmitted by the MAC. The firstoctet is aligned to lane 0, the second to lane 1, the third to lane 2, the fourth to lane 3, the fifth to lane 4, thesixth to lane 5, the seventh to lane 6 and the eighth to lane 7, then repeating with the ninth to lane 0, etc.Delimiters and interframe idle characters are encoded on the TXD and RXD signals with the control codeindicated by assertion of TXC and RXC, respectively.

Table 151–2—Transmit and receive lane associations

TXD, RXD TXC, RXC Lane

<7:0> <0> 0

<15:8> <1> 1

<23:16> <2> 2

<31:24> <3> 3

<39:32> <4> 4

<47:40> <5> 5

<55:48> <6> 6

<63:56> <7> 7

TXD<63:0>TXC<7:0>

RXD<63:0>RXC<7:0>RX_CLK

PLS_DATA.request

PLS_SIGNAL.indication

PLS_DATA.indication

PLS Service Primitives MII SignalsReconciliation Sublayer

PLS_CARRIER.indication

Figure 151–2—Reconciliation Sublayer (RS) inputs and outputs

TX_CLK

PLS_DATA_VALID.indication


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151.1.7 Mapping of MII signals to PLS service primitives

The Reconciliation Sublayer (RS) shall map the signals provided at the MII to the PLS service primitivesdefined in Clause 6. The PLS service primitives provided by the RS and described here behave in exactly thesame manner as defined in Clause 6. Full duplex operation only is implemented at 40 Gb/s and 100 Gb/s;therefore, PLS service primitives supporting CSMA/CD operation are not mapped through the RS to theMII.

Mappings for the following primitives are defined for 40 Gb/s and 100 Gb/s operation:PLS_DATA.requestPLS_DATA.indicationPLS_CARRIER.indicationPLS_SIGNAL.indicationPLS_DATA_VALID.indication

151.1.7.1 Mapping of PLS_DATA.request

151.1.7.1.1 Function

The RS maps the primitive PLS_DATA.request to the MII signals TXD<63:0>, TXC<7:0>, and TX_CLK.

151.1.7.1.2 Semantics of the service primitive

PLS_DATA.request(OUTPUT_UNIT)

The OUTPUT_UNIT parameter can take one of three values: ONE, ZERO, or DATA_COMPLETE. It rep-resents a single data bit. The DATA_COMPLETE value signifies that the Media Access Control sublayerhas no more data to output.

151.1.7.1.3 When generated

This primitive is generated by the MAC sublayer to request the transmission of a single data bit on the phys-ical medium or to stop transmission.

151.1.7.1.4 Effect of receipt

The OUTPUT_UNIT values are conveyed to the PHY by the signals TXD<63:0> and TXC<7:0> on eachTX_CLK rising edge. Each PLS_DATA.request transaction shall be mapped to a TXD signal in sequence(TXD<0>, TXD<1>,... TXD<63>, TXD<0>) as described in 151.2. After 64 PLS_DATA.request transac-tions from the MAC sublayer (eight octets of eight PLS_DATA.request transactions each), the RS requeststransmission of 64 data bits by the PHY. The first octet of preamble shall be converted to a Start controlcharacter and aligned to lane 0. The TXD<63:0> and TXC<7:0> shall be generated by the RS for each 64bit-times of the MAC sublayer.

The DATA_COMPLETE value shall be mapped to a Terminate control character encoded on the next eightTXD signals in sequence after the last data octet; and is transferred to the PHY at the next TX_CLK risingedge. This may be on the same TX_CLK rising edge as the last data octet or the subsequent TX_CLK risingedge. When the Terminate control character is in lane 0, 1, 2, 3, 4, 5, or 6, the lanes following in sequenceare encoded with an Idle control character.


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151.1.7.2 Mapping of PLS_DATA.indication


The RS maps the MII signals RXD<63:0>, RXC<7:0> and RX_CLK to the primitive PLS_DATA.indica-tion.


PLS_DATA.indication (INPUT_UNIT)

The INPUT_UNIT parameter can take one of two values: ONE or ZERO. It represents a single data bit.


The INPUT_UNIT values are derived from the signals RXC<7:0> and RXD<63:0> received from the PHYon each rising edge of RX_CLK. Each primitive generated to the MAC sublayer entity corresponds to aPLS_DATA.request issued by the MAC at the remote end of the link connecting two DTEs. For eachRXD<63:0> during frame reception, the RS shall generate 64 PLS_DATA.indication transactions until theend of frame (Terminate control character), where 0, 8, 16, 24, 32, 40, 48 or 56 PLS_DATA.indicationtransactions will be generated from the RXD<63:0> containing the Terminate. During frame reception, eachRXD signal shall be mapped in sequence into a PLS_DATA.indication transaction (RXD<0>, RXD<1>,...RXD<63>, RXD<0>) as described in 151.2.

The RS shall convert a valid Start control character to a preamble octet prior to generation of the associatedPLS_DATA.indication transactions. The RS shall not generate any PLS_DATA.indication primitives for aTerminate control character. To assure robust operation, the value of the data transferred to the MAC may bechanged by the RS as required by MII error indications (see 151.3.3). Sequence ordered_sets are not indi-cated to the MAC (see 151.3.4).


The effect of receipt of this primitive by the MAC sublayer is unspecified.

151.1.7.3 Mapping of PLS_CARRIER.indication

40 Gb/s and 100 Gb/s operation supports full duplex operation only. The RS never generates this primitive.

151.1.7.4 Mapping of PLS_SIGNAL.indication

40 Gb/s and 100 Gb/s operation supports full duplex operation only. The RS never generates this primitive.

151.1.7.5 Mapping of PLS_DATA_VALID.indication


The RS maps the MII signals RXC<7:0> and RXD<63:0> to the primitive PLS_DATA_VALID.indication.


PLS_DATA_VALID.indication (DATA_VALID_STATUS)

The DATA_VALID_STATUS parameter can take one of two values: DATA_VALID orDATA_NOT_VALID. The DATA_VALID value indicates that the INPUT_UNIT parameter of the


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PLS_DATA.indication primitive contains valid data of an incoming frame. The DATA_NOT_VALID valueindicates that the INPUT_UNIT parameter of the PLS_DATA.indication primitive does not contain validdata of an incoming frame.


The PLS_DATA_VALID.indication service primitive shall be generated by the RS whenever theDATA_VALID_STATUS parameter changes from DATA_VALID to DATA_NOT_VALID or vice versa.

DATA_VALID_STATUS shall assume the value DATA_VALID when a PLS_DATA.indication transac-tion is generated in response to reception of a Start control character on lane 0 if the prior RXC<7:0> andRXD<63:0> contained eight Idle characters, a Sequence ordered set, or a Terminate character.DATA_VALID_STATUS shall assume the value DATA_NOT_VALID when RXC of the current lane insequence is asserted for anything except an Error control character. In the absence of errors,DATA_NOT_VALID is caused by a Terminate control character. When DATA_VALID_STATUS changesfrom DATA_VALID to DATA_NOT_VALID because of a control character other than Terminate, the RSshall ensure that the MAC will detect a FrameCheckError prior to indicating DATA_NOT_VALID to theMAC (see 151.3.3.1).


The effect of receipt of this primitive by the MAC sublayer is unspecified.

151.2 MII data stream

Packets transmitted through the MII shall be transferred within the MII data stream. The data stream is asequence of bytes, where each byte conveys either a data octet or control character. The parts of the datastream are shown in Figure 151–3.

<inter-frame><preamble><sfd><data><efd>

Figure 151–3—MII data stream


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For the MII, transmission and reception of each bit and mapping of data octets to lanes shall be as shown inFigure 151–4.

151.2.1 Inter-frame <inter-frame>

The inter-frame <inter-frame> period on an MII transmit or receive path is an interval during which noframe data activity occurs. The <inter-frame> corresponding to the MAC interpacket gap begins with theTerminate control character, continues with Idle control characters and ends with the Idle control characterprior to a Start control character. The length of the interpacket gap may be changed between the transmittingMAC and receiving MAC by one or more functions (e.g., RS lane alignment or PHY clock rate compensa-tion). The minimum IPG at the MII of the receiving RS is one octet.

The signaling of link status information logically occurs in the <inter-frame> period (see 151.3.4). Sub-clause 151.3.3 describes frame processing when signaling of link status information is initiated or termi-nated.

151.2.2 Preamble <preamble> and start of frame delimiter <sfd>

The preamble <preamble> begins a frame transmission by a MAC as specified in 4.2.5 and when generatedby a MAC consists of 7 octets with the following bit values:

10101010 10101010 10101010 10101010 10101010 10101010 10101010

The Start control character indicates the beginning of MAC data on the MII. On transmit, the RS convertsthe first data octet of preamble transferred from the MAC into a Start control character. On receive, the RSconverts the Start control character into a preamble data octet. The Start control character is aligned to lane 0of the MII by the RS on transmit and by the PHY on receive.

The start of frame delimiter <sfd> indicates the start of a frame and immediately follows the preamble. Thebit value of <sfd> at the MII is unchanged from the Start Frame Delimiter (SFD) specified in 4.2.6 and is thebit sequence:

10101011

MAC’s Serial Bit Stream

MAC’s Serial Bit StreamFirst Bit

Figure 151–4—Relationship of data lanes to MAC serial bit stream

...D0 D7 ...D8 D15 ...D16 D23 ...D24 D31 ...D32 D39 ...D56 D63...D40 D47 ...D48 D55

TXD<56> TXD<63>

...TXD<48> TXD<55>

...TXD<40> TXD<47>

...TXD<32> TXD<39>

...TXD<24> TXD<31>

...TXD<16> TXD<23>

...TXD<8> TXD<15>

...TXD<0> TXD<7>

...

MII Lane 0 MII Lane 1 MII Lane 2 MII Lane 3 MII Lane 4 MII Lane 5 MII Lane 6 MII Lane 7

RXD<56> RXD<63>

...RXD<48> RXD<55>

...RXD<40> RXD<47>

...RXD<32> RXD<39>

...RXD<24> RXD<31>

...RXD<16> RXD<23>

...RXD<8> RXD<15>

...RXD<0> RXD<7>

...

...D0 D7 ...D8 D15 ...D16 D23 ...D24 D31 ...D32 D39 ...D56 D63...D40 D47 ...D48 D55

First Bit


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The preamble and SFD are shown previously with their bits ordered for serial transmission from left to right.As shown, the left-most bit of each octet is the LSB of the octet and the right-most bit of each octet is theMSB of the octet.

The preamble and SFD are transmitted through the MII as octets sequentially ordered on the lanes of theMII. The first preamble octet is replaced with a Start control character and it is aligned to lane 0, the secondoctet on lane 1, the third on lane 2, the fourth on lane 3, the fifth on lane 4, the sixth on lane 5, the seventh onlane 6 and the SFD on lane 7, and the eight octets are transferred on the next rising edge of TX_CLK. Theninth octet is assigned to lane 0 with subsequent octets sequentially assigned to the lanes. The MII <pream-ble> and <sfd> are:

Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7Start 10101010 10101010 10101010 10101010 10101010 10101010 10101011

151.2.3 Data <data>

The data <data> in a well-formed frame shall consist of a set of data octets.

151.2.4 End of frame delimiter <efd>

Assertion of TXC with the appropriate Terminate control character encoding of TXD on a lane constitutesan end of frame delimiter <efd> for the transmit data stream. Similarly, assertion of RXC with the appropri-ate Terminate control character encoding of RXD constitutes an end of frame delimiter for the receive datastream. The MII shall recognize the end of frame delimiter on any of the eight lanes of the MII.

151.2.5 Definition of Start of Packet and End of Packet Delimiters

For the purposes of Clause 30, the Start of Packet delimiter is defined as the Start control character, and theEnd of Packet delimiter is defined as the end of the last sequential data octet preceding the Terminate controlcharacter or other control character causing a change from DATA_VALID to DATA_NOT_VALID. (See151.1.7.5.2 and 30.3.2.1.5.)

151.3 MII functional specifications

The MII is designed to make the differences among the various media and transceiver combinations trans-parent to the MAC sublayer. The selection of logical control signals and the functional procedures are alldesigned to this end.

NOTE—No MII loopback is defined, but MII signals are specified such that transmit signals may be connected toreceive signals to create a loopback path. To do this, TXD<0> is connected to RXD<0> ... TXD<63> to RXD<63>,TXC<0> to RXC<0> ... TXC<7> to RXC<7>, and TXCLK to RXCLK. Such a loopback does not test the Link FaultSignaling state diagram, nor any of the error handling functions of the receive RS.

151.3.1 Transmit

151.3.1.1 TX_CLK

TX_CLK is a continuous clock used for operation at the appropriate frequency. TX_CLK provides the tim-ing reference for the transfer of the TXC<7:0> and TXD<63:0> signals from the RS to the PHY. The valuesof TXC<7:0> and TXD<63:0> shall be sampled by the PHY on the rising edge of TX_CLK. TX_CLK issourced by the RS.

The TX_CLK frequency shall be one-sixty-fourth of the MAC transmit data rate.


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151.3.1.2 TXC<7:0> (transmit control)

TXC<7:0> indicate that the RS is presenting either data or control characters on the MII for transmission.The TXC signal for a lane shall be de-asserted when a data octet is being sent on the corresponding lane andasserted when a control character is being sent. In the absence of errors, the TXC signals are de-asserted bythe RS for each octet of the preamble (except the first octet that is replaced with a Start control character)and remain de-asserted while all octets to be transmitted are presented on the lanes of the MII. TXC<7:0>are driven by the RS and shall transition synchronously with respect to the rising edge of TX_CLK. Table151–3 specifies the permissible encodings of TXD and TXC for a MII transmit lane. Additional require-ments apply for proper code sequences and in which lanes particular codes are valid (e.g., Start control char-acter is to be aligned to lane 0).

151.3.1.3 TXD<63:0> (transmit data)

TXD is a bundle of 64 data signals organized into eight lanes of eight signals each (TXD<7:0>,TXD<15:8>, TXD<23:16>, TXD<31:24>, TXD<39:32>, TXD<47:40>, TXD<55:48>, and TXD<63:56>)that are driven by the RS. Each lane is associated with a TXC signal as shown in Table 151–2 and shall beencoded as shown in Table 151–3. TXD<63:0> shall transition synchronously with respect to the rising edgeof TX_CLK. For each high TX_CLK transition, data and/or control are presented on TXD<63:0> to thePHY for transmission. TXD<0> is the least significant bit of lane 0, TXD<8> the least significant bit oflane 1, TXD<16> the least significant bit of lane 2, TXD<24> the least significant bit of lane 3, TXD<32>the least significant bit of lane 4, TXD<40> the least significant bit of lane 5, TXD<48> the least significantbit of lane 6, and TXD<56> the least significant bit of lane 7.

Assertion on a lane of appropriate TXD values when TXC is asserted will cause the PHY to generate code-groups associated with either Idle, Start, Terminate, Sequence, or Error control characters. While the TXC

Table 151–3—Permissible encodings of TXC and TXD

TXC TXD Description PLS_DATA.request parameter

0 0x00 through 0xFF Normal data transmission ZERO, ONE (eight bits)

1 0x00 through 0x06 Reserved —

1 0x07 Idle No applicable parameter (normal inter-frame)

1 0x08 through 0x9B Reserved —

1 0x9C Sequence (only valid in lane 0) No applicable parameter (inter-frame status signal)

1 0x9D through 0xFA Reserved —

1 0xFB Start (only valid in lane 0) No applicable parameter, replaces first eight ZERO, ONE of a frame (preamble octet)

1 0xFC Reserved —

1 0xFD Terminate DATA_COMPLETE

1 0xFE Transmit error propagation No applicable parameter

1 0xFF Reserved —

NOTE—Values in TXD column are in hexadecimal, most significant bit to least significant bit (i.e., <7:0>).


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of a lane is de-asserted, TXD of the lane is used to request the PHY to generate code-groups correspondingto the data octet value of TXD. An example of normal frame transmission is illustrated in Figure 151–5.

Figure 151–6 shows the behavior of TXD and TXC during an example transmission of a frame propagatingan error.


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Figure 151–5—Normal frame transmission

TX_CLK

TXC<7:0>

TXD<7:0>

TXD<15:8>

TXD<23:16>

TXD<31:24>

0x010xFF 0xFF

SI I

0x00 0xFC

frame data

I: Idle control character, S: Start control character, Dp: preamble Data octet, T: Terminate control character

DpI Iframe data

DpI Iframe data

TXD<39:32>

TXD<47:40>

TXD<55:48>

TXD<63:56>

Dp0xFF T

DpI Iframe data

DpI Iframe data

DpI Iframe data

DpI Iframe data

frame data I


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151.3.1.4 Start control character alignment

On transmit, it may be necessary for the RS to modify the length of the <inter-frame> in order to align theStart control character (first octet of preamble) on lane 0. This shall be accomplished in one of the followingtwo ways:

1) A MAC implementation may incorporate this RS function into its design and always insertadditional idle characters to align the start of preamble on an eight byte boundary. Note that thiswill reduce the effective data rate for certain packet sizes separated with minimum inter-framespacing.

2) Alternatively, the RS may maintain the effective data rate by sometimes inserting and some-times deleting idle characters to align the Start control character. When using this method theRS must maintain a Deficit Idle Count (DIC) that represents the cumulative count of idle char-acters deleted or inserted. The DIC is incremented for each idle character deleted, decrementedfor each idle character inserted, and the decision of whether to insert or delete idle characters isconstrained by bounding the DIC to a minimum value of zero and maximum value of seven.Note that this may result in inter-frame spacing observed on the transmit MII that is up to sevenoctets shorter than the minimum transmitted inter-frame spacing specified in Clause 4; how-ever, the frequency of shortened inter-frame spacing is constrained by the DIC rules. The DICis only reset at initialization and is applied regardless of the size of the IPG transmitted by theMAC sublayer. An equivalent technique may be employed to control RS alignment of the Startcontrol character provided that the result is the same as if the RS implemented DIC asdescribed.

Figure 151–6—Transmit Error Propagation

I: Idle control character, S: Start control character, Dp: preamble Data octet, T: Terminate control character,

TX_CLK

TXC<7:0>

TXD<7:0>

TXD<15:8>

TXD<23:16>

TXD<31:24>

0x010xFF 0xFF

SI I

0x00 0xFC

frame data

DpI Iframe data

DpI Iframe data

TXD<39:32>

TXD<47:40>

TXD<55:48>

TXD<63:56>

Dp0xFF T

DpI Iframe data

DpI Iframe data

DpI Iframe data

DpI Iframe data

frame data

0x01 0x00

E frame data

I

E: Error control character


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151.3.2 Receive

151.3.2.1 RX_CLK (receive clock)

RX_CLK is a continuous clock that provides the timing reference for the transfer of the RXC<7:0> andRXD<63:0> signals from the PHY to the RS. RXC<7:0> and RXD<63:0> shall be sampled by the RS onthe rising edge of RX_CLK. RX_CLK is sourced by the PHY.

The frequency of RX_CLK may be derived from the received data or it may be that of a nominal clock (e.g.,TX_CLK). When the received data rate at the PHY is within tolerance, the RX_CLK frequency shall be one-sixty-fourth of the MAC receive data rate.

There is no need to transition between the recovered clock reference and a nominal clock reference on aframe-by-frame basis. If loss of received signal from the medium causes a PHY to lose the recoveredRX_CLK reference, the PHY shall source the RX_CLK from a nominal clock reference.

NOTE—This standard neither requires nor assumes a guaranteed phase relationship between the RX_CLK andTX_CLK signals.

151.3.2.2 RXC<3:0> (receive control)

RXC<7:0> indicate that the PHY is presenting either recovered and decoded data or control characters onthe MII. The RXC signal for a lane shall be de-asserted when a data octet is being received on the corre-sponding lane and asserted when a control character is being received. In the absence of errors, the RXC sig-nals are de-asserted by the PHY for each octet of the preamble (except the first octet that is replaced with aStart control character) and remain de-asserted while all octets to be received are presented on the lanes ofthe MII. RXC<7:0> are driven by the PHY and shall transition synchronously with respect to the rising edgeof RX_CLK. Table 151–4 specifies the permissible encodings of RXD and RXC for a MII receive lane.Additional requirements apply for proper code sequences and in which lanes particular codes are valid (e.g.,Start control character is to be aligned to lane 0).

Figure 151–7 shows the behavior of RXC<7:0> during an example frame reception with no errors.


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Table 151–4—Permissible lane encodings of RXD and RXC

RXC RXD Description PLS_DATA.indication parameter

0 0x00 through 0xFF Normal data reception ZERO, ONE (eight bits)

1 0x00 through 0x06 Reserved —

1 0x07 Idle No applicable parameter (Normal inter-frame)

1 0x08 through 0x9B Reserved —

1 0x9C Sequence (only valid in lane 0) No applicable parameter (Inter-frame status signal)

1 0x9D through 0xFA Reserved —

1 0xFB Start (only valid in lane 0) No applicable parameter, first eight ZERO, ONE of a frame (a preamble octet)

1 0xFC Reserved —

1 0xFD Terminate No applicable parameter (start of inter-frame)

1 0xFE Receive error No applicable parameter

1 0xFF Reserved —

NOTE—Values in RXD column are in hexadecimal, most significant bit to least significant bit (i.e., <7:0>).


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151.3.2.3 RXD (receive data)

RXD is a bundle of 64 data signals (RXD<63:0>) organized into eight lanes of eight signals each(RXD<7:0>, RXD<15:8>, RXD<23:16>, RXD<31:24>, RXD<39:32>, RXD<47:40>, RXD<55:48>, andRXD<63:56>) that are driven by the PHY. Each lane is associated with a RXC signal as shown in Table151–2 and shall be decoded by the RS as shown in Table 151–4. RXD<63:0> shall transition synchronouslywith respect to the rising edge of RX_CLK. For each rising RX_CLK transition, received data and/or controlare presented on RXD<63:0> for mapping by the RS. RXD<0> is the least significant bit of lane 0,RXD<8> the least significant bit of lane 1, RXD<16> the least significant bit of lane 2, RXD<24> the leastsignificant bit of lane 3, RXD<24> the least significant bit of lane 3, RXD<32> the least significant bit oflane 4, RXD<40> the least significant bit of lane 5, RXD<48> the least significant bit of lane 6, andRXD<56> the least significant bit of lane 7. Figure 151–7 shows the behavior of RXD<63:0> during framereception.

While the RXC of a lane is de-asserted, RXD of the lane is used by the RS to generate PLS_DATA.indica-tions. Assertion on a lane of appropriate RXD values when RXC is asserted indicates to the RS the Startcontrol character, Terminate control character, Sequence control character, or Error control character thatdrive its mapping functions.

RXC of a lane is asserted with the appropriate Error control character encoding on RXD of the lane to indi-cate an that error was detected somewhere in the frame presently being transferred from the PHY to the RS(e.g., a coding error, or any error that the PHY is capable of detecting, and that may otherwise be undetect-able at the MAC sublayer).

Figure 151–7— Frame reception without error

I: Idle control character, S: Start control character, Dp: preamble Data octet, T: Terminate control character

RX_CLK

RXC<7:0>

RXD<7:0>

RXD<15:8>

RXD<23:16>

RXD<31:24>

0x010xFF 0xFF

SI I

0x00 0xFC

frame data

DpI Iframe data

DpI Iframe data

RXD<39:32>

RXD<47:40>

RXD<55:48>

RXD<63:56>

Dp0xFF T

DpI Iframe data

DpI Iframe data

DpI Iframe data

DpI Iframe data

frame data I


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The effect of an Error control character on the RS is defined in 151.3.3.1. Figure 151–8 shows the behaviorof RXC and RXD during the reception of an example frame with an error.

151.3.3 Error and fault handling

151.3.3.1 Response to error indications by the MII

If, during frame reception (i.e., when DATA_VALID_STATUS = DATA_VALID), a control characterother than a Terminate control character is signaled on a received lane, the RS shall ensure that the MACwill detect a FrameCheckError in that frame. This requirement may be met by incorporating a function inthe RS that produces a received frame data sequence delivered to the MAC sublayer that is guaranteed to notyield a valid CRC result, as specified by the frame check sequence algorithm (see 3.2.8). This data sequencemay be produced by substituting data delivered to the MAC. The RS generates eight PLS_DATA.indicationprimitives for each Error control character received within a frame, and may generate eightPLS_DATA.indication primitives to ensure FrameCheckError when a control character other than Termi-nate causes the end of the frame.

Other techniques may be employed to respond to a received Error control character provided that the resultis that the MAC sublayer behaves as though a FrameCheckError occurred in the received frame.

Figure 151–8—Reception with error

I: Idle control character, S: Start control character, Dp: preamble Data octet, T: Terminate control character,

RX_CLK

RXC<7:0>

RXD<7:0>

RXD<15:8>

RXD<23:16>

RXD<31:24>

0x010xFF 0xFF

DpI I

0x00 0xFC

frame data

SI Iframe data

DpI Iframe data

RXD<39:32>

RXD<47:40>

RXD<55:48>

RXD<63:56>

Dp0xFF T

DpI Iframe data

DpI Iframe data

DpI Iframe data

DpI Iframe data

frame data

0x02 0x00

E frame data

I

E: Error control character


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151.3.3.2 Conditions for generation of transmit Error control characters

If, during the process of transmitting a frame, it is necessary to request that the PHY deliberately corrupt thecontents of the frame in such a manner that a receiver will detect the corruption with the highest degree ofprobability, then an Error control character may be asserted on a transmit lane by the appropriate encodingof the lane’s TXD and TXC signals.

151.3.3.3 Response to received invalid frame sequences

The PCS is required to either preserve the column alignment of the transmitting RS, or align the Start controlcharacter to lane 0. The RS shall not indicate DATA_VALID to the MAC for a Start control characterreceived on any other lane. Error free operation will not change the SFD alignment in lane 7. A MAC/RSimplementation is not required to process a packet that has an SFD in a position other than lane 7 of the col-umn containing the Start control character.

151.3.4 Link fault signaling

Link fault signaling operates between the remote RS and the local RS. Faults detected between the remoteRS and the local RS are received by the local RS as Local Fault. Only an RS originates Remote Faultsignals.

Sublayers within the PHY are capable of detecting faults that render a link unreliable for communication.Upon recognition of a fault condition a PHY sublayer indicates Local Fault status on the data path. Whenthis Local Fault status reaches an RS, the RS stops sending MAC data, and continuously generates a RemoteFault status on the transmit data path (possibly truncating a MAC frame being transmitted). When RemoteFault status is received by an RS, the RS stops sending MAC data, and continuously generates Idle controlcharacters. When the RS no longer receives fault status messages, it returns to normal operation, sendingMAC data.

[Editor’s note (to be removed prior to publication) - How Sequence ordered sets are carried across theinterface was not part of the approved baseline, the following is speculative.]

Status is signaled in an eight byte Sequence ordered_set as shown in Table 151–5. The PHY indicates LocalFault with a Sequence control character in lane 0 and data characters of 0x00 in lanes 1, 2, 4, 5, 6, and 7 plusa data character of 0x01 in lane 3. The RS indicates a Remote Fault with a Sequence control character inlane 0 and data characters of 0x00 in lanes 1, 2, 4, 5, 6, and 7 plus a data character of 0x02 in lane 3. Thoughmost fault detection is on the receive data path of a PHY, in some specific sublayers, faults can be detectedon the transmit side of the PHY. This is also indicated by the PHY with a Local Fault status.

Table 151–5—Sequence ordered_sets

Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Description

Sequence 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Reserved

Sequence 0x00 0x00 0x01 0x00 0x00 0x00 0x00 Local Fault

Sequence 0x00 0x00 0x02 0x00 0x00 0x00 0x00 Remote Fault

Sequence ≥ 0x00 ≥ 0x00 ≥ 0x03 ≥ 0x00 ≥ 0x00 ≥ 0x00 ≥ 0x00 Reserved

NOTE—Values in Lane 1-7 columns are in hexadecimal, most significant bit to least significant bit (i.e., <7:0>).The link fault signaling state diagram allows future standardization of reserved Sequence ordered sets for func-tions other than link fault indications


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The RS reports the fault status of the link. Local Fault indicates a fault detected on the receive data pathbetween the remote RS and the local RS. Remote Fault indicates a fault on the transmit path between thelocal RS and the remote RS. The RS shall implement the link fault signaling state diagram (seeFigure 151–9).

151.3.4.1 Conventions

The notation used in the state diagram follows the conventions of 21.5. The notation ++ after a counter indi-cates it is to be incremented.

151.3.4.2 Variables and counters

The Link Fault Signaling state diagram uses the following variables and counters:

col_cntA count of the number of columns received not containing a fault_sequence. This counter incre-ments at RX_CLK rate (on the rising clock transitions) unless reset.

fault_sequenceA new column received on RXC<7:0> and RXD<63:0> comprising a Sequence ordered_set ofeight bytes and consisting of a Sequence control character in lane 0 and a seq_type in lanes 1, 2, 3,4, 5, 6, and 7 indicating either Local Fault or Remote Fault.

last_seq_typeThe seq_type of the previous Sequence ordered_set receivedValues: Local Fault; 0x00 in lane 1, 0x00 in lane 2, 0x01 in lane 3, 0x00 in lane 4, 0x00 in

lane 5, 0x00 in lane 6, 0x00 in lane 7.Remote Fault; 0x00 in lane 1, 0x00 in lane 2, 0x02 in lane 3, 0x00 in lane 4, 0x00 inlane 5, 0x00 in lane 6, 0x00 in lane 7.

link_faultAn indicator of the fault status.Values: OK; No fault.

Local Fault; fault detected by the PHY.Remote Fault; fault detection signaled by the remote RS.

resetCondition that is true until such time as the power supply for the device that contains the RS hasreached the operating region.Values: FALSE: The device is completely powered and has not been reset (default).

TRUE: The device has not been completely powered or has been reset.seq_cnt

A count of the number of received Sequence ordered_sets of the same type.seq_type

The value received in the current Sequence ordered_setValues: Local Fault; 0x00 in lane 1, 0x00 in lane 2, 0x01 in lane 3, 0x00 in lane 4, 0x00 in

lane 5, 0x00 in lane 6, 0x00 in lane 7.Remote Fault; 0x00 in lane 1, 0x00 in lane 2, 0x02 in lane 3, 0x00 in lane 4, 0x00 inlane 5, 0x00 in lane 6, 0x00 in lane 7.

151.3.4.3 State Diagram

The Link Fault Signaling state diagram specifies the RS monitoring of RXC<7:0> and RXD<63:0> forSequence ordered_sets. The variable link_fault is set to indicate the value of a received Sequenceordered_set when four fault_sequences containing the same fault value have been received with each pair offault sequences separated by less than 128 columns and no intervening fault_sequences of a different faultvalue.


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The variable link_fault is set to OK following any interval of 128 columns not containing a Remote Fault orLocal Fault Sequence ordered_set.

The RS output onto TXC<7:0> and TXD<63:0> is controlled by the variable link_fault.

a) link_fault = OKThe RS shall send MAC frames as requested through the PLS service interface. In the absence ofMAC frames, the RS shall generate Idle control characters.

b) link_fault = Local FaultThe RS shall continuously generate Remote Fault Sequence ordered_sets.

c) link_fault = Remote FaultThe RS shall continuously generate Idle control characters.

151.3.5 PCS MDIO function mapping

[Editor’s note (to be removed prior to publication) - Insert MDIO/MII variable mapping

Figure 151–9—Link Fault Signaling state diagram

NEW_FAULT_TYPE

reset

INIT

seq_cnt ⇐ 0

fault_sequence

COUNT

seq_cnt++col_cnt ⇐ 0

FAULTcol_cnt ⇐ 0

seq_cnt ⇐ 0

fault_sequence ∗ seq_cnt < 3 ∗

fault_sequence ∗ seq_cnt ≥3 ∗ seq_type = last_seq_type

fault_sequence ∗ seq_type ≠ last_seq_type

fault_sequence ∗ seq_type ≠ last_seq_type

link_fault ⇐ OK

!fault_sequence ∗ col_cnt > 127

!fault_sequence ∗ col_cnt > 127

last_seq_type ⇐ seq_type

link_fault ⇐ seq_typefault_sequence ∗ seq_type = last_seq_type

seq_type = last_seq_type

UCT


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151.4 Protocol implementation conformance statement (PICS) proforma for Clause 151, Reconciliation Sublayer (RS) and Media Independent Interface (MII)5

151.4.1 Introduction

The supplier of a protocol implementation that is claimed to conform to Clause 151, Reconciliation Sublayer(RS) and Media Independent Interface (MII), shall complete the following protocol implementation con-formance statement (PICS) proforma.

A detailed description of the symbols used in the PICS proforma, along with instructions for completing thePICS proforma, can be found in Clause 21.

[Editor’s note (to be removed prior to publication) - Insert PICS, for 40 and 100Gb/s, RS and MII]



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152. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R

152.1 Overview

152.1.1 Scope

This clause specifies the Physical Coding Sublayer (PCS) that is common to two families of (40 Gb/s and100 Gb/s) Physical Layer implementations, known as 40GBASE-R and 100GBASE-R. The 40GBASE-RPCS can connect directly to one of the following Physical Layers: 40GBASE-SR4, 40GBASE-LR?,40GBASE-CR4, and 40GBASE-KR4. The 100GBASE-R PCS can connect directly to one of the followingPhysical Layers: 100GBASE-SR10, 100GBASE-LR4, 100GBASE-ER4, and 100GBASE-CR10. The terms40GBASE-R and 100GBASE-R are used when referring generally to Physical Layers using the PCS definedhere.

Both 40GBASE-R and 100GBASE-R are based on a 64B/66B code. The 64B/66B code supports data andcontrol characters, while maintaining robust error detection. Data striping is introduced to support multiplelanes in the Physical Layer. Part of the striping includes the periodic insertion of an alignment marker whichallows the receive PCS to align data from multiple lanes.

40GBASE-R and 100GBASE-R can be extended to support any full duplex medium requiring only that themedium be compliant at the PMA level.

152.1.2 Relationship of 40GBASE-R and 100GBASE-R to other standards

Figure 152–1 depicts the relationships among the 40GBASE-R and 100GBASE-R sublayers (shownshaded), the Ethernet MAC and reconciliation layers, and the higher layers.


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152.1.3 Summary of 10GBASE-R sublayer

The following subclauses provide an overview of the 40GBASE-R and 100GBASE-R sublayers. Figure152–1 depicts the relationship between the 40GBASE-R PCS and 100GBASE-R PCS and their associatedsublayers.

152.1.3.1 Physical Coding Sublayer (PCS)

The PCS service interface is the Media Independent Interface (MII), which is defined in Clause 151. The40 Gb/s instantiation of this is called the 40 Gb/s Media Independent Interface (XLGMII) and the 100 Gb/sinstantiation of this interface is called the 100 Gb/s Media Independent Interface (CGMII). The MII pro-vides a uniform interface to the Reconciliation Sublayer for all 40 Gb/s and 100 Gb/s PHY implementations.

The 40GBASE-R and 100GBASE-R PCSs provide all services required by the MII, including the following:

a) Encoding (decoding) of eight MII data octets to (from) 66-bit blocks (64B/66B).b) Transferring encoded data to (from) the PMA.c) Deleting (inserting) idles to compensate for the rate difference between the MAC and PMD due to

the insertion (deletion) of alignment markers.

Figure 152–1—40GBASE-R and 100GBASE-R PCS relationship to the ISO/IEC Open Sys-tems Interconnection (OSI) reference model and IEEE 802.3 CSMA/CD LAN model

100GBASE-R



PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

HIGHER LAYERS



MAC

MDIMEDIUM

CGMII

100GBASE-R PCS

PMD

PMA

RECONCILIATION

PHY

MDIMEDIUM

XLGMII

40GBASE-R PCS

PMD

PMA PHY

40GBASE-R


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d) Determining when a functional link has been established and informing the management entity viathe MDIO when the PHY is ready for use.

152.1.3.2 Physical Medium Attachment (PMA) sublayer

The PMA provides a medium-independent means for the PCS to support the use of a range of physicalmedia. The 40GBASE-R and 100GBASE-R PMAs perform the following functions:

a) Mapping of transmit and receive data streams between the PCS and PMA via the PMA service inter-face.

b) Recovery of clock from the received data stream.c) Mapping and multiplexing of transmit and receive bits between the PMA and PMD via the PMD

service interface.d) Optionally provides data loopback at the PMA service interface.

The PMA is specified in Clause 153.

152.1.3.3 Physical Medium Attachment (PMD) sublayer

The PMD and its media are specified in Clause 154 through Clause 158.

The MDI, logically subsumed within each PMD subclause, is the actual medium attachment for the varioussupported media.

152.1.4 Inter-sublayer interfaces

There are a two interfaces employed by 40GBASE-R and 100GBASE-R. The PMA service interface uses anabstract service model to define the operation of the interface. The PCS service interface is the MII that isdefined in Clause 151. The MII is a logical interface.

The upper interface of the PCS may connect to the Reconciliation Sublayer through the MII. The Reconcili-ation sublayer provides the same service interface to the PCS. The lower interface of the PCS connects to thePMA sublayer to support a PMD. The 40GBASE-R PCS has a nominal rate at the PMA service interface of10.3125 Mtransfers/s, which provides capacity for the MAC data rate of 40 Gb/s. The 100GBASE-R PCShas a nominal rate at the PMA service interface of 5.15625 Mtransfers/s, which provides capacity for theMAC data rate of 100 Gb/s.

It is important to note that, while this specification defines interfaces in terms of bits, octets, and frames,implementations may choose other data-path widths for implementation convenience.

152.1.5 Physical Medium Attachment (PMA) service interface

The PMA service interfaces for the PCS is described in an abstract manner and does not imply any particularimplementation. The PMA Service Interface supports the exchange of encoded data between the PCS andPMA. It is defined in 153.4.

152.1.6 Functional block diagram

Figure 152–2 provides a functional block diagram of the 40GBASE-R PHY and 100GBASE-R PHY.


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152.2 Physical Coding Sublayer (PCS)

152.2.1 PCS service interface (MII)

The PCS service interface allows the 40GBASE-R or 100GBSE-R PCS to transfer information to and froma PCS client. A PCS client is generally the Reconciliation Sublayer. The PCS Service Interface is preciselydefined as the Media Independent Interface (MII) in Clause 151.

PCS

PMA sublayer

RXD<63:0>RXC<7:0>RX_CLK

ENCODE

Figure 152–2—Functional block diagram

MII

TXD<63:0>TXC<7:0>TX_CLK

SCRAMBLE

LANE BLOCK SYNC

DESCRAMBLE

DECODE

BER

PCS TRANSMIT PCS RECEIVE

MONITOR

PMA_SIGNAL.indication

BLOCK DISTRIBUTION

ALIGNMENT INSERTION

AlIGNMENT LOCK LANE DESKEW

ALIGNMENT REMOVAL

PMA_UNITDATA.requestx (x = 0-3 for 40GBASE-R) orPMA_UNITDATA.requestx (x = 0-19 for 100GBASE-R)

PMA_UNITDATA.indicatex (x = 0-3 for 40GBASE-R) orPMA_UNITDATA.indicatex (x = 0-19 for 100GBASE-R)


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152.2.2 Functions within the PCS

The PCS comprises the PCS Transmit and PCS Receive processes for 40GBASE-R and 100GBASE-R. ThePCS shields the Reconciliation Sublayer (and MAC) from the specific nature of the underlying channel. ThePCS transmit channel and receive channel can each operate in normal mode or test-pattern mode.

When communicating with the MII, the PCS uses an eight octet-wide, synchronous data path, with packetdelimiting being provided by transmit control signals (TXCn = 1) and receive control signals (RXCn = 1).When communicating with the PMA, the PCS uses a 4-lane or 20-lane wide, data path that conveys 4 or 20streams of encoded bits6. Alignment to 64B/66B block is performed in the PCS. The PMA sublayer operatesindependent of block and packet boundaries. The PCS provides the functions necessary to map packetsbetween the MII format and the PMA service interface format.

When the transmit channel is in normal mode, the PCS Transmit process continuously generates blocksbased upon the TXD <63:0> and TXC <7:0> signals on the MII. The blocks are scrambled and then distrib-uted to individual lanes7. After distribution, alignment marker blocks are periodically added to each lane.Transmit data-units are sent to the PMA service interface via the PMA_UNITDATA.request primitive.

When the transmit channel is in test-pattern mode, a test pattern is packed into the transmit data-units thatare sent to the PMA service interface via the PMA_UNITDATA.request primitive.

When the receive channel is in normal mode, the PCS Synchronization process continuously monitorsPMA_SIGNAL.indication(SIGNAL_OK). When SIGNAL_OK indicates OK, then the PCS Synchroniza-tion process accepts data-units via the PMA_UNITDATA.indication primitive. It attains block synchroniza-tion based on the 2-bit synchronization headers on all lanes. Once block synchronization is found on alllanes, then PCS alignment marker lock can be attained by searching for valid alignment markers. Afteralignment markers are found on all lanes, the lanes can be re-ordered and deskewed. Note that a particulartransmit lane can be received on any receive lane due to the skew and multiplexing that occurs in the path.

The PCS deskew process conveys received blocks to the PCS Receive process. The PCS deskew processdeskews and aligns the individual lanes, removes the alignment markers, re-forms a single stream and setsthe align_status flag to indicate whether the PCS has obtained alignment.

When the PCS deskew process has obtained alignment, the BER monitor process monitors the signal qualityasserting hi_ber if excessive errors are detected. When align_status is asserted and hi_ber is de-asserted, thePCS Receive process continuously accepts blocks and generates RXD <63:0> and RXC <7:0> on the MII.

When the receive channel is in test-pattern mode, the BER monitor process is disabled. The Receive processwill be held in the RX_INIT state. The received bits will be compared to the test pattern and errors counted.

The PCS shall provide transmit test-pattern mode for the pseudo-random patterns, and shall provide receivetest-pattern mode for the pseudo-random patterns. Test-pattern mode is activated separately for transmit andreceive. The PCS shall support transmit test-pattern mode and receive test-pattern mode operating simulta-neously so as to support loopback testing.

152.2.3 Use of blocks

The PCS maps MII signals into 66-bit blocks, and vice versa, using a 64B/66B coding scheme. The synchro-nization headers of the blocks allow establishment of block boundaries by the PCS Synchronization process.Blocks are unobservable and have no meaning outside the PCS. The PCS functions ENCODE andDECODE generate, manipulate, and interpret blocks as provided by the rules in 152.2.4.

6These streams are from a common clock, but can vary in phase and skew dynamically.7These are called Virtual Lanes in the PMA.


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152.2.4 64B/66B transmission code

The PCS uses a transmission code to improve the transmission characteristics of information to be trans-ferred across the link and to support transmission of control and data characters. The encodings defined bythe transmission code ensure that sufficient transitions are present in the PHY bit stream to make clockrecovery possible at the receiver. The encoding also preserves the likelihood of detecting any single or mul-tiple bit errors that may occur during transmission and reception of information. In addition, the synchroni-zation headers of the code enable the receiver to achieve block alignment on the incoming PHY bit stream.The 64B/66B transmission code specified for use in this standard has a high transition density and is a run-length-limited code8.

The relationship of block bit positions to MII, PMA, and other PCS constructs is illustrated in Figure 152–3for transmit and Figure 152–4 for receive. These figures illustrate the processing of a block containing 8 dataoctets. See 152.2.4.3 for information on how blocks containing control characters are mapped. Note that thesync header is generated by the encoder and bypasses the scrambler.

152.2.4.1 Notation conventions

For values shown as binary, the leftmost bit is the first transmitted bit.

64B/66B encodes 8 data octets or control characters into a block. Blocks containing control characters alsocontain a block type field. Data octets are labeled D0 to D7. Control characters other than /O/, /S/ and /T/ arelabeled C0 to C7. The control character for ordered_set is labeled as O0 since it is only valid on the first octetof the MII. The control character for start is labeled as S0 for the same reason. The control character for ter-minate is labeled as T0 to T7.

One MII transfer provides eight characters that are encoded into one 66-bit transmission block. The sub-script in the above labels indicates the position of the character in the eight characters from the MII transfer.

Contents of block type fields, data octets and control characters are shown as hexadecimal values. The LSBof the hexadecimal value represents the first transmitted bit. For instance, the block type field 0x1e is sentfrom left to right as 01111000. The bits of a transmitted or received block are labeled TxB<65:0> andRxB<65:0> respectively where TxB<0> and RxB<0> represent the first transmitted bit. The value of thesync header is shown as a binary value. Binary values are shown with the first transmitted bit (the LSB) onthe left.

152.2.4.2 Transmission order

Block bit transmission order is illustrated in Figure 152–3 and Figure 152–4. Note that these figures showthe mapping from MII to 64B/66B block for a block containing eight data characters.

152.2.4.3 Block structure

Blocks consist of 66 bits. The first two bits of a block are the synchronization header (sync header). Blocksare either data blocks or control blocks. The sync header is 01 for data blocks and 10 for control blocks.Thus, there is always a transition between the first two bits of a block. The remainder of the block containsthe payload. The payload is scrambled and the sync header bypasses the scrambler. Therefore, the syncheader is the only position in the block that always guaranteed to contain a transition. This feature of thecode is used to obtain block synchronization.

8In 10GBASE-R the run length is limited to 66bits, but in 40GBASE-R and 100GBASE-R, when multiplexing occurs in the PMA, thisguaranteed run length limit increases. For example, if two lanes are multiplexed in the PMA, then the possible run length would double.


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Figure 152–3—PCS Transmit bit ordering
MII

TXD<0> TXD<63>

Output of encoder D0 D1 D2 D3 D4 D5 D6 D70 7

S0 S1 S2 S3 S4 S5 S6 S70 7Output of scrambler

S0 S1 S2 S3 S4 S5 S6 S70 7

Sync header

Transmit block

Scrambler

Block Distribution

PMA service interface

TxB<0> TxB<65>

function

Sync header

function

PMA_UNITDATA.request0

S0S1

S2S3

S4S5

S6S7

07

S0S1

S2S3

S4S5

S6S7

07

S0S1

S2S3

S4S5

S6S7

07

PMA_UNITDATA.request1

PMA_UNITDATA.request3 (for 40GBASE-R)PMA_UNITDATA.request19 (for 100GBASE-R)

o o o

TxB<0>

TxB<65>

TxB<66>

TxB<131>TxB<263> (for 40GBASE-R)TxB<1319 (for 100GBASE-R)


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Figure 152–4—PCS Receive bit ordering

MII

RXD<0> RXD<63>

Input to decoder D0 D1 D2 D3 D4 D5 D6 D70 7

S0 S1 S2 S3 S4 S5 S6 S70 7

Input to descrambler

S0 S1 S2 S3 S4 S5 S6 S70 7

Sync header

Receive block

Descrambler

Lane Block Sync and Deskew

PMA service interface

RxB<0> RxB<65>

function

Sync header

function

PMA_UNITDATA.indicate0

S0S1

S2S3

S4S5

S6S7

07

o o o

S0S1

S2S3

S4S5

S6S7

07

S0S1

S2S3

S4S5

S6S7

07

RxB<65>

RxB<0>

RxB<131>

RxB<66>

RxB<263> (for 40GBASE-R)RxB<1319> (for 100GBASE-R)

Note: These incoming lanes aretypically skewed relative to eachother on receive.

PMA_UNITDATA.indicate3 orPMA_UNITDATA.indicate19PMA_UNITDATA.indicate1


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Data blocks contain eight data characters. Control blocks begin with an 8-bit block type field that indicatesthe format of the remainder of the block. For control blocks containing a Start, Terminate character orordered set, that character is implied by the block type field. Other control characters are encoded in a 7-bitcontrol code. Each control block contains eight characters.

The format of the blocks is as shown in Figure 152–5. In the figure, the column labeled Input Data shows, inabbreviated form, the eight characters used to create the 66-bit block. These characters are either data char-acters or control characters and, when transferred across the MII interface, the corresponding TXC or RXCbit is set accordingly. Within the Input Data column, D0 through D7 are data octets and are transferred withthe corresponding TXC or RXC bit set to zero. All other characters are control octets and are transferredwith the corresponding TXC or RXC bit set to one. The single bit fields (thin rectangles with no label in thefigure) are sent as zero and ignored upon receipt.

Bits and field positions are shown with the least significant bit on the left. Hexadecimal numbers are shownin normal hexadecimal. For example the block type field 0x1e is sent as 01111000 representing bits 2through 9 of the 66 bit block. The least significant bit for each field is placed in the lowest numbered posi-tion of the field.

All unused values of block type field9 are reserved and shall not be transmitted and shall be considered anerror if received.

152.2.4.4 Control codes

The same set of control characters are supported by the MII and the PCS. The representations of the controlcharacters are the control codes. MII encodes a control character into an octet (an eight bit value). The40GBASE-R and 100GBASE-R PCS encode the start and terminate control characters implicitly by theblock type field. The 40GBASE-R and 100GBASE-R PCS encode the ordered_set control codes using theblock type field. The 40GBASE-R and 100GBASE-R PCS encode each of the other control characters into a7-bit C code).

The control characters and their mappings to 40GBASE-R and 100GBASE-R control codes and MII controlcodes are specified in Table 152–1. All MII, 40GBASE-R and 100GBASE-R control code values that do notappear in the table shall not be transmitted and shall be treated as an error if received.

The mapping of 40GBASE-R PCS into OPU3 specified in ITU-T Recommendation G.709 depends on theset of control block types shown in Figure 152–5. Any change to the coding specified in Figure 152–5 mustbe coordinated with ITU-T Study Group 15.

152.2.4.5 Ordered sets

Ordered sets are used to extend the ability to send control and status information over the link such as remotefault and local fault status. Ordered sets consist of a control character followed by seven data characters.Ordered sets always begin on the first octet of the MII. 40 and 100 Gigabit Ethernet use one kind ofordered_set: the sequence ordered_set (see 151.3.4). The sequence ordered_set control character is denoted

9The block type field values have been chosen to have a 4-bit Hamming distance between them. There are four unused values thatmaintain the Hamming distance: 0x00, 0x2d, 0x33 and 0x66.


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/Q/. An additional ordered_set, the signal ordered_set, has been reserved and it begins with another controlcode. The block type field encodes the control code. See Table 152–1 for the mappings.

152.2.4.6 Valid and invalid blocks

A block is invalid if any of the following conditions exists:

a) The sync field has a value of 00 or 11. b) The block type field contains a reserved value.c) Any control character contains a value not in Table 152–1.d) The set of eight MII characters does not have a corresponding block format in Figure 152–5.

152.2.4.7 Idle (/I/)

Idle control characters (/I/) are transmitted when idle control characters are received from the MII. Idle char-acters may be added or deleted by the PCS to adapt between clock rates. /I/ insertion and deletion shall occurin groups of 8. /I/s may be added following idle or ordered sets. They shall not be added while data is beingreceived.

O0 D1 D2 D3/D4 D5 D6 D7

Figure 152–5—64B/66B block formats

C0 C1 C2 C3/C4 C5 C6 C7 10 0x1e

D2 D3 D4 D5 D6 D7

Control Block Formats:Block TypeField

0xff

0xe1

0xb4

0xaa

0x99

0x87

0x78

0xcc

0xd2

10

10

10

10

10

10

10

10

10

D0 D1 D2 D3/D4 D5 D6 T7

D0 D1 D2 D3/D4 D5 T6 C7

D0 D1 D2 D3/D4 T5 C6 C7

D0 D1 D2 D3/T4 C5 C6 C7

D0 D1 D2 T3/C4 C5 C6 C7

D0 D1 T2 C3/C4 C5 C6 C7

D0 T1 C2 C3/C4 C5 C6 C7

T0 C1 C2 C3/C4 C5 C6 C7

S0 D1 D2 D3/D4 D5 D6 D7 D1

D0

D0

D0

D0

D0

D0

D0

C0

D1

D1

D1

D1

D1

D1

C1

C1

D2

C2

D2

D2

D2

D2

C2

C2

D3

D3

D3

D3

C3

C3

C3

C3

D4

D4

D4

C4

C4

C4

C4

C4

D5

D5

C5

C5

C5

C5

C5

C5

D6

C6

C6

C6

C6

C6

C6

C6

C7

C7

C7

C7

C7

C7

C7

C7

D2

D2 D30x4b10 D1

Input Data Sync

D0 D1 D2 D3/D4 D5 D6 D7 01 D0 D1 D2 D3 D4 D5 D6 D7

Data Block Format:

Block Payload

0 65Bit Position: 1 2

D4 D5 D6 D7

O0 D1 D2 D3/D4 D5 D6 D7 D2 D30x5510 D1 D4 D5 D6 D7


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152.2.4.8 Start (/S/)

The start control character (/S/) indicates the start of a packet. This delimiter is only valid on the first octet ofthe MII (TXD<0:7> and RXD<0:7>). Receipt of an /S/ on any other octet of TxD indicates an error. Blocktype field values implicitly encode an /S/ as the first character of the block.

152.2.4.9 Terminate (/T/)

The terminate control character (/T/) indicates the end of a packet. Since packets may be any length, the /T/can occur on any octet of the MII interface and within any character of the block. The location of the /T/ inthe block is implicitly encoded in the block type field. A valid end of packet occurs when a block containinga /T/ is followed by a control block that does not contain a /T/.

152.2.4.10 ordered_set (/O/)

The ordered_set control characters (/O/) indicate the start of an ordered_set. There are two kinds of orderedsets: the sequence ordered_set and the signal ordered_set (which is reserved). When it is necessary to desig-nate the control character for the sequence ordered_set specifically, /Q/ will be used. /O/ is only valid on thefirst octet of the MII. Receipt of an /O/ on any other octet of TXD indicates an error. Block type field valuesimplicitly encode an /O/ as the first character of the block. The block type encodes the specific /O/ characterfor the ordered_set.

Sequence ordered_sets may be deleted by the PCS to adapt between clock rates. Such deletion shall onlyoccur when two consecutive sequence ordered sets have been received and shall delete only one of the two.Only Idles may be inserted for clock compensation. Signal ordered_sets are not deleted for clockcompensation.

Table 152–1—Control codes

Control Character Notation MII Control Code 40GBASE-R and 100GBASE-R

Control Code

idle /I/ 0x07 0x00

start /S/ 0xfb Encoded by block type field

terminate /T/ 0xfd Encoded by block type field

error /E/ 0xfe 0x1e

Sequence ordered_set /Q/ 0x9c Encoded by block type 0x4b

Signal ordered_seta /Fsig/ 0x5c Encoded by block type 0x55

aReserved for INCITS T11 Fibre Channel use


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152.2.4.11 Error (/E/)

The /E/ is sent whenever an /E/ is received. It is also sent when invalid blocks are received. The /E/ allowsthe PCS to propagate received errors. See R_BLOCK_TYPE and T_BLOCK_TYPE function definitions in152.2.17.2.3 for further information.

152.2.5 Transmit process

The transmit process generates blocks based upon the TXD<63:0> and TXC<7:0> signals received from theMII. One MII data transfer is encoded into each block. It takes 66 PMA_UNITDATA transfers to send a 66-bit block of data on each of the lanes. Therefore, if the PCS is connected to an MII and PMA sublayer wherethe ratio of their transfer rates is exactly 16:33, then the transmit process only needs to perform rate adapta-tion to make room for the alignment markers. This will consist of deleting idles or deleting sequence orderedsets. Where the MII and PMA sublayer data rates are not synchronized to that ratio, the transmit process willneed to insert idles, delete idles, or delete sequence ordered sets to adapt between the rates in addition formaking room for alignment markers.

The transmit process generates blocks as specified in the transmit process state diagram. The contents ofeach block are contained in a vector tx_coded<65:0>, which is passed to the scrambler. tx_coded<1:0> con-tains the sync header and the remainder of the bits contain the block payload.

152.2.6 Scrambler

The payload of the block is scrambled with a self-synchronizing scrambler. The scrambler shall produce thesame result as the implementation shown in Figure 152–6. This implements the scrambler polynomial:10

(152–1)

There is no requirement on the initial value for the scrambler. The scrambler is run continuously on all pay-load bits (excluding alignment markers). The sync header bits bypass the scrambler.

152.2.7 Block distribution

Once the data is encoded and scrambled, it is distributed to multiple lanes, 66-bit blocks at a time in a roundrobin distribution. This allows the PCS to support multiple physical lanes in the PMD and XLAUI or CAUIinterfaces. The 40GBASE-R PCS distributes the 66-bit blocks to 4 lanes, and the 100GBASE-R PCS distrib-

10The convention here, which considers the most recent bit into the scrambler to be the lowest order term, is consistent with most refer-ences and with other scramblers shown in this standard. Some references consider the most recent bit into the scrambler to be the high-est order term and would therefore identify this as the inverse of the polynomial in Equation (152–1). In case of doubt, note that theconformance requirement is based on the representation of the scrambler in the figure rather than the polynomial equation.

G x( ) 1 x39 x58+ +=

Figure 152–6—Scrambler

S0 S56S39S38S2S1 S57

Serial Data Input

Scrambled Data Output


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utes the blocks to 20 lanes. The distribution process is shown in Figure 152–7. Note that what are calledlanes in the PCS are called virtual lanes in the PMA. They are virtual since multiple PCS lanes can be multi-plexed together and can be carried on a physical lane together.

152.2.8 Alignment marker insertion

In order to support alignment and de-skew of individual lanes at the receive PCS, alignment markers areadded periodically to each lane. The alignment marker has the form of a regular 66-bit block. They interruptany transfer that is already occurring so that the alignment markers can be inserted into all lanes at the sametime. Other special properties of the alignment markers are that they are not scrambled and do not conformto the encoding rules as outlined in Figure 152–5. This is possible because the alignment markers are addedafter encoding is performed in the transmit PCS and the alignment markers are removed before decoding isperformed in the receive PCS. The alignment markers are not scrambled in order to allow the receiver to

find the alignment markers and re-align all of the data before descrambling is performed. The alignmentmarkers themselves are formed from a known pattern that looks random and has lots or transitions and there-fore scrambling is not necessary for the alignment markers. The alignment markers are inserted after every16384 66-bit blocks on each lane. Alignment marker insertion is shown in Figure 152–8 and Figure 152–9.

66b Block 066b Block 166b Block 2

66b Block 0

66b Block 1

66b Block 2

66b Block n

Lane 0

Lane 1

Lane 2

Lane n

66b Block n+1

66b Block n+2

66b Block n+3

66b Block 2n

Figure 152–7—PCS Block distribution

Round RobinBlock Distribution

ooo

66b Block 0

66b Block 1

66b Block 2

66b Block n

Lane 0

Lane 1

Lane 2

Lane n

66b Block n+1

66b Block n+2

66b Block n+3

66b Block 2n

Figure 152–8—Alignment marker insertion

Marker 0

Marker 1

Marker 2

Marker n

66b Block 2n+1

66b Block 2n+2

66b Block 2n+3

66b Block 3n

66b Block 3n+1

66b Block 3n+2

66b Block 3n+3

66b Block 4n

ooo


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The format of the alignment markers are shown in Figure 152–10.

The content of the alignment markers is shown in Table 152–2. The contents depend on the lane number andthe octet number. Note that M0 = !M4, M1 = !M5, M2 = !M6, and M3 = !M7. This property allows the align-ment markers to be DC balanced. Lane markers 0-3 are used for 40GBASE-R PCS and 0-19 are used for100GBASER-R PCS. As an example, the lane marker for Lane number 0 is sent as (left most bit sent first):

101000001100010110100001000010111101111100111010010111101111010000

After the alignment makers are added, the data is sent to the PMA.

152.2.9 PMA Interface

When the transmit channel is operating in normal mode, the 40GBASE-R PCS sends four bits of transmitdata at a time via PMA_UNITDATA.request primitives and the 100GBASE-R PCS sends 20 bits of transmitdata at a time via PMA_UNITDATA.request primitives.

The UNITDATA.request primitives are parallel serial streams of bits. Since 66-bit blocks were distributed toeach lane, that means for 40GBASE-R PCS: on lane 0 bits 0 to 65 are sent, on lane 1 bits 66 to 131 are sent;on lane 2 bits 132 to 197 are sent, on lane 3 bits 198 to 263 are sent, then on lane 0 bits 264 to 329 are sentetc.

For 100GBASE-R it is: on lane 0 bits 0 to 65, on lane 1 bits 66 to 131; on lane 2 bits 132 to 197, on lane 3bits 198 to 263, on lane 4 bits 264 to 329, on lane 5 bits 330 to 395, on lane 6 bits 396 to 461, on lane 7 bits462 to 527, on lane 8 bits 528 to 593, on lane 9 bits 594 to 659, on lane 10 bits 660 to 725, on lane 11 726 to

Lane 0

Lane 1

Lane 2

Lane n

Figure 152–9—Alignment marker insertion period

ooo

16384 blocks between alignment markers

alignment marker

10 M0 M1 M2 M3 M4 M5 M6 M7

0 65Bit Position: 1 2

Figure 152–10—Alignment marker format


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791, on lane 12 bits 792 to 857, on lane 13 bits 858 to 923, on lane 14 bits 924 to 989, on lane 15 bits 990 to1055, on lane 16 bits 1056 to 1121, on lane 17 bits 1122 to 1187, on lane 18 bits 1188 to 1253, on lane 19bits 1254 to 1319, then on lane 0 bits 1320 to 1385, etc.

The transmit PCS is constrained to meet a maximum skew budget at the PMA interface. The allowable bud-get is as shown in Table 152–3

Skew is defined as the difference between the times of the earliest lane and latest lane for the one to zerotransition of the alignment marker sync bits. Dynamic skew is defined as the change in skew over the timethat the link is operational.

.

152.2.10 Test-pattern generators

[Editor’s note (to be removed prior to publication) - How test patterns operate was not part of the baselineagreement, the following is one possible way.]

Table 152–2—Alignment marker encodings

Lane Number

Encodinga {M0, M1, M2, M3, M4, M5, M6,M7}

Lane Number

Encoding {M0, M1, M2, M3, M4, M5, M6,M7}

0 0xc1, 0x68, 0x21, 0xf4, 0x3e, 0x97, 0xde, 0x0b 10 0xfd, 0x6c, 0x99, 0xde, 0x02, 0x93, 0x66, 0x2d

1 0x9d, 0x71, 0x8e, 0x17, 0x62, 0x8e, 0x71, 0xe8 11 0xb9, 0x91, 0x55, 0xb8, 0x46, 0x6e, 0xaa, 0x47

2 0x59, 0x4b, 0xe8, 0xb0, 0xa6, 0xb4, 0x17, 0x4f 12 0x5c, 0x b9, 0xb2, 0xcd, 0xa3, 0x46, 0x4d, 0x32

3 0x4d, 0x95, 0x7b, 0x10, 0xb2, 0x6a, 0x84, 0xef 13 0x1a, 0xf8, 0xbd, 0xab, 0xe5, 0x07, 0x42, 0x54

4 0xf5, 0x 07, 0x09, 0x0b, 0x0a, 0xf8, 0xf6, 0xf4 14 0x83, 0xc7, 0xca, 0xb5, 0x7c, 0x38, 0x35, 0x4a

5 0xdd, 0x14, 0xc2, 0x50, 0x22, 0xeb, 0x3d, 0xaf 15 0x35, 0x36, 0xcd, 0xeb, 0xca, 0xc9, 0x32, 0x14

6 0x9a, 0x4a, 0x26, 0x15, 0x65, 0xb5, 0xd9, 0xea 16 0xc4, 0x31, 0x4c, 0x30, 0x3b, 0xce, 0xb3, 0xcf

7 0x7b, 0x45, 0x66, 0xfa, 0x84, 0xba, 0x99, 0x05 17 0xad, 0xd6, 0xb7, 0x35, 0x52, 0x29, 0x48, 0xca

8 0xa0, 0x24, 0x76, 0xdf, 0x5f, 0xdb, 0x89, 0x20 18 0x5f, 0x66, 0x2a, 0x6f, 0xa0, 0x99, 0xd5, 0x90

9 0x68, 0xc9, 0xfb, 0x38, 0x97, 0x36, 0x04, 0xc7 19 0xc0, 0xf0, 0xe5, 0xe9, 0x3f, 0x0f, 0x1a, 0x16

aEach octet is transmitted LSB to MSB

Table 152–3—Maximum allowed output skew

PCS Maximum Skew Worst Case Dynamic Skew

40GBASE-R tbd (~400) bits tbd (~2) bits



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When the transmit channel is operating in test-pattern mode, it sends 4 bits (for 40GBASE-R) or 20 bits (for100GBASE-R) of test pattern at a time via PMA_UNITDATA.request primitives. The test-pattern generatorshall be implemented.

There is a single type of required PCS transmit test pattern: pseudo-random. The pseudo-random test-patternmode is suitable for receiver tests and for certain transmitter tests.

When pseudo-random pattern is selected, the test pattern is generated by the scrambler using a random seedloaded through the MDIO registers. The input to the scrambler is the control block type with all idles. Notethat the alignment markers are also added to the stream so that the receive PCS can align and deskew thelanes.

152.2.11 Block synchronization

When the receive channel is operating in normal mode, the block synchronization function receives data via4-bit or 20-bit PMA_UNITDATA.request primitives. It shall form 4 or 20 bit streams from the primitives byconcatenating requests with the bits of each primitive in order from each PMA_UNITDATA.indicate0 toPMA_UNITDATA.indicate3 or PMA_UNITDATA.indicate0 to PMA_UNITDATA.indicate19. It obtainslock to the 66-bit blocks in each bit stream using the sync headers and outputs 66-bit blocks. PCS lane lockis obtained as specified in the PCS lane lock state diagram shown in Figure 152–12.

152.2.12 Lane deskew

Once the receiver has PCS lane lock on each lane (4 or 20 lanes), then the process of deskewing the lanescan begin. This is accomplished by first obtaining alignment marker lock as specified in the PCS alignmentmarker lock state diagram shown in Figure 152–13 on each lane. After alignment maker lock is achieved,then any lane to lane skew can be removed as shown in the PCS deskew state diagram in Figure 152–14. ThePCS must reorder lanes if they are received out of order. PCS transmit lanes can be received on differentlanes than they were originally transmitted on due to skew and multiplexing, and so the receive PCS isrequired to handle receiving any transmit lane on any receive lane.

The skew budget that the PCS receiver must support is shown in Table 152–4. Skew is defined as the differ-ence between the times of the earliest lane and latest lane for the one to zero transition of the alignmentmarker sync bits. Dynamic skew is defined as the change in skew over the time that the link is operational.

152.2.13 Alignment marker removal

After all lanes are aligned and deskewed, then the alignment markers are removed. The alignment markersare deleted from the data stream. The difference in rate from the deleted alignment markers is made up forby inserting idles.

Table 152–4—Maximum skew tolerance requirements

PCS Maximum Skew Worst Case Dynamic Skew




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152.2.14 Descrambler

The descrambler processes the payload to reverse the effect of the scrambler using the same polynomial. Itshall produce the same result as the implementation shown in Figure 152–11.

152.2.15 Receive process

The receive process decodes blocks to produce RXD<63:0> and RXC<7:0> for transmission to the MII.One MII data transfer is decoded from each block. Where the MII and PMA sublayer data rates are not syn-chronized to a 16:33 ratio, the receive process will insert idles, delete idles, or delete sequence ordered setsto adapt between rates.

The receive process decodes blocks as specified in the receive state diagram shown in Figure 152–17.

152.2.16 Test-pattern checker

When the receive channel is operating in pseudo-random test-pattern mode, the pseudo-random test-patternchecker checks the bits received via PMA_UNITDATA.indication primitives.

The pseudo-random test-pattern checker utilizes the PCS lane lock state diagram, the alignment marker statediagram, the PCS deskew state diagram and the descrambler operating as they do during normal data recep-tion. The BER monitor state diagram is disabled during receive test-pattern mode. When align_status is trueand the pseudo-random receive test-pattern mode is active, the pseudo-random test-pattern checker observesthe output from the descrambler. When the output of the descrambler is the all idle pattern, a match isdetected. When operating in pseudo-random test pattern, the test-pattern error counter counts blocks with amismatch. Any mismatch indicates an error and shall increment the test-pattern error counter.

152.2.17 Detailed functions and state diagrams

152.2.17.1 State diagram conventions

The body of this subclause is comprised of state diagrams, including the associated definitions of variables,constants, and functions. Should there be a discrepancy between a state diagram and descriptive text, thestate diagram prevails.

The notation used in the state diagrams follows the conventions of 21.5. State diagram timers follow theconventions of 14.2.3.2. The notation ++ after a counter or integer variable indicates that its value is to beincremented.

Figure 152–11—Descrambler

S0 S56S39S38S2S1 S57

Scrambled Data Input

Serial Data Output


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152.2.17.2 State variables

152.2.17.2.1 Constants

EBLOCK_R<71:0> 72 bit vector to be sent to the MII interface containing /E/ in all the eight character locations.

EBLOCK_T<65:0>66 bit vector to be sent to the PMA containing /E/ in all the eight character locations.

LBLOCK_R<71:0>72 bit vector to be sent to the MII interface containing one Local Fault ordered_set. The LocalFault ordered_set is defined in 151.3.4.

LBLOCK_T<65:0>66 bit vector to be sent to the PMA containing one Local Fault ordered set.

152.2.17.2.2 Variables

align_statusA variable set by the PCS deskew process to reflect the status of the lane-to-lane alignment. Settrue when all lanes are synchronized and aligned, set false when the deskew process is not com-plete.

alignment_valid Boolean indication that is set true if all lanes are aligned. In order to be valid, each lane must be inam_lock, with each alignment marker matching a marker from Table 152–2. In addition each lanemust have a unique marker value and the lanes must be deskewed so that each maker from all lanesare aligned. It is false otherwise.

am_lock<x>Boolean variable that is set true when receiver acquires alignment marker delineation for a givenlane, where x=0:3 for 40GBASE-R and x=0:19 for 100GBASE-R.

am_slip_doneBoolean variable that is asserted true when the AM_SLIP requested by the PCS alignment markerlock state diagram has been completed indicating that the next candidate block position can betested.

am_statusA Boolean variable that represents the following behavior: For all n in am_lock<n>. It is set truewhen all lanes are in am_lock and false when at least one lane is not in am_lock.

am_valid Boolean indication that is set true if received block rx_coded is a valid alignment marker. A validalignment marker will match one of the encodings in Table 152–2 and it will be repeated every16385 blocks. Note that we do not know which marker to expect on which lane.

ber_test_shBoolean variable that is set true when a new sync header is available for testing and false whenBER_TEST_SH state is entered. A new sync header is available for testing when the Block Syncprocess has accumulated enough bits from the PMA to evaluate the header of the next block.

block_lock<x>Boolean variable that is set true when receiver acquires block delineation for a given lane, wherex=0:3 for 40GBASE-R and x=0:19 for 100GBASE-R.

deskew_errorA Boolean variable used by the PCS deskew process to indicate that a lane-to-lane alignment errorhas been detected. It is set true when all lanes are not aligned to the alignment marker positions,and set false when all lanes are aligned to the alignment marker positions.

enable_deskewA Boolean that indicates the enabling and disabling of the deskew process. Blocks may be dis-carded whenever deskew is enabled. True when dekew is enabled, false when deskew is disabled.


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hi_berBoolean variable which is asserted true when the ber_cnt exceeds 16 indicating a bit error ratio>10–4

resetBoolean variable that controls the resetting of the PCS. It is true whenever a reset is necessaryincluding when reset is initiated from the MDIO, during power on, and when the MDIO has put thePCS into low-power mode.

r_test_modeBoolean variable that is asserted true when the receiver is in test-pattern mode.

rx_coded<65:0>Vector containing the input to the 64B/66B decoder. The format for this vector is shown in Figure152–5. The leftmost bit in the figure is rx_coded<0> and the rightmost bit is rx_coded<65>.

rx_raw<71:0> Vector containing one MII transfers. RXC<0> through RXC<7> are from rx_raw<0> throughrx_raw<7>, respectively. RXD<0> through RXD<63> are from rx_raw<8> through rx_raw<63>,respectively.

sh_valid Boolean indication that is set true if received block rx_coded has valid sync header bits. That is,sh_valid is asserted if rx_coded<0> ≠ rx_coded<1> and de-asserted otherwise.

signal_okBoolean variable that is set based on the most recently received value of PMA_UNITDATA.indi-cation(SIGNAL_OK). It is true if the value was OK and false if the value was FAIL.

slip_doneBoolean variable that is asserted true when the SLIP requested by the Block Lock state diagramhas been completed indicating that the next candidate block sync position can be tested.

test_amBoolean variable that is set true when a new block is available for testing and false whenTEST_AM state is entered. A new block is available for testing when the Block Sync process hasaccumulated enough bits from the PMA to evaluate the next block

test_shBoolean variable that is set true when a new sync header is available for testing and false whenTEST_SH state is entered. A new sync header is available for testing when the Block Sync processhas accumulated enough bits from the PMA to evaluate the header of the next block

tx_coded<65:0>Vector containing the output from the 64B/66B encoder. The format for this vector is shown in Fig-ure 152–5. The leftmost bit in the figure is tx_coded<0> and the rightmost bit is tx_coded<65>.

tx_raw<71:0> Vector containing one MII transfer. TXC<0> through TXC<7> are placed in tx_raw<0> throughtx_raw<7>, respectively. TXD<0> through TXD<63> are placed in tx_raw<8> throughtx_raw<71>, respectively.

152.2.17.2.3 Functions

AM_SLIPCauses the next candidate block position to be tested. The precise method for determining the nextcandidate block position is not specified and is implementation dependent. However, an imple-mentation shall ensure that all possible blocks are evaluated.

DECODE(rx_coded<65:0>) Decodes the 66-bit vector returning rx_raw<71:0> which is sent to the MII. The DECODE func-tion shall decode the block as specified in 152.2.4.

ENCODE(tx_raw<71:0>) Encodes the 72-bit vector returning tx_coded<65:0> of which tx_coded<63:0> is sent to the


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scrambler. The two high order sync bits bypass the scrambler. The ENCODE function shall encodethe block as specified in 152.2.4.

R_BLOCK_TYPE = {C, S, T, D, E}This function classifies each 66-bit rx_coded vector as belonging to one of the five types depend-ing on its contents.

Values: C; The vector contains a sync header of 10 and one of the following:a) A block type field of 0x1e and eight valid control characters other than /E/;b) A block type field of 0x4b.c) A block type field of 0x55.

S; The vector contains a sync header of 10 and the following:a) A block type field of 0x78.

T; The vector contains a sync header of 10, a block type field of 0x87, 0x99, 0xaa, 0xb4,0xcc, 0xd2, 0xe1 or 0xff and all control characters are valid.

D; The vector contains a sync header of 01.E; The vector does not meet the criteria for any other value.

A valid control character is one containing a 10GBASE-R control code specified in Table 152–1.

R_TYPE(rx_coded<65:0>) Returns the R_BLOCK_TYPE of the rx_coded<65:0> bit vector.

R_TYPE_NEXTPrescient end of packet check function. It returns the R_BLOCK_TYPE of the rx_coded vectorimmediately following the current rx_coded vector.

SLIPCauses the next candidate block sync position to be tested. The precise method for determining thenext candidate block sync position is not specified and is implementation dependent. However, animplementation shall ensure that all possible bit positions are evaluated.

T_BLOCK_TYPE = {C, S, T, D, E}This function classifies each 72-bit tx_raw vector as belonging to one of the five types dependingon its contents.

Values: C; The vector contains one of the following:a) eight valid control characters other than /O/, /S/, /T/ and /E/; b) one valid ordered set.

S; The vector contains an /S/ in its first character, and all characters following the /S/ aredata characters.

T; The vector contains a /T/ in one of its characters, all characters before the /T/ are datacharacters, and all characters following the /T/ are valid control characters otherthan /O/, /S/ and /T/.

D; The vector contains eight data characters.E; The vector does not meet the criteria for any other value.

A tx_raw character is a control character if its associated TXC bit is asserted. A valid control char-acter is one containing an MII control code specified in Table 152–1. A valid ordered_set consistsof a valid /O/ character in the first character and data characters in the seven characters followingthe /O/. A valid /O/ is any character with a value for O code in Table 152–1.

T_TYPE(tx_raw<71:0>)Returns the T_BLOCK_TYPE of the tx_raw<71:0> bit vector.


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152.2.17.2.4 Counters

am_cnt Count of the number of alignment markers checked within the current 4 block window.

am_invalid_cnt Count of the number of invalid alignment markers within the current 4 block window.

ber_cnt Count up to a maximum of 16 of the number of invalid sync headers within the current 31.25 µs(40GBASE-R) or 12.5 µs (100GBASE-R) period.

sh_cntCount of the number of sync headers checked within the current 64 block window.

sh_invalid_cnt Count of the number of invalid sync headers within the current 64 block window.

152.2.17.2.5 Timers

State diagram timers follow the conventions of 14.2.3.2.

31.25us_timer (for 40GBASE-R)Timer that is triggered every 31.25 µs +1%, –25%.

12.5us_timer (for 100GBASE-R)Timer that is triggered every 12.5 µs +1%, –25%.

152.2.17.3 State diagrams

The 40GBASE-R PCS shall implement four PCS lane lock processes as depicted in Figure 152–12. The100GBASE-R PCS shall implement twenty PCS lane lock processes as depicted in Figure 152–12. A PCSlane lock process operates independently on each lane. Once PCS lane lock is achieved on all of the lanes,then the PCS alignment marker process starts.

The 40GBASE-R PCS shall implement four PCS alignment marker lock processes as depicted in Figure152–13. The 100GBASE-R PCS shall implement twenty PCS alignment marker lock processes as depictedin Figure 152–13. A PCS alignment marker lock process operates independently on each lane. The PCSalignment marker lock state diagram shown in Figure 152–13 determines when the PCS has obtained align-ment marker lock to the received data stream for a given lane.

Once alignment marker lock is achieved on all lanes, then the PCS deskew process is run as depicted in Fig-ure 152–14. The PCS deskew process is responsible for determining if the PCS is capable of presentingcoherent data to the MII.

The BER Monitor state diagram shown in Figure 152–15 monitors the received aggregate signal for high biterror ratio.

The Transmit state diagram shown in Figure 152–16 controls the encoding of transmitted blocks. It makesexactly one transition for each transmit block processed. Though the Transmit state diagram sends LocalFault ordered sets when reset is asserted, the scrambler may not be operational during reset. Thus, the LocalFault ordered sets may not appear on the PMA service interface.

The Receive state diagram shown in Figure 152–17 controls the decoding of received blocks. It makesexactly one transition for each receive block processed.

The PCS shall perform the functions of PCS lane lock, alignment marker lock, PCS deskew, BER Monitor,Transmit and Receive as specified in these state diagrams.


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[Editor’s note (to be removed prior to publication) - FEC errored block marking will likely change someof the state machines since the FEC sublayer will need to mark many blocks bad to ensure that all 64Bpackets are dropped.]

152.2.18 PCS Management

The following objects apply to PCS management. If an MDIO Interface is provided (see Clause 45), they areaccessed via that interface. If not, it is recommended that an equivalent access be provided.

152.2.18.1 Status

PCS_status: Indicates whether the PCS is in a fully operational state. It is only true if align_status is true andhi_ber is false. This status is reflected in MDIO register 3.32.12. A latch low view of this status isreflected in MDIO register 3.1.2 and a latch high of the inverse of this status, Receive fault, isreflected in MDIO register 3.8.10.

align_status:Indicates the state of the align_status variable. This status is reflected in MDIO register 3.32.0. Alatch low view of this status is reflected in MDIO register tbd.

am_lock<x>: Indicates the state of the am_lock<x> variable. There are either 4 (for 40GBASE-R) or 20(100GBASE-R) copies of this, one per lane. This status is reflected in MDIO register 3.52.0through 3.52.7 and 3.53.0 through 3.53.11. A latch low view of this status is reflected in MDIOregister tbd.

block_lock<x>: Indicates the state of the block_lock<x> variable. There are either 4 (for 40GBASE-R) or 20(100GBASE-R) copies of this, one per lane. This status is reflected in MDIO register 3.50.0through 3.50.7 and 3.51.0 through 3.51.11. A latch low view of this status is reflected in MDIOregister tbd.

hi_ber: Indicates the state of the hi_ber variable. This status is reflected in MDIO register 3.32.1. A latchhigh view of this status is reflected in MDIO register tbd.

152.2.18.2 Counters

The following counters are reset to zero upon read and upon reset of the PCS. When they reach all ones, theystop counting. Their purpose is to help monitor the quality of the link.

ber_count:6-bit counter that counts each time BER_BAD_SH state is entered. This counter is reflected inMDIO register bits 3.33.13:8. Note that this counter counts a maximum of 16 counts per 31.25(40GBASE-R) or 12.5 µs (100GBASE-R) since the BER_BAD_SH can be entered a maximum of16 times per window.

errored_block_count:8-bit counter. When the receiver is in normal mode, errored_block_count counts once for each timeRX_E state is entered. This counter is reflected in MDIO register bits 3.33.7:0.

test_pattern_error_count:16-bit counter. When the receiver is in test-pattern mode, the test_pattern_error_count countserrors as described in 152.2.16. This counter is reflected in MDIO register bits 3.43.15:0.


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152.2.18.3 Test mode control

tx_test_mode:Boolean variable controlling transmit channel operating mode. When false, the transmit channeloperates in normal mode. When true, the transmit channel operates in test-pattern mode.

rx_test_mode:Boolean variable controlling receive channel operating mode. When false, the receive channeloperates in normal mode. When true, the receive channel operates in test-pattern mode.

152.2.18.4 Loopback

The PCS shall be placed in Loopback mode when the Loopback bit in MDIO register 3.0.14 is set to a logicone. In this mode, the PCS shall accept data on the transmit path from the MII and return it on the receivepath to the MII. In addition, the PCS shall transmit a continuous stream of 1s on all lanes to the PMA sub-layer, and shall ignore all data presented to it by the PMA sublayer.


Predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B) demands that there bean upper bound on the propagation delays through the network. This implies that MAC, MAC Control sub-layer, and PHY implementors must conform to certain delay maxima, and that network planners and admin-istrators conform to constraints regarding the cable topology and concatenation of devices. The sum oftransmit and receive delay contributed by the 10GBASE-R PCS shall be no more than tbd (10GBASE-Rwas 3584) BT.

152.2.20 Auto-Negotiation

The following requirements apply to a PCS used with a 40GBASE-KR4 PMD, 40GBASE-CR4 PMD or100GBSE-CR10 PMD. Support for the Auto-Negotiation process defined in Clause 73 is mandatory. ThePCS shall support the primitive AN_LINK.indication(link_status) (see 73.9). The parameter link_statusshall take the value FAIL when PCS_status=false and the value OK when PCS_status=true. The primitiveshall be generated when the value of link_status changes.

152.2.21 PCS MDIO function mapping

[Editor’s note (to be removed prior to publication) - Add in MDIO/PCS variable mapping.]


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Figure 152–12—PCS lane lock state diagram

RESET_CNT

TEST_SH

sh_cnt⇐ 0sh_invalid_cnt ⇐ 0slip_done ⇐ false

sh_valid

test_sh

reset + !signal_ok

VALID_SH

sh_cnt ++

test_sh ∗ sh_cnt < 64

INVALID_SH

sh_cnt ++sh_invalid_cnt ++

sh_cnt = 64 ∗ sh_invalid_cnt = 0

64_GOODblock_lock<x> ⇐ true

!sh_valid

sh_cnt = 64 ∗ sh_invalid_cnt > 0

SLIPblock_lock<x> ⇐ falseSLIP

sh_cnt = 64 ∗ sh_invalid_cnt < 16 ∗ block_lock<x>

test_sh ∗ sh_cnt < 64 ∗ sh_invalid_cnt < 16 ∗ block_lock<x>

sh_invalid_cnt = 16 + !block_lock<x>

slip_done

LOCK_INIT

block_lock<x> ⇐ falsetest_sh ⇐ false

UCT

UCT

test_sh ⇐ false

Note - block_lock<x> refers to the received lane x, where x = 0:3 or 0:19


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Figure 152–13—PCS alignment marker lock state diagram

AM_RESET_CNT

TEST_AM

am_cnt⇐ 0am_invalid_cnt ⇐ 0am_slip_done ⇐ false

am_valid

test_am

reset + !block_lock<x>

VALID_AM

am_cnt ++

test_am ∗ am_cnt < 4

INVALID_AM

am_cnt ++am_invalid_cnt ++

am_cnt = 2 ∗ am_invalid_cnt = 0

2_GOODam_lock<x> ⇐ true

!am_valid

am_cnt = 4 ∗ am_invalid_cnt > 0

AM_SLIPam_lock<x> ⇐ falseAM_SLIP

am_cnt = 4 ∗ am_invalid_cnt < 4 ∗ am_lock<x>

test_am ∗ am_cnt < 4 ∗ am_invalid_cnt < 4 ∗ am_lock<x>

am_invalid_cnt = 4 + !am_lock<x>

am_slip_done

AM_LOCK_INIT

am_lock<x> ⇐ falsetest_am ⇐ false

UCT

UCT

test_am ⇐ false

Note - am_lock<x> refers to the received lane x, where x = 0:3 or 0:19


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Figure 152–14—PCS deskew state diagram

LOSS_OF_ALIGNMENTalign_status ⇐ false

reset + !am_status

enable_deskew ⇐ true

am_status * alignment_valid

!alignment_valid

deskew_error

!deskew_errorALIGN_ACQUIRED

align_status ⇐ trueenable_deskew ⇐ false


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Figure 152–15—BER monitor state diagram

BER_MT_INIT

BER_TEST_SH

hi_ber ⇐ falseber_test_sh ⇐ false

UCT

reset + r_test_mode + !align_status

sh_valid ∗ xus_timer_done

BER_BAD_SH

!sh_valid

ber_cnt ++

HI_BER

hi_ber ⇐ true

ber_test_sh ∗ ber_cnt < 16 ∗ xus_timer_not_done

ber_cnt =16

START_TIMER

ber_cnt ⇐ 0start xus_timer

ber_cnt < 16 ∗ xus_timer_done

xus_timer_done

GOOD_BER

hi_ber ⇐ false

UCT

ber_test_sh

ber_test_sh ⇐ false

xus_timer = 31.25 usec for 40GBASE-R or 12.5 usec for 100GBASE-R


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Figure 152–16—Transmit state diagram

TX_INIT

reset

T_TYPE(tx_raw) = C

tx_coded ⇐ LBLOCK_T

TX_C

tx_coded ⇐ ENCODE(tx_raw)

T_TYPE(tx_raw) = (E + D + T)T_TYPE(tx_raw) = S

D

D

TX_E

tx_coded ⇐ EBLOCK_T

T_TYPE(tx_raw) = C

T_TYPE(tx_raw) = S

T_TYPE(tx_raw) = (E + D + T)

TX_D


D

T_TYPE(tx_raw) = D

TX_T


T_TYPE(tx_raw) = T)

T_TYPE(tx_raw) = C

C

C

T_TYPE(tx_raw) = (E + C + S)

T_TYPE(tx_raw) = D

T_TYPE(tx_raw) = T T_TYPE(tx_raw) = (E + S)

T_TYPE(tx_raw) = S

D

T_TYPE(tx_raw) = C

C

T_TYPE(tx_raw) = (E + D + T)


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Figure 152–17—Receive state diagram

RX_INIT

reset+ r_test_mode + hi_ber + !align_status

R_TYPE(rx_coded) = C

rx_raw ⇐ LBLOCK_R

RX_C

rx_raw ⇐ DECODE(rx_coded)

R_TYPE(rx_coded) = (E + D + T)R_TYPE(rx_coded) = S

D

D

RX_E

rx_raw ⇐ EBLOCK_R


R_TYPE(rx_coded) = S

R_TYPE(rx_coded) = (E + D + T)

RX_D


D

R_TYPE(rx_coded) = D

RX_T


R_TYPE(rx_coded) = T∗ R_TYPE_NEXT = (S + C)


C

C

(R_TYPE(rx_coded) = T∗ R_TYPE_NEXT = (E + D + T)) + R_TYPE(rx_coded) = (E + C + S)

R_TYPE(rx_coded) = D

R_TYPE(rx_coded) = T∗ R_TYPE_NEXT = (S + C)

(R_TYPE(rx_coded) = T ∗ R_TYPE_NEXT = (E + D + T)) + R_TYPE(rx_coded) = (E + S)

R_TYPE(rx_coded)= S

D


C


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152.3 Protocol implementation conformance statement (PICS) proforma for Clause 152, Physical Coding Sublayer (PCS) type 40GBASE-R and 100GBASE-R11


The supplier of a protocol implementation that is claimed to conform to Clause 152, Physical Coding Sub-layer (PCS), type 40GBASE-R and 100GBASE-R, shall complete the following protocol implementationconformance statement (PICS) proforma. A detailed description of the symbols used in the PICS proforma,along with instructions for completing the PICS proforma, can be found in Clause 21.

[Editor’s note (to be removed prior to publication) - Insert PICS, for 40 Gb/s and 100Gb/s Physical codingsublayer]



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153. Physical Medium Attachment (PMA) sub-layer, 40/100GBASE-R

153.1 Overview

153.1.1 Scope

This clause specifies the Physical Medium Attachment sub-layer (PMA) that is common to two families of(40 Gb/s and 100 Gb/s) Physical Layer implementations, known as 40GBASE-R and 100GBASE-R. ThePMA allows the PCS (specified in Clause 152) to connect in a media independent way with a range of phys-ical media. The 40GBASE-R PMA can connect directly to one of the following Physical Layers:40GBASE-SR4, 40GBASE-LR?, 40GBASE-CR4, or 40GBASE-KR4. The 100GBASE-R PMA can con-nect directly to one of the following Physical Layers: 100GBASE-SR10, 100GBASE-LR4, 100GBASE-ER4, or 100GBASE-CR10. The terms 40GBASE-R and 100GBASE-R are used when referring generally toPhysical Layers using the PMA defined here.

40GBASE-R and 100GBASE-R can be extended to support any full duplex medium requiring only that thePMD be compliant with the appropriate PMA interface.

Electrical and timing specifications for the XLAUI and CAUI interfaces based on 10Gb/s per lane signalingare covered in Annex 153A. The PMD service interfaces for 40GBASE-SR and 100GBASE-SR PMD arecovered in 156.1.1. Other PMA interfaces are specified as logical interfaces, and may not be realized physi-cally.

153.1.2 Position of the PMA in the 40GBASE-R or 100GBASE-R sub-layers

Figure 153–1 depicts the relationships among the 40GBASE-R and 100GBASE-R sub-layers (PMA shownshaded), the Ethernet MAC and reconciliation layers, the higher layers, and the ISO/IEC Open System Inter-connection (OSI) reference model. The purpose of the PMA is to adapt the virtual lane formatted signal toan appropriate number of logical or physical lanes, to recover clock from the received signal, and optionallyto provide test signals and loopback.


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153.1.3 Summary of functions

The following is a summary of the principal functions implemented (when required) by the PMA in both thetransmit and receive directions:

a) Provide per input-lane clock and data recovery.b) Provide bit level multiplexing/gearboxing.c) Provide clock generation.d) Provide signal drivers.e) Optionally provides data loopback at the PMA service interface.f) Provide test pattern generation and detection.

In addition, the following functions are provided in the receive direction:

a) Provide receive link status information.

Figure 153–1—40GBASE-R and 100GBASE-R PMA relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model and IEEE 802.3 CSMA/CD LAN model



CGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUB-LAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

MDIMEDIUM

HIGHER LAYERS



MAC

XLGMII

40GBASE-R PCS

MDIMEDIUM

CGMII

100GBASE-R PCS

PMDPMA

PMDPMA

RECONCILIATION

PHYPHY


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153.1.4 PMA context

The PMA is modeled in stages as illustrated in Figure 153–2. Each stage of the PMA recombines the virtuallanes originating from the PCS from m PMA input lanes to n PMA output lanes.

Various stages of the PMA are optional, depending on the number of lanes required for a particular PMDand whether there is a need for an extender sub-layer (XLAUI/CAUI). A PMA with an equal number ofinput and output lanes is used to provide retiming and signal drivers, if required.

Figure 153–2—40GBASE-R and 100GBASE-R PMA layering


PMD TYPES:MEDIUM:

C = PMD FOR COPPER — 10 ME = PMD FOR FIBER— 40 KM SINGLE-MODE FIBERK = PMD FOR BACKPLANES — 1 ML = PMD FOR FIBER—10 KM SINGLE-MODE FIBERS = PMD FOR FIBER— 100 M MULTIMODE FIBER


CAUI = 100 GB/S ATTACHMENT UNIT INTERFACECGMII = 100 GB/S MEDIA INDEPENDENT INTERFACEFEC = FORWARD ERROR CORRECTIONMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUB-LAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLAUI = 40 GB/S ATTACHMENT UNIT INTERFACEXLGMII = 40 GB/S MEDIA INDEPENDENT INTERFACE

PMA LAYERING

MDI

PMA (4:1 or 2)2?

FEC1

PMD

MAC AND HIGHER LAYERS

RECONCILIATION

XLGMII

PMA (4:4)XLAUI

MDI

PMA (10:4)2

PMD

CGMII

PMA (20:10)CAUI

100GBASE-R PCS40GBASE-R PCS

Medium Medium

PMA (10:10)1PMA (4:4)1

NOTE: 1. OPTIONAL2. CONDITIONAL BASED ON PMD TYPE

FEC1


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Table 153–1 summarizes the supportable PMA stages for each interface rate.

Table 153–1—Possible PMA variants

Rate Direction Logical input lanes logical output Lanes

40GBASE-R Transmit 4 4

41 21

41 11

Receive 11 41

21 41

4 4

100GBASE-R Transmit 20 10

10 10

102 52

10 4

52 52

42 42

52 12

42 12

Receive 12 42

12 52

42 42

52 52

52 102

4 10

10 10

10 20

Notes: 1. Pending decision on whether 40GBASE-LR interface is 4, 2, or 1 lane(s)2. Not used in initial version of the standard3. Additional ratios can be obtained by combining stages, e.g., a PMA(20:5) can be constructed using a PMA(20:10) stacked on a PMA(10:5)


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153.2 PMA interfaces

All PMA variants for 40GBASE-R and 100GBASE-R signals are described in a parameterized specificationwhich applies to all input/output lane counts and each direction of transmission. A bi-directional PMA isformed from a transmit PMA with x input lanes and y output lanes, and a receive PMA with y input lanesand x output lanes as illustrated in Figure 153–3.

ReceivePMA

TransmitPMA

. . .

. . .

x input lanes

y output lanes

. . .

x output lanes

. . .y input lanes

link status

link status

Figure 153–3—Transmit and Receive Parameterized PMAs


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A parameterized PMA is illustrated in Figure 153–4. The parameters of a PMA include:

— The aggregate rate supported (40GBASE-R or 100GBASE-R).— Whether the PMA isin the Tx or Rx direction.— The numbers of input and output lanes.

153.3 PMA primitives

[Editor’s note (to be removed prior to publication) - The service interface definitions and notation in802.3ba between PMA and PMD sublayers will be reconciled as per the service interface definitions spec-ified in 1.2.2 (see 150.2.6)]

m input n output

link status

Figure 153–4—Parameterized PMA Illustration

. . .

. . .

. . .. . .

lanes. . .

. . .lanes

. . .

. . .

v/m virtual lanesper demux

v/n virtual lanesper mux

SIL

CDR

CDR

CDR

Driver

Driver

Driver

(Rx direction only)

PLL(s)input clock output clock

CDR Clock and Data RecoveryPLL Phase Locked LoopSIL Signal Indicate LogicVL Virtual Lane

VL1

VLv

VLy

VLx

All implementations that map every input VL to an output VL position are valid


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The traditional naming of PMA primitives (e.g., as in Clause 51) is not sufficient to describe PMAs that sup-port 40GBASE-R and 100GBASE-R interfaces because:

— The same model of redistributing the data from input lanes to output lanes is used in the Tx and Rxdirections. A Tx PMA with x input lanes and y output lanes is paired with an Rx PMA with y inputlanes and x output lanes.

— Several PMA stages may be required to adapt between the number of VLs emerging from the PCS tothe number of lanes required by a particular PMD. For example, a 4-lane interface for 100GBASE-Rmay involve a 20:10 PMA from the PCS, two 10:10 PMAs on either side of a CAUI for an extender,and a 10:4 PMA which finally interfaces with the PMD.

The naming of primitives is chosen to allow a single parameterized description of PMA stages to be used inthese various contexts. The following primitives are defined for a PMD with m input lanes and n outputlanes:

PMA_UNITDATA.inputx(input_bit_lane_x), x=0 through m-1

PMA_UNITDATA.outputy(output_bit_lane_y), y=0 through n-1

In addition, for an Rx PMA:

PMA_SIGNAL.input(SIGNAL_OK)

PMA_SIGNAL.output(SIGNAL_OK)

Aliases are provided for primitives at the PMA service interface (see 153.4), where z is 4 for a PMA support-ing 40GBASE-R PMDs and z is 20 for a PMA supporting 100GBASE-R PMDs:

PMA_UNITDATA.requestx(input_bit_lane_x), x=0 through z-1

PMA_UNITDATA.indicationx(output_bit_lane_x), x=0 through z-1

PMA_SIGNAL.indication(SIGNAL_OK)

Note that for the PMA_SIGNAL primitives, the parameter value may have different names depending onthe sending layer. For example, SIGNAL_DETECT is used by many of the optical PMDs to indicate thatlight has been detected on the fiber, which may or may not indicate a valid signal. SIGNAL_OK generallyimplies that the sending layer of the SIGNAL.indication primitive has performed some additional logic, e.g.,successfully recovered the clock of the input signal within the lock range, to verify the validity of thereceived signal. There may still be other errors in the signal, e.g., bad FEC or lane alignment, that are not bediscovered until higher layers, but both SIGNAL_DETECT and SIGNAL_OK should be understood tomean that the layer sending the SIGNAL.indication primitive has not discovered any errors in the receivedsignal.

153.3.1 PMA_UNITDATA.inputx

For a PMA with m input lanes, this primitive is defined for x=0 to m-1. This primitive defines the transfer ofdata (in the form of bits received on input lane x) from the adjacent layer to the PMA. In the Tx direction,data is received from the layer above (the PMA client), while in the Rx direction, data is received from thelayer below.

153.3.1.1 Semantics of the service primitive

PMA_UNITDATA.inputx (input_bit_lane_x)


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The data conveyed by the primitive is a single bit received on input lane x.

153.3.1.2 When generated

If the sending layer is a 40GBASE-R PCS or 100GBASE-R PCS, a group of 4 or 20 bits is generated, oneper input lane, at the virtual lane rate. In general, for a PMA supporting a 40GBASE-R PMD, the number ofvirtual lanes v=4 and for a PMA supporting a 100GBASE-R PMD, the number of virtual lanes v=20. APMA with m input lanes receives bits on each of its input lanes at v/m times the virtual lane rate. Skew mayexist between the bits received on each lane even though all lanes originate from the same synchronoussource, so there is independence of arrival of bits on each lane.

153.3.1.3 Effect of receipt

Clock (if necessary) and data are recovered on the lane receiving the bit. The bit makes its way through thePMA to an output lane through a process that may demultiplex virtual lanes from the input, perform anynecessary buffering to tolerate dynamic skew across input lanes, and multiplex virtual lanes to output lanes,and finally sending the bit on an output lane using the PMA_UNITDATA.outputy primitive.

153.3.2 PMA_UNITDATA.outputy

For a PMA with n output lanes, this primitive is defined for y=0 to n-1. This primitive defines the transfer ofdata (in the form of bits transmitted on an output lane) from the PMA to the adjacent layer. In the Rx direc-tion, data is transmitted to the layer above (the PMA client), while in the Tx direction, data is transmitted tothe layer below.


PMA_UNITDATA.outputy (output_bit_lane_y)

The data conveyed by the primitive is a single bit sent on one of the output lanes.


When clock (if necessary) and data have been recovered on every input lane from which a VL is routed tothis output lane, and (if necessary), buffers are filled to allow tolerating the dynamic skew that may appearbetween the input lanes, VLs are demultiplexed from the input lanes, remultiplexed to the output lanes, andbits are transferred to each output lane according to the output clock(s).


The effect of receipt is a function of the layer to which the bit is transferred.

153.3.3 PMA_SIGNAL.input

This primitive is defined in the Rx direction only. It is used by the layer below to convey link status informa-tion to the PMA.


PMA_SIGNAL.input (SIGNAL_OK)

This is used by the layer below (the PMD or another stacked PMA) to convey link status information to thePMA.


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The layer below (a PMD or another stacked PMA) reports the link status specific to the PMD or PMA layer.


When SIGNAL_OK is received from the layer below, clock and data is recovered on all of the input lanes,buffers are filled (if necessary) to accommodate dynamic skew, and bits are sent on the output lanes,PMA_SIGNAL.output (SIGNAL_OK) is sent to the layer above.

153.3.4 PMA_SIGNAL.output

This primitive is defined in the Rx direction only. It is used to convey link status information from the PMAto the layer above (the PMA client).


PMA_SIGNAL.output (SIGNAL_OK)

This is used to convey link status information to the layer above (the PCS, FEC, or a stacked PMA).


This is generated through a set of Signal Indicate Logic (SIL) that reports signal health based on receipt ofPMA_SIGNAL.input (SIGNAL_OK) from the layer below, clock and data being recovered on all of theinput lanes, buffers filled (if necessary) to accommodate dynamic skew, and bits being sent on the outputlanes. When these conditions are met, PMA_SIGNAL.output (SIGNAL_OK) is sent to the layer above.


The effect is a function of the layer to which the indication is sent.

153.4 PMA service interface

The PMA Service Interface exists between the PMA client (the PCS or FEC sub-layer) and the uppermostPMA in a set of one or more stacked PMAs (possibly including an extender sub-layer). Due to the parame-terized nature of the PMA specification, the PMA service interface is described using a set of primitiveswhich are aliases for specific cases of the more general primitives described in Clause 153.3. The number oflanes v at the PMA service interface is 4 for PMAs supporting 40GBASE-R PMDs, and 20 for PMAs sup-porting 100GBASE-R PMDs. This primitive is defined for each lane x=0 to v-1.

PMA_UNITDATA.requestx is an alias for the PMA_UNITDATA.inputx primitive of the uppermost TxPMA (adjacent to the PCS or FEC sub-layer)

PMA_UNITDATA.indicationx is an alias for the PMA_UNITDATA.outputx primitive of the uppermostRx PMA (adjacent to the PCS or FEC sub-layer)

PMA_SIGNAL.indication is an alias for the PMA_SIGNAL.output primitive of the uppermost RxPMA.


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153.5 PMD service interface

The PMD service interface exists between the lowermost PMA in a set of one or more stacked PMAs(including extender sub-layers) and the PMD. Due to the parameterized nature of the PMA specification, thePMD Service Interface primitives correspond to specific cases of the primitives described in 153.3 at theboundary of the PMA. The number of lanes z for the PMD service interface must match the number of lanesin the PMD (for example, 4 for 40GBASE-SR4 and 10 for 100GBASE-SR10). The PMD_UNITDATAprimitives are defined for each lane x=0 to z-1 of the PMD service interface. Note that electrical and timingspecifications of the PMD service interface aredefined only for 40GBASE-SR4 and 100GBASE-SR10 inter-faces. For other PMDs, the PMA service interface is specificied only logically.

PMD_UNITDATA.requestx describes the same signal as the PMA_UNITDATA.outputx primitive ofthe lowermost Tx PMA adjacent to the PMD sub-layer.

PMD_UNITDATA.indicationx describes the same signal as the PMA_UNITDATA.inputx primitive ofthe lowermost Rx PMA adjacent to the PMD sub-layer

PMD_SIGNAL.indication describes the same signal as the PMA_SIGNAL.input primitive of the lower-most Rx PMA adjancent to the PMD sub-layer.

153.6 Functions within the PMA

The purpose of the PMA is to adapt the virtual lane formatted signal to an appropriate number of logical orphysical lanes, to recover clock from the received signal, and optionally to provide test signals and loop-back. Each input or output lane of the PMA carries one or more virtual lanes which are bit-multiplexed. Allinput lanes of a given PMA carry the same number of virtual lanes and operate at the same nominal bit-rate.All output lanes of a given PMA carry the same number of virtual lanes and operate at the same nominal bit-rate. Therefore, the number of input lanes and the number of output lanes for a given PMA must be divisorsof the number of PCS virtual lanes (see Clause 152) for the interface type provided. For 40GBASE-R inter-faces, the number of virtual lanes is 4, so the possible numbers of input or output lanes is 4, 2, 1. For100GBASE-R interfaces, the number of virtual lanes is 20, so the possible numbers of input or output lanesis 20, 10, 5, 4, 2, 1.

153.6.1 Per input-lane clock and data recovery

Where required, the PMA provides per input-lane clock and data recovery (CDR). Note that CDR may notbe needed in the case of a PMA implemented together with an adjacent layer that provides signal timing,e.g., the Tx PMA adjacent to the PCS.

153.6.2 Bit level multiplexing/gearboxing

The PMA provides bit level multiplexing or gearboxing between the bits received on the input lanes via thePMA_UNITDATA.input primitive and distributes the bits to the output lanes using thePMA_UNITDATA.output primitive. The general flow is shown in Figure 153–4.

The aggregate signal carried by the group of input lanes or the group of output lanes is arranged as a set ofVirtual Lanes (VLs). For PMAs supporting 40GBASE-R interfaces, the number of virtual lanes v is 4, andthe nominal rate of each virtual lane R is 10.3125 Gb/s. For PMAs supporting 100GBASE-R interfaces, thenumber of virtual lanes v is 20, and the nominal rate of each virtual lane R is 5.15625 Gb/s.

For a PMA with m input lanes, each input lane carries, bit multiplexed, v/m virtual lanes. Each input lane hasa nominal bit-rate of R x v/m. If bit x received on an input lane belongs to a particular virtual lane, the nextbit of that same virtual lane is received on the same input lane at bit position x+v/m. If the input lane carries


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more than one VL, bit position x+1 belongs to another VL, and bit x+1+v/m is the next bit from that sameVL.

For a PMA with n output lanes, each output carries, bit multiplexed, v/n virtual lanes. Each input lane has anominal bit-rate of R x v/n. If bit x sent on an output lane belongs to a particular virtual lane, the next bit ofthat same virtual lane is sent on the same output lane at bit position x+v/n.

Each VL received in any temporal position on an input lane is transferred into a temporal position on an out-put lane. As the PCS (see Clause 152) has fully flexible receive logic, an implementation is free to performthe mapping of VLs from input lanes to output lanes without constraint. The only requirement is that fromthe time the link is brought up, each VL from an input lane is mapped to a particular output lane, and theinput lane to output lane mapping of VLs is maintained.

Any PMA which combines VLs from different input lanes onto the same output lane must tolerate dynamicskew between the input lanes without changing the VL positions on the output. The amount of dynamicskew which must be tolerated is shown in Table 153–2. Generally, buffers or FIFOs are required between theinput and output lanes to maintain the VL ordering at the output in the presence of dynamic skew across theinput lanes.

153.6.3 Clocking architecture

A PMA with m input lanes and n output lanes must clock the output lanes at m/n times the rate of the inputlanes.

The actual architecture of how this clocking is provided may vary depending on the context of the particularPMA. Typical implementations are described below:

— In a Tx PMA implemented synchronously with the PCS, the input and output clocks may simply bederived from the system reference clock.

— A PMA may utilize a clock recovered by an upstream stage in the data path as the input clock, deriv-ing the output clock with an appropriate PLL multiplier/divider circuit.

— A PMA may derive its input clock from CDR on one of the input lanes, and generate the outputclock with an appropriate PLL multiplier/divider circuit.

There is no requirement that the PMA clock all output lanes in unison. Examples of independent clocking ofoutput lanes include:

— The case where the number of input and output lanes are equal (the PMA is provided for retimingand regeneration of the signal). This may be implemented without any rearrangement of VLsbetween input lanes and output lanes (although rearrangements are allowed), and such a PMA may

Table 153–2—Dynamic Skew to be tolerated by PMA

Interface/PMA type 40GBASE-R 100GBASE-R

Tx PMA implemented synchronously with PCS 0 bits/VL 0 bits/VL

Other Tx PMA including those below extender sub-layer (XLAUI/CAUI)

2 bits/VL 1 bit/VL

Rx PMA 38 bits/VL 19 bits/VL


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be implemented by driving each output lane using the clock recovered from the corresponding inputlane.

— If the number of input and output lanes have a common factor, the PMA may be partitioned such thatVLs from a subset of the input lanes are mapped only to a subset of the output lanes (for example, a10:4 PMA could be implemented as two 5:2 PMAs). The output clock for one subset may be inde-pendent of the output clock for other subset(s).

153.6.4 Signal drivers

For the output of logical PMA interfaces, the bit-flow across the output lanes is the only required behavior.For cases where the output lanes of the PMA represent an “exposed” interface, the PMA provides electricalsignal drivers for the output lanes. The electrical and jitter/timing specifications for these interfaces appearin:

— Annex 153A specifies the XLAUI/CAUI interface— 156.1.1 specifies the PMD service interface. 156.6.1 and 156.6.5 specify the Parallel physical inter-

face (PPI), the physical instantiation of the PMD service interface.

153.6.5 Link status

An Rx PMA provides link status information to the layer above using the PMA_SIGNAL.output primitive.The PMA continuously monitors the link status reported by the layer below from the PMA_SIGNAL.inputprimitive, and uses this as input to Signal Indicate Logic (SIL) to determine the link status to report to thelayer above. Other inputs to the SIL include the status of clock and data recovery on the input lanes andwhether buffers/FIFOs have reached the required fill level to accommodate dynamic skew so that data isbeing sent on the output lanes. In a set of one or more stacked PMAs between the PCS (or FEC) and thePMD, the lowermost PMA receives its PMA_SIGNAL.input from the PMD_SIGNAL.indication primitive,and the uppermost reports its PMD_SIGNAL.output as the PMD_SIGNAL.indication primitive at the PMAservice interface.

153.6.6 PMA loopback mode (optional)

PMA loopback mode is optional. If it is implemented, it shall conform to the requirements of this Clause(153.6.6).

At the PMA service interface, the uppermost PMA in a set of one or more stacked PMAs may provide aloopback function. The function involves looping back each input lane of the uppermost Tx PMA to the cor-responding output lane of the uppermost Rx PMA.

If a Clause 45 MDIO is implemented, then this function maps to the PMA loopback function as specified in45.2.1.1.4. A device is placed in loopback mode when the loopback bit in the PMA/PMD Control register 1is set to a logic one. A device is removed from loopback mode when this bit is set to a logic zero.

Figure 153–5 illustrates the data flow for PMA loopback mode. In loopback mode, the Tx PMA continues toperform the normal bit muxing/gearboxing operations from its input lanes to its output lanes as described in153.6.2, but in addition, conveys the bits from its input lanes to the corresponding Rx PMA. The Rx PMAsends these bits to its output lanes, ignoring what is received from the input lanes of the Rx PMA. The RxPMA indicates a link status of SIGNAL_OK without respect to the link status it receives from the layerbelow or whether clock and data are recovered on its input lanes.


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[Editor’s Note (to be removed prior to publication): There is no adopted baseline for test patterns - the fol-lowing is a placeholder based on gustlin_03_0708.pdf]

153.6.7 PMA test patterns

Where the output lanes of the PMA appear on an exposed interface (e.g., XLAUI/CAUI or the PMD serviceinterface), the PMA may generate and detect test patterns. These test patterns are used to test adjacent layerinterfaces or to perform testing between an interface and external testing equipment. These test patterns arenot intended to traverse more than one layer or to be carried over an end-to-end Ethernet link. The test pat-terns cannot be recovered if they are rearranged through the bit multiplexing/gearboxing operationsdescribed in 153.6.2.

If a Clause 45 MDIO is supported, then these functions map to the PMA test pattern functions as specified in45.2.3.15.1, 45.2.3.15.2, 45.2.3.15.3, and 45.2.3.15.4.

When transmit PRBS31 test pattern (see 49.2.8) is enabled (TBD - should a shorter pattern, e.g., PRBS9 (see68.6.1) be included also?), the PMA generates a PRBS31 pattern on each of its output lanes. If the PMA is inthe Rx direction, it also generates PMA_SIGNAL.output(SIGNAL_OK) independent of the link status orclock and data recovery on its input lanes, which are ignored in this state. When transmit PRBS31 test pat-tern is disabled, the PMA returns to normal operation performing bit multiplexing/gearboxing as describedin 153.6.2.

When a receive PRBS31 test pattern mode is enabled, the PMA expects to find the PRBS31 pattern on eachof its input lanes. The test pattern error counter register specified in 45.2.3.16 counts, in aggregate across allof the input lanes (TBD - should counters be provided per lane, up to 20 lanes?), errors in detecting thePRBS31 pattern on the input lanes. While in receive PRBS test pattern mode, the output lanes are disabled,and if the PMA is in the Rx direction, the PMA_SIGNAL.output primitive does not indicate a valid signalsince the test pattern cannot, in general, transit the PMA and still be recognized. When receive PRBS31 testpattern is disabled, the PMA returns to normal operation performing bit multiplexing/gearboxing asdescribed in 153.6.2.

Editor’s note to be removed on publication: 10G interfaces only support transmit square wave test pat-tern, not receive square wave test pattern. If we follow this precedent, the 2nd paragraph is removed andthe sentence about what the transmit square wave test pattern does in the Rx direction is removed since itis irrelevant.

Figure 153–5—PMA Loopback Mode

TxPMA

x input lanes

y output lanes

RxPMA

x output lanes

. . .

y input lanes

X X X

. . .

. . .. . .

PMA_SIGNAL.input

PMA_SIGNAL.indicate(SIGNAL_OK)

Xinputs ignored

in loopbackmode

derived normally from inputduring loopback


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When transmit square wave test pattern mode is enabled, the PMA generates a square wave test pattern oneach of its output lanes (TBD ones followed by TBD zeros, provisionally 8). If the PMA is in the Rx direc-tion, it also generates PMA_SIGNAL.output (SIGNAL_OK) independent of the link status or clock anddata recovery on its input lanes, which are ignored in this state. When transmit test pattern is disabled, thePMA returns to normal operation performing bit multiplexing/gearboxing as described in 153.6.2.

When a receive square wave test pattern mode is enabled, the PMA expects to find a square wave pattern(TBD ones followed by TBD zeros, provisionally 8) on each of its input lanes. The test pattern error counterregister specified in 45.2.3.16 counts, in aggregate across all of the input lanes (TBD - should counters beprovided per lane, up to 20 lanes?), errors in detecting the square wave pattern on the input lanes. While inreceive test pattern mode, the output lanes are disabled, and if the PMA is in the Rx direction, thePMA_SIGNAL.output primitive does not indicate a valid signal since the test pattern cannot, in general,transit the PMA and still be recognized. When receive test pattern is disabled, the PMA returns to normaloperation performing bit bultiplexing/gearboxing as described in 153.6.2.

153.7 PMA MDIO function mapping

The optional MDIO capability described in Clause 45 describes several variables that may provide controland status information for and about the PMA. Mapping of MDIO control variables to PMA control vari-ables is shown in Table 153–3. Mapping of MDIO status variables to PMA status variables is shown inTable 153–4.

Table 153–3—MDIO/PMA control variable mapping

MDIO control variable PMA register name Register/bit number PMA control variable

PMA Loopback 1.0.0

PRBS9 transmit test-pat-tern enable TBD

3.42.6

PRBS31 receive test-pat-tern enable

3.42.5

PRBS31 transmit test-pat-tern enable

3.42.4

Transmit test-pattern enable

3.42.3

Receive test-pattern enable TBD - receive square wave may be NA

3.42.2

Test-pattern select TBD - Square wave only valid value

3.42.1


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Table 153–4—MDIO/PMA status variable mapping

MDIO status variable PMA register name Register/bit number PMA status variable

Test-pattern error counter 3.43.15:0


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153.8 Protocol implementation conformance statement (PICS) proforma for Clause 153, Physical Medium Attachment (PMA) sub-layer, 40/100GBASE-R


The supplier of a protocol implementation that is claimed to conform to Clause 153, PMA Interface sub-layer, 40/100GBASE-R, shall complete the following protocol implementation conformance statement(PICS) proforma.

A detailed description of the symbols used in the PICS proforma, along with instructions for completing thesame, can be found in Clause 21.

153.8.2 Identification

153.8.2.1 Implementation identification

153.8.2.2 Protocol summary

TBD

Supplier1

Contact point for enquiries about the PICS1

Implementation Name(s) and Version(s)1,3

Other information necessary for full identification—e.g., name(s) and version(s) for machines and/or operating systems; System Name(s)2

NOTES

1—Required for all implementations.

2—May be completed as appropriate in meeting the requirements for the identification.

3—The terms Name and Version should be interpreted appropriately to correspond with a supplier’s terminology(e.g., Type, Series, Model).

Date of Statement


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154. Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-KR4

154.1 Overview

This clause specifies the 40GBASE-KR4 PMD. In order to form a complete PHY, the PMD shall be con-nected to the appropriate sublayers (see Table 154–1) and with the management functions that are optionallyaccessible through the management interface defined in Clause 45, or equivalent.

Table 154–1—PHY (Physical Layer) clauses associated with the 40GBASE-KR PMD

Associated clause 10GBASE-KR

151—RS Required

151—XLGMIIa

aThe XLGMII is an optional interface. However, if the XLGMII is notimplemented, a conforming implementation must behave functionally asthough the RS and XLGMII were present.

Optional

153A—XLAUI Optional

152—PCS for 40GBASE-R Required

153—PMA for 40GBASE-R Required

73—Auto-Negotiation for Backplane Ethernet Required

74—FEC for BASE-R Optional


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Figure 154–1 shows the relationship of the 40GBASE-KR4 PMD and MDI (shown shaded) with other sub-layers to the ISO/IEC Open System Interconnection (OSI) reference model.

154.2 Physical Medium Dependent (PMD) service interface

[Editor’s note (to be removed prior to publication) - The service interface definitions and notation in802.3ba between PMA and PMD sublayers will be reconciled as per the service interface definitions spec-ified in 1.2.2 (see 150.2.6)]

This subclause specifies the services provided by the 40GBASE-KR4 PMD. The service interface for thisPMD is described in an abstract manner and does not imply any particular implementation. The PMD Ser-vice Interface supports the exchange of encoded data. The PMD translates the encoded data to and from sig-nals suitable for the medium.

The following PMD service primitives are defined:

a) PMD_UNITDATA.requestb) PMD_UNITDATA.indicationc) PMD_SIGNAL.indication

Figure 154–1—40GBASE-KR4 PMD relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model and the IEEE 802.3 CSMA/CD LAN model

LANCSMA/CD

LAYERS



RECONCILIATION

HIGHER LAYERS


PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSI REFERENCE

MODELLAYERS

MDI

MEDIUM

PMA

XLGMII

FEC

40GBASE-R PCS

40GBASE-KR4

PHY

PMD

AN

AN = AUTO-NEGOTIATION SUBLAYERFEC = FORWARD ERROR CORRECTION SUBLAYERMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE

PMD TYPES:MEDIUM:

K = PMD FOR BACKPLANES — 1m



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154.2.1 PMD_UNITDATA.request

This primitive defines the transfer of encoded data from the PMA to the PMD.


PMD_UNITDATA.request (tx_bit <0:3>)

The data conveyed by PMD_UNITDATA.request is a continuous sequence of four parallel code-groupstreams, one stream for each lane. The tx_bit <0:3> correspond to the bits in the tx_lane<0:3> bit streams.Each bit in the tx_bit parameter can take one of two values: ONE or ZERO.


The PMA continuously sends four parallel code-group streams to the PMD at a nominal signaling speed of10.3125 GBaud.

154.2.1.3 Effect of Receipt

Upon receipt of this primitive, the PMD converts the specified stream of bits into the appropriate signals onthe MDI.

154.2.1.4 PMD_UNITDATA.indication

This primitive defines the transfer of encoded data from the PMD to the PMA.

154.2.2 Semantics of the service primitive

PMD_UNITDATA.indication (rx_bit <0:3>)

The data conveyed by PMD_UNITDATA.indication is a continuous sequence of four parallel encoded bitstreams. The rx_bit<0:3> correspond to the bits in the rx_lane<0:3> bit streams. Each bit in the rx_bitparameter can take one of two values: ONE or ZERO.


The PMD continuously sends streams of bits to the PMA corresponding to the signals received from theMDI.


This primitive is received by the client (the PMA) as PMA_UNITDATA.inputi(input_bit_lane_i). Theeffect of receipt is described in 153.3.1.3.

154.2.3 PMD_SIGNAL.indication

This primitive is generated by the PMD to indicate the status of the signals being received from the MDI.


PMD_SIGNAL.indication (SIGNAL_DETECT)

SIGNAL_DETECT in 40GBASE-KR4 indicates the successful completion of the start-up protocol on allfour lanes.


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The SIGNAL_DETECT parameter can take on one of two values: OK or FAIL. When SIGNAL_DETECT=FAIL, rx_bit is undefined, but consequent actions based on PMD_UNITDATA.indication, where neces-sary, interpret rx_bit as a logic ZERO.


The PMD generates this primitive to indicate a change in the value of SIGNAL_DETECT.


The effect of receipt of this primitive by the client (the PMA) is described in 153.3.3.3.

154.3 PCS requirements for Auto-Negotiation (AN) service interface

The PCS associated with this PMD shall support the AN service interface primitive AN_LINK.indicationdefined in 73.9. (See 49.2.16 and 152.2.20.)


Predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B) demands that there bean upper bound on the propagation delays through the network. This implies that MAC, MAC Control sub-layer, and PHY implementors must consider the delay maxima, and that network planners and administra-tors consider the delay constraints regarding concatenation of devices. A description of overall system delayconstraints and the definitions for bit-times and pause_quanta can be found in 69.3 and 150.3

The sum of the transmit and the receive delays contributed by the 40GBASE-KR4 PMD and medium shallbe no more than 1024 bit times. It is assumed that the round-trip delay through the medium is 160 bit times.

154.5 Skew constraints

[Editor’s note (to be removed prior to publication) - this description of skew constraints is a place holderand needs review. The numbers will be reconciled to meet the requirements of 152.2.12]

The maximum skew between lanes is described in Table 48-5.

154.6 PMD MDIO function mapping

The optional MDIO capability described in Clause 45 defines several variables that provide control and sta-tus information for and about the PMD. If MDIO is implemented, it shall map MDIO control variables toPMD control variables as shown in Table 154–1, and MDIO status variables to PMD status variables asshown in Table 154–2.

154.7 PMD functional specifications

154.7.1 Link block diagram

The 40GBASE-KR4 PMD uses the same Link block diagram as10GBASE-KX4, as defined in 71.6.1


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Table 154–1—MDIO/PMD control variable mapping

MDIO control variable PMA/PMD register name Register/ bit number PMD control variable

Reset Control register 1 1.0.15 PMD_reset

Global PMD Transmit Disable Transmit disable register 1.9.0 Global_PMD_transmit_disable

Transmit disable 3 Transmit disable register 1.9.4 PMD_transmit_disable_3




Restart training Backplane PMD control register 1.150.0 mr_restart_training

Training enable Backplane PMD control register 1.150.1 mr_training_enable

Table 154–2—MDIO/PMD status variable mapping

MDIO status variable PMA/PMD register name Register/ bit number PMD status variable

Fault Status register 1 1.1.7 PMD_fault

Transmit fault Status register 2 1.8.11 PMD_transmit_fault

Receive fault Status register 2 1.8.10 PMD_receive_fault

Global PMD Receive signal detect Receive signal detect register 1.10.0 Global_PMD_signal_detect

PMD signal detect 3 Receive signal detect register 1.10.4 PMD_signal_detect_3




Receiver status 3 Backplane PMD status register 1.151.12 rx_trained_3

Frame lock 3 Backplane PMD status register 1.151.13 frame_lock_3

Start-up protocol status 3 Backplane PMD status register 1.151.14 training_3

Training failure 3 Backplane PMD status register 1.151.15 training_failure_3




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154.7.2 PMD transmit function

The PMD Transmit function shall convert the four logical streams requested by the PMD service interfacemessage PMD_UNITDATA.request (tx_bit<0:3>) into four separate electrical streams. A positive outputvoltage of SL minus SL<n> (differential voltage) corresponds to tx_bit = ONE.

154.7.3 PMD receive function

The PMD Receive function shall convert the four electrical streams from the MDI into four logical streamsfor delivery to the PMD service interface using the message PMD_UNITDATA.indication (rx_bit<0:3>). Apositive input voltage of DL minus DL<n> (differential voltage) shall correspond to rx_bit = ONE.

154.7.4 Global PMD signal detect function

The Global PMD signal detect function shall continuously report the message PMD_SIGNAL.indication(SIGNAL_DETECT) to the PMD service interface. SIGNAL_DETECT, while normally intended to be anindicator of signal presence, is used by 40GBASE-KR4 to indicate the successful completion of the start-upprotocol on all lanes.

SIGNAL_DETECT shall be set to FAIL following system reset or the manual reset of the training state dia-gram. Upon completion of training, SIGNAL_DETECT shall be set to OK.

If training is disabled by management, SIGNAL_DETECT shall be set to OK.

If the MDIO interface is implemented, then Global_PMD_signal_detect (1.10.0) shall be continuously set tothe value of SIGNAL_DETECT as described in 45.2.1.9.5; and PMD_signal_detect_0 (1.10.1),PMD_signal_detect_1 (1.10.2), PMD_signal_detect_2 (1.10.3) and PMD_signal_detect_3 (1.10.4) shall beset to 1 or 0 depending on whether a particular lane’s signal_detect, as defined by the training state diagramin Figure 72-5, returns true or false.














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154.7.5 PMD transmit disable function

The Global_PMD_transmit_disable function is optional. When this function is supported, it shall meet therequirements of this subclause.

a) When the Global_PMD_transmit_disable variable is set to ONE, this function shall turn off thetransmitter such that it drives a constant level (i.e., no transitions) and does not exceed the maximumdifferential peak-to-peak output voltage specified in Table 72-6.

b) If a PMD_fault (154.7.7) is detected, then the PMD may turn off the electrical transmitter.c) Loopback, as defined in 154.7.6, shall not be affected by Global_PMD_transmit_disable.

If the MDIO interface is implemented, then this function shall map to the Global_PMD_transmit_disable bitas specified in 45.2.1.8.5.

154.7.6 Loopback mode

Loopback mode shall be provided for the 40GBASE-KR4 PMD by the transmitter and receiver of a deviceas a test function to the device. When loopback mode is selected, transmission requests passed to the trans-mitter are shunted directly to the receiver, overriding any signal detected by the receiver on its attached link.Note, this bit does not affect the state of the transmitter. The method of implementing loopback mode is notdefined by this standard.

Control of the loopback function is specified in 45.2.1.1.4.

NOTE 1—The signal path that is exercised in the loopback mode is implementation specific, but it is recommended thatthis signal path encompass as much of the circuitry as is practical. The intention of providing this loopback mode ofoperation is to permit diagnostic or self-test functions to test the transmit and receive data paths using actual data. Otherloopback signal paths may also be enabled independently using loopback controls within other devices or sublayers.

NOTE 2—Placing a network port into loopback mode can be disruptive to a network.

154.7.7 PMD_fault function

If the MDIO is implemented, PMD_fault is the logical OR of PMD_receive_fault, PMD_transmit_fault, andany other implementation specific fault.

154.7.8 PMD transmit fault function

The PMD_transmit_fault function is optional. The faults detected by this function are implementation spe-cific, but should not include the assertion of the Global_PMD_transmit_disable function.

If a PMD_transmit_fault (optional) is detected, then the Global_PMD_transmit_disable function should alsobe asserted.

If the MDIO interface is implemented, then this function shall be mapped to the PMD_transmit_fault bit asspecified in 45.2.1.7.4.

154.7.9 PMD receive fault function

The PMD_receive_fault function is optional. The faults detected by this function are implementation spe-cific.

If the MDIO interface is implemented, then this function shall contribute to PMA/PMD receive fault bit asspecified in 45.2.1.7.5.


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154.7.10 PMD control function

Each lane of the 40GBASE-KR4 PMD uses the same control function as10GBASE-KR, as defined in72.6.10.

The random seed for the training pattern described in 72.6.10.2.6 shall be different for each of the lanes.

154.8 10GBASE-KR electrical characteristics

154.8.1 Transmitter characteristics

Transmitter electrical characteristics at TP1 for 40GBASE-KR4 are the same as 10GBASE-KR, as detailedin 72.7.1.1 through 72.7.1.11.

154.8.1.1 Test fixture

The same test fixture as 10GBASE-KR is used on all lanes as described in 72.7.1.1

154.8.2 Receiver characteristics

Receiver electrical characteristics at TP4 for 40GBASE-KR4 are the same as 10GBASE-KR, as detailed in72.7.1.1 through 72.7.2.5.


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154.8.2.1 Receiver interference tolerance

The receiver interference tolerance tests are the same as those described for 10GBASE-KR in 72.7.2.1 andAnnex 69A.

154.9 Interconnect characteristics

Informative interconnect characteristics for 40GBASE-KR4 are provided in Annex 69B.

154.10 Environmental specifications

154.10.1 General safety

All equipment that meets the requirements of this standard shall conform to applicable sections (includingisolation requirements) of IEC 60950-1.

154.10.2 Network safety

The designer is urged to consult the relevant local, national, and international safety regulations to ensurecompliance with the appropriate requirements.

154.10.3 Installation and maintenance guidelines

It is recommended that sound installation practice, as defined by applicable local codes and regulations, befollowed in every instance in which such practice is applicable.

154.10.4 Electromagnetic compatibility

A system integrating the 40GBASE-KR4 PHY shall comply with applicable local and national codes for thelimitation of electromagnetic interference.

154.10.5 Temperature and humidity

A system integrating the 40GBASE-KR4 PHY is expected to operate over a reasonable range ofenvironmental conditions related to temperature, humidity, and physical handling (such as shock andvibration). Specific requirements and values for these parameters are considered to be beyond the scope ofthis standard.


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154.11 Protocol implementation conformance statement (PICS) proforma for Clause 154, Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-KR412

[Editor’s note (to be removed prior to publication) - Insert PICS, for 40GBASE-KR4]


The supplier of a protocol implementation that is claimed to conform to Clause 154, Physical MediumDependent Sublayer and Baseband Medium, Type 40GBASE-KR4, shall complete the following protocolimplementation conformance statement (PICS) proforma.






Supplier1




NOTES




Identification of protocol standard IEEE Std 802.3ba-20xx, Clause 154, Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-KR4

Identification of amendments and corrigenda to this PICS proforma that have been completed as part of this PICS

Have any Exception items been required? No [ ] Yes [ ](See Clause 21; the answer Yes means that the implementation does not conform to IEEE Std 802.3ba-20xx.)

Date of Statement


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155. Physical Medium Dependent Sublayer and Baseband Medium, Type 40GBASE-CR4 and 100GBASE-CR10

155.1 Overview

This clause specifies the 40GBASE-CR4 and 100GBASE-CR10 PMDs (including MDI) and the basebandmedium. In order to form a complete PHY (Physical Layer device), a PMD is combined with the appropriatesublayers (see Table 155–1) and with the management functions, which are optionally accessible throughthe management interface defined in Clause 45, or equivalent.

Table 155–1—PHY (Physical Layer) clauses associated with the 40GBASE-CR4 and 100GBASE-CR10 PMD

Associated clause 40GBASE-CR4 100GBASE-CR10

151-RS Required Required

151—XLGMIIa

aThe XLGMII is an optional interface. However, if the XLGMII is not implemented, a conforming implementa-tion must behave functionally as though the RS and XLGMII were present.

Optional Not applicable

151—CGMIIb

bThe CGMII is an optional interface. However, if the XLGMII is not implemented, a conforming implementa-tion must behave functionally as though the RS and XLGMII were present.

Not applicable Optional

153A—XLAUI Optional Optional

152—PCS for 40/100GBASE-R Required Required

153—PMA for 40/100GBASE-R Required Required

73- Auto-Negotiation Required Required

74—FEC Optional Optional


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Figure 155–1 shows the relationship of the 40GBASE-CR4 and 100GBASE-CR10 PMD sublayers and MDIto the ISO/IEC Open System Interconnection (OSI) reference model.

155.2 Physical Medium Dependent (PMD) service interface

[Editor’s note (to be removed prior to publication) - The service interface definitions and notation in802.3ba between PMA and PMD sublayers will be reconciled as per the service interface definitions spec-ified in 1.2.2 (see 150.2.6)].

This subclause specifies the services provided by the 40GBASE-CR4 and 100GBASE-CR10 PMDs. Theservice interface for these PMDs are described in an abstract manner and do not imply any particular imple-mentation. The PMD Service Interface supports the exchange of encoded data between the PMA and PMDentities. The PMD translates the encoded data to and from signals suitable for the specified medium.


PMD_UNITDATA.request<0:n>PMD_UNITDATA.indication<0:n>PMD_SIGNAL.indication

Figure 155–1—40GBASE-CR4 and 100GBASE-CR10 PMDs relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model and the IEEE 802.3

CSMA/CD LAN model

LANCSMA/CD

LAYERS



RECONCILIATION

HIGHER LAYERS


PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSI REFERENCE

MODELLAYERS

MDI

MEDIUM

PMA

MDI

MEDIUM

PMA

XLGMII CGMII

FEC

PCSFEC

PCS

40GBASE-CR4 100GBASE-CR10

PHY PHY

ANAN

PMD PMD

AN = AUTO-NEGOTIATION SUBLAYERCGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEFEC = FORWARD ERROR CORRECTION SUBLAYERMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE

PMD TYPES:MEDIUM:

C = PMD FOR COPPER— 10 m



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155.2.1 PMD_UNITDATA.request

This primitive defines the transfer of data from the PMA to the PMD.


PMD_UNITDATA.request0(tx_bit0)PMD_UNITDATA.request1(tx_bit1)...PMD_UNITDATA.requesti(tx_biti)...PMD_UNITDATA.requestn(tx_bitn)

The data conveyed by PMD_UNITDATA.request0 to PMD_UNITDATA.requestn consists of four or tenparallel continuous streams of encoded bits, one stream for each lane. The tx_bit<0:n> correspond to the bitsin the tx_lane<0:n> bit streams. Each bit in the tx_bit parameter can take one of two values: ONE or ZERO.


The PMA continuously sends four or ten parallel bit streams to the PMD, each at a nominal signaling speedof 10.3125 GBd.


Upon receipt of this primitive, the PMD converts the specified streams of bits into the appropriate signals onthe MDI.

155.2.2 PMD_UNITDATA.indication

This primitive defines the transfer of data from the PMD to the PMA.


PMD_UNITDATA.indication0(rx_bit0)PMD_UNITDATA.indication1(rx_bit1)...PMD_UNITDATA.indicationi(rx_biti)...PMD_UNITDATA.indicationn(rx_bitn)

The data conveyed by PMD_UNITDATA.indication0 to PMD_UNITDATA.indicationn consists of four orten parallel continuous streams of encoded bits. The rx_bit<0:n> correspond to the bits in the rx_lane<0:n>bit streams. Each bit in the rx_bit parameter can take one of two values: ONE or ZERO.




The effect of receipt of this primitive by the client (the PMA) is described in 153.n.


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155.2.3 PMD_SIGNAL.indication



PMD_SIGNAL.indication(SIGNAL_DETECT)

The SIGNAL_DETECT parameter can take on one of two values: OK or FAIL. When SIGNAL_DETECT= FAIL, rx_bit<0:n> are undefined, but consequent actions based on PMD_UNITDATA.indication, wherenecessary, interpret rx_bit<0:n> as logic ZEROs.




The effect of receipt of this primitive by the client (the PMA) is described in 153.3.3.3.

155.3 PCS requirements for Auto-Negotiation (AN) service interface

The PCS associated with this PMD shall support the AN service interface primitive AN_LINK.indicationdefined in 73.9. (See 49.2.16 and 152.2.20)


Predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B) demands that there bean upper bound on the propagation delays through the network. This implies that implementors of MAC,MAC Control, and PHY must consider the delay maxima, and that network planners and administrators con-sider the delay constraints regarding the cable topology and concatenation of devices. A description of over-all system delay constraints and the definitions for bit-times and pause_quanta can be found in 150.3.

The sum of the transmit and the receive delays contributed by the 40GBASE-CR4 and 100GBASE-CR10PMDs and medium shall be no more than 2560 bit times. It is assumed that the round-trip delay through themedium is 1135 bit times

155.5 Skew constraints

The maximum skew between lanes is TBD.

[Editor’s note (to be removed prior to publication) - This description of skew constraints is a place holderand needs review]


The optional MDIO capability described in Clause 45 defines several variables that provide control and sta-tus information for and about the PMD. Mapping of MDIO control variables to PMD control variables isillustrated in Table 155–2 for 40GBASE-CR4 and 100GBASE-CR10. Mapping of MDIO status variables toPMD status variables is illustrated in Table 155–3 for 40GBASE-CR4 and 100GBASE-CR10


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[Editor’s note (to be removed prior to publication) - For MDIO control variables and PMD control vari-ables naming, “backplane” will be replaced with a copper interface designation.]

Table 155–2—40GBASE-CR4 and 100GBASE-CR10 MDIO/PMD control variable mapping

MDIO control variable PMA/PMD register name Register/ bit number PMD control variable


Global PMD Transmit Disable Transmit disable register 1.9.0 Global_PMD_transmit_disable

Transmit disable 9to Transmit disable 0 Transmit disable register 1.9.10 to

1.9.1PMD_transmit_disable_9 to

PMD_transmit_disable_0

Restart training Backplane PMD control register 1.150.0 mr_restart_training

Training enable Backplane PMD control register 1.150.1 mr_training_enable

Table 155–3—40GBASE-CR4 and 100GBASE-CR10 MDIO/PMD status variable mapping


Fault Status register 1 1.1.7 PMD_fault



Global PMD Receive signal detect Receive signal detect register 1.10.0 Global_PMD_signal_detect

PMD signal detect 9 to PMD signal detect 0 Receive signal detect register 1.10.10 to

1.10.1PMD_signal_detect_9 to

PMD_signal_detect_0

Receiver status 9 Backplane PMD status register 3 1.157.4 rx_trained_9

Frame lock 9 Backplane PMD status register 3 1.157.5 frame_lock_9

Start-up protocol status 9 Backplane PMD status register 3 1.157.6 training_9

Training failure 9 Backplane PMD status register 3 1.157.7 training_failure_9










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Table 155–3—40GBASE-CR4 and 100GBASE-CR10 MDIO/PMD status variable mapping



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155.6.1 Link block diagram

A 40GBASE-CR4 and 100GBASE-CR10 link is illustrated in Figure 155–2. For purposes of system con-formance, the PMD sublayer is standardized at the points described in this subclause. The electrical transmitsignal is defined at the output end of the mated connector (TP2). Unless specified otherwise, all transmittermeasurements and tests defined in 155.7.3 are made at TP2. Unless specified otherwise, all receiver mea-surements and tests defined in 155.7.4 are made at the input end of the mated connector (TP3). A mated con-nector pair has been included in both the transmitter and receiver specifications defined in 155.7.3 and155.7.4.. AC-coupling capacitors are to be included in the receiver block.

The 40GBASE-CR4 and 100GBASE-CR10 channel is defined between the transmitter and receiver blocksto include the transmiter and receiver differential controlled impedance printed circuit board insertion lossand the cable assembly insertion loss as illustrated in Figure 155–2. All cable assembly measurements are tobe made between TP1 and TP4 as illustrated in Figure 155–1. Two mated connector pairs have beenincluded in the cable assembly specifications defined in 155.8. Transmitter and receiver differential con-trolled impedance printed circuit board insertion losses are specified in 155.9.

[Editor’s note (to be removed prior to publication) - The 40GBASE-CR4 and 100GBASE-CR10 channelparameters are expected to fall within the high confidence region as defined for 10GBASE-KR in 802.3apAnnex 69B.]

NOTE—SLn and SLn<n> are the positive and negative sides of the transmit differential signal pair and DLn andDLn<n> are the positive and negative sides of the receive differential signal pair for lane n (n = 0, 1, 2, 3 or n=0, 1, 2, 3,4, 5, 6, 7, 8, 9 ).

155.6.2 PMD Transmit function

The 40GBASE-CR4 PMD transmit function shall convert the four logical bit streams requested by the PMDservice interface message PMD_UNITDATA.request (tx_bit<0:3>) into four separate electrical signalstreams. The 100GBASE-CR10 PMD Transmit function shall convert the ten logical bit streams requested

CR4 or CR10

receive function includ-ing AC-coupling

Cable Assembly

MDI MDI

Signal Shield

Signal

Signal<n>

Link Shield

4x or 10x

TP2TP1 TP4TP3

CR4 or CR10

transmit function

SLn

SLn<n>

DLn

DLn<n>

PMDServiceInterface

PMDServiceInterface

PMD PMD

tx_b

it<0:

3> o

r

rx_b

it<0:

3> o

rTx_PCB Rx_PCB

Channel SIGNAL DETECT

tx_b

it<0:

9>

rxbi

t<0:

9>

Figure 155–2—40GBASE-CR4 and 100GBASE-CR10 link (half link is illustrated)


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by the PMD service interface message PMD_UNITDATA.request (tx_bit<0:3>) into ten separate electricalsignal streams. The electrical signal streams shall then be delivered to the respective MDIs, all according tothe transmit electrical specifications in 155.7.3. A positive output voltage of SLn minus SLn<n> (differ-ential voltage) shall correspond to tx_bit = ONE.

The 40GBASE-CR4 PMD shall convey the bits received from the PMD service interface using the messagePMD_UNITDATA.request (tx_bit<0:3>) to the MDI lanes, where (SL0/<n>, SL1/<n>, SL2/<n>, SL3/<n>) = tx_bit<0:3>.The 100GBASE-CR10 PMD shall convey the ten bits received from thePMD service interface using the message PMD_UNITDATA.request(tx_bit<0:9>) to the MDI lanes, where(SL0/<n>, SL1/<n>, SL2/<n>, SL3/<n>, SL4/<n>, SL5/<n>, SL6/<n>,SL7/<n>, SL8/<n>, SL9/<n>) = tx_bit<0:9>

155.6.3 PMD Receive function

The 40GBASE-CR4 PMD Receive function shall convert the four electrical signal streams from the MDIinto four logical bit streams for delivery to the PMD service interface using the messagePMD_UNITDATA.indication (rx_bit<0:3>) as per clause 156; the 100GBASE-CR10 PMD Receive func-tion shall convert the ten electrical signal streams from the MDI into ten logical bit streams for delivery tothe PMD service interface using the message PMD_UNITDATA.indication (rx_bit<0:9>) as per clause 156,all according to the receive electrical specifications in 155.7.4. A positive input voltage level in each signalstream of DLn minus DLn<n> (differential voltage) shall correspond to a rx_bit = ONE.

The 40GBASE-CR4 PMD shall convey the bits received from the MDI lanes to the PMD service interfaceusing the message PMD_UNITDATA.indication(rx_bit<0:3>)as per clause 156, where rx_bit<0:3> =(DL0/<n>, DL1/<n>, DL2/<n>, DL3/<n>).The 100GBASE-CR10 PMD shall convey thebits received from the MDI lanes to the PMD service interface using the message PMD_UNITDATA.indi-cation(rx_bit<0:9>) as per clause 156, where rx_bit<0:9> = (DL0/<n>, DL1/<n>, DL2/<n>,DL3/<n>,DL4/<n>, DL5/<n>, DL6/<n>, DL7/<n>,DL8/<n>, DL9/<n>).

155.6.4 Global PMD signal detect function

The Global PMD signal detect function shall report to the PMD service interface, using the messagePMD_SIGNAL.indication (SIGNAL_DETECT) for 40GBASE-CR4 and PMD_SIGNAL.indication(SIGNAL_DETECT) for 100GBASE-CR10, which is signaled continuously. SIGNAL_DETECT in40GBASE-CR4 and 100GBASE-CR10 indicates the successful completion of the start-up protocol on allfour or ten lanes.

SIGNAL_DETECT, while normally intended to be an indicator of signal presence, is used by 40GBASE-CR4 and 100GBASE-CR10 to indicate the successful completion of the start-up protocol on each lane.

SIGNAL_DETECT shall be set to FAIL following system reset or the manual reset of the training state dia-gram. Upon completion of training, SIGNAL_DETECT shall be set to OK.

If training is disabled by management, SIGNAL_DETECT shall be set to OK.

If the MDIO interface is implemented, then Global_PMD_signal_detect (1.10.0) shall be continuously set tothe value of SIGNAL_DETECT as described in 45.2.1.9.5; and PMD_signal_detect_0 (1.10.1),PMD_signal_detect_1 (1.10.2), PMD_signal_detect_2 (1.10.3) and PMD_signal_detect_3 (1.10.4) shall beset to 1 or 0 depending on whether a particular lane’s signal_detect, as defined by the training state diagramin Figure 72-5, returns true or false.


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155.6.5 PMD lane-by-lane signal detect function

When the MDIO is implemented, each PMD_signal_detect_n value, where n represents the lane number inthe range 0:3 for 40GBASE-CR4 and 0:9 for 100GBASE-CR10, shall be continuously updated according tothe requirements of 155.6.4.

[Editor’s note (to be removed prior to publication) - The lane-by-lane signal definition may need refine-ment to assure lane-by-lane detection is addressed in155.5.4.]

155.6.6 Global PMD transmit disable function

The Global_PMD_transmit_disable function is optional. When implemented, it allows all of the transmittersto be disabled with a single variable.

a) When a Global_PMD_transmit_disable variable is set to ONE, this function shall turn off all of thetransmitters such that each transmitter drives a constant level (i.e., no transitions) and does notexceed the maximum differential peak-to-peak output voltage in Table 155–4.

b) If a PMD_fault (155.6.9) is detected, then the PMD may turn off the electrical transmitter in alllanes.

c) Loopback, as defined in 155.6.8, shall not be affected by Global_PMD_transmit_disable.

155.6.7 PMD lane-by-lane transmit disable function

The Global_PMD_transmit_disable function is optional. It allows the electrical transmitters in each lane tobe selectively disabled. When this function is supported, it shall meet the requirements of this subclause.

a) When the Global_PMD_transmit_disable variable is set to ONE, this function shall turn off thetransmitter such that it drives a constant level (i.e., no transitions) and does not exceed the maximumdifferential peak-to-peak output voltage specified in Table 155–4.

b) If a PMD_fault (155.6.9) is detected, then the PMD may turn off the electrical transmitter.c) Loopback, as defined in 155.6.8, shall not be affected by Global_PMD_transmit_disable.

155.6.8 Loopback mode

Loopback mode shall be provided for the 40GBASE-CR4 and 100GBASE-CR10 PMD by the transmitterand receiver of a device as a test function to the device. When loopback mode is selected, transmissionrequests passed to the transmitter are shunted directly to the receiver, overriding any signal detected by thereceiver on its attached link. Note, this bit does not affect the state of the transmitter. The method of imple-menting loopback mode is not defined by this standard.

Control of the loopback function is specified in 45.2.1.1.4.

NOTES1—The signal path that is exercised in the loopback mode is implementation specific, but it is recommended that thissignal path encompass as much of the circuitry as is practical. The intention of providing this loopback mode ofoperation is to permit diagnostic or self-test functions to test the transmit and receive data paths using actual data. Otherloopback signal paths may also be enabled independently using loopback controls within other devices or sublayers.2—Placing a network port into loopback mode can be disruptive to a network.

155.6.9 PMD_fault function

If the MDIO is implemented, PMD_fault is the logical OR of PMD_receive_fault, PMD_transmit_fault, andany other implementation specific fault.


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155.6.10 PMD transmit fault function

The PMD_transmit_fault function is optional. The faults detected by this function are implementation spe-cific, but should not include the assertion of the Global_PMD_transmit_disable function.

If a PMD_transmit_fault (optional) is detected, then the Global_PMD_transmit_disable function should alsobe asserted.

If the MDIO interface is implemented, then this function shall be mapped to the PMD_transmit_fault bit asspecified in 45.2.1.7.4.

155.6.11 PMD receive fault function

The PMD_receive_fault function is optional. The faults detected by this function are implementation spe-cific.

If the MDIO interface is implemented, then this function shall contribute to PMA/PMD receive fault bit asspecified in 45.2.1.7.5.

155.6.12 PMD control function

Each lane of the 40GBASE-CR4 or 100GBASE-CR10 PMD uses the same control function as10GBASE-KR, as defined in 72.6.10.

The random seed for the training pattern described in 72.6.10.2.6 shall be different for each of the lanes.

155.7 MDI Electrical specifications for 40GBASE-CR4 and 100GBASE-CR10

[Editor’s note (to be removed prior to publication) - 40GBASE-KR4 will also use the transmitter andreceiver electrical characteristics of 10GBASE-KR as a baseline. Consistency with Clause 154 (KR4) willbe maintained whenever possible.]

155.7.1 Signal levels

The 40GBASE-CR4 and 100GBASE-CR10 MDI is a low-swing AC-coupled differential interface. Trans-mitter to receiver path AC-coupling, as defined in 155.7.4.3, allows for interoperability between compo-nents operating from different supply voltages. Low-swing differential signaling provides noise immunityand improved electromagnetic interference (EMI).

155.7.2 Signal paths

The 40GBASE-CR4 and 100GBASE-CR10 MDI signal paths are point-to-point connections. Each path cor-responds to a 40GBASE-CR4 or 100GBASE-CR10 MDI lane and comprises two complementary signals,which form a balanced differential pair. For 40GBASE-CR4 there are four differential paths in each direc-tion for a total of eight pairs, or sixteen connections. For 100GBASE-CR10 there are ten differential paths ineach direction for a total of 20 pairs, or forty connections. The signal paths are intended to operate on twi-naxial cable assemblies ranging from 0.5 m to 10 m in length, as described in 155.8.

155.7.3 Transmitter characteristics

[Editor’s note (to be removed prior to publication) - The TBD’s and 155.6.x reference placeholders inTable 155-1 indicate the need to account for possible differences between 10GBASE-KR4 transmitter


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characteristics and 40GBASE-CR4/100GBASE-CR10 due to the differences in test points and channelcharacteristics.

Transmitter characteristics shall meet specifications at TP2, unless otherwise noted. The specifications aresummarized in Table 155–4 and detailed in 72.7.1.1 through 72.7.1.11 with the exception of the transmitterspecified in 155.7.3.3.

Table 155–4—Transmitter characteristics’ summary

Parameter Subclause reference Value Units

Signaling speed, per lane 155.7.3.3 10.3125 ± 100 ppm GBd

Unit interval nominal 155.7.3.3 96.9697 ps

Differential peak-to-peak output voltage (max.) with TX disabled

72.6.5 or 155.9.x 30(TBD) mV

Common-mode voltage limits 72.7.1.4 or 155.9.x 0–1.9(TBD) V

Differential output return loss (min.) 72.7.1.5 or 155.9.x [See Equation (72–4) and Equation (72–5)] (TBD)

dB

Common-mode output return loss (min.) 72.7.1.6 or 155.9.x [See Equation (72–6) and Equation (72–7)] (TBD)

dB

Transition time (20%–80%) 72.7.1.7 or 155.9.x 24–47 (TBD) ps

Max output jitter (peak-to-peak)Random jittera

Deterministic jitterDuty Cycle Distortionb

Total jitteraJitter is specified at BER 10-12.bDuty Cycle Distortion is considered part of the deterministic jitter distribution.

72.7.1.8 or 155.9.x0.15(TBD)0.15(TBD)0.035(TBD)0.28(TBD)

UIUIUIUI


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155.7.3.1 Test fixtures

[Editor’s note (to be removed prior to publication) - subclause to be revised as necessary to meet baselineobjectives of utilizing transmitter electrical characteristics of 10GBASE-KR, as detailed in clause 72.]

The test fixture of Figure 155–3, or its functional equivalent, is required for measuring the transmitter speci-fications described in 155.7.3.

155.7.3.2 Test-fixture impedance

[Editor’s note (to be removed prior to publication) - subclause to be revised as necessary to meet baselineobjectives of utilizing transmitter electrical characteristics of 10GBASE-KR, as detailed in clause 72.]

The differential load impedance applied to the transmitter output by the test fixture depicted in Figure 155–3shall have a return loss greater than TBD dB from 100 MHz to 6000 MHz. The reference impedance for dif-ferential return loss measurements shall be 100 Ω.

155.7.3.3 Signaling speed range

The 40GBASE-CR4 and 100GBASE-CR10 MDI signaling speed shall be 10.3125 GBd ±100 ppm per lane.The corresponding unit interval is nominally 96.9697 ps.

155.7.4 Receiver characteristics

[Editor’s note (to be removed prior to publication) - The TBD’s and 155.6.x reference placeholders inTable 155-2 indicate the need to account for possible differences between 10GBASE-KR4 receiver char-acteristics and 40GBASE-CR4/100GBASE-CR10 receiver characteristics due to the differences intestpoints and channel characteristics.]

TransmitterUnderTest

DigitalOscilloscope Postor DataAcquisitionModule

R=50Ω

MDI

R=50Ω

or Equivalent

SignalShield

R=5kΩ

R=5kΩVcom

Connected for common mode measurement only

Processing

Test FixtureTP2

Figure 155–3—Transmit test fixture


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Receiver characteristics are summarized in Table 155–5 and as detailed in 72.7.1.1 through 72.7.2.5 with theexception of the receiver characteristics specified in 155.7.4.1, 155.7.4.2, and 155.7.4.3

155.7.4.1 Bit error ratio

The receiver shall operate with a BER 10–12 or better when receiving a compliant transmit signal, as definedin 155.7.3, through a compliant cable assembly as defined in 155.8 exhibiting the maximum insertion loss of155.8.2.

155.7.4.2 Signaling speed range

A 40GBASE-CR4 and 100GBASE-CR10 receiver shall comply with the requirements of 155.7.4.1 for anysignaling speed in the range 10.3125 GBd ± 100 ppm. The corresponding unit interval is nominally 96.9697ps.

155.7.4.3 AC-coupling

[Editor’s note (to be removed prior to publication) - subclause to be revised as necessary to meet baselineobjective of utilizing receiver electrical characteristics of 10GBASE-KR, as detailed in clause 72.]

The 40GBASE-CR4 and 100GBASE-CR10 receiver shall be AC-coupled to the cable assembly to allow formaximum interoperability between various 10 Gb/s components. AC-coupling is considered to be part of thereceiver for the purposes of this standard unless explicitly stated otherwise. It should be noted that there maybe various methods for AC-coupling in actual implementations.

NOTE—It is recommended that the maximum value of the coupling capacitors be limited to TBD pF. This will limit theinrush currents to the receiver that could damage the receiver circuits when repeatedly connected to transmit moduleswith a higher voltage level.

155.8 Cable assembly characteristics

The 40GBASE-CR4 and 100GBASE-CR10 cable assembly contains insulated conductors terminated in aconnector at each end for use as a link segment between MDIs. This cable assembly is primarily intended as

Table 155–5—Receiver characteristics’ summary

Parameter Subclause reference Value Units

Bit error ratio 155.7.4.1 10–12

Signaling speed, per lane 155.7.4.2 10.3125 ± 100 ppm GBd

Unit interval (UI) nominal 155.7.4.2 96.9697 ps

Receiver coupling 155.7.4.3 AC

Differential input peak-to-peak amplitude (maximum) 72.7.2.4 1200a

aThe receiver shall tolerate amplitudes up to 1600 mV without permanent damage

mV

Differential input return loss (minimum)b

bRelative to 100 Ω differential.

72.7.2.5 [See Equation (72–4) and Equation (72–5)] (TBD)

dB


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a point-to-point interface of up to 10 m between network ports using controlled impedance cables. All cableassembly measurements are to be made between TP1 and TP4 as illustrated in Figure 155–2. These cableassembly specifications are based upon twinaxial cable characteristics, but other cable types are acceptableif the specifications are met.

Table 155–6—Cable assembly differential characteristics’ summary

Description Reference Value Unit

Maximum Insertion loss at 5.15625 GHz 155.8.2 and 155.8.3 TBD dB

Minimum Return loss at 5.15625 GHz 155.8.3 TBD dB

Minimum NEXT loss at 5.15625 GHz 155.8.4.1 TBD dB

Minimum MDNEXT loss at 5.15625 GHz 155.8.4.2 TBD dB

Minimum ELFEXT loss at 5.15625 GHz 155.8.5.1 TBD dB

Minimum MDELFEXT loss at 5.15625 GHz 155.8.5.2 TBD dB


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155.8.1 Characteristic impedance and reference impedance

The nominal differential characteristic impedance of the cable assembly is 100 Ω. The differential referenceimpedance for cable assembly specifications shall be 100 Ω.

155.8.2 Cable assembly insertion loss

[Editor’s note (to be removed prior to publication) - Cable assembly characteristics figure files to beincluded on resolution of equation TBD’s.]

The insertion loss (in dB with f in MHz) of each pair of the 10GBASE-CR4 and 100GBASE-CR10 cableassembly shall be:

(155–1)

for all frequencies from 100 MHz to 6000 MHz. This includes the attenuation of the differential cablingpairs and the assembly connectors.

The maximum cable assembly insertion loss is illustrated in Figure 155–4.

Figure 155–4—Maximum cable assembly insertion loss (informative)

Insertion Loss f( ) TBD f×( ) TBD f×( ) TBDf

------------⎝ ⎠⎛ ⎞+ +≤


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155.8.3 Cable assembly return loss

The return loss (in dB with f in MHz) of each pair of the 40GBASE-CR4 and 100GBASE-CR10 cableassembly shall be:

(155–2)

for 100 MHz ≤ f < TBD MHz.

(155–3)

for TBD MHz ≤ f ≤ 6000 MHz.

The minimum cable assembly return loss is illustrated in Figure 155–5.

Figure 155–5—Minimum cable assembly return loss (informative)

155.8.4 Near-End Crosstalk (NEXT)

155.8.4.1 Differential Near-End Crosstalk

In order to limit the crosstalk at the near end of a link segment, the differential pair-to-pair Near-EndCrosstalk (NEXT) loss between any of the four or ten transmit lanes and any of the four or ten receive lanesis specified to meet the BER objective specified in 155.7.4.1. The NEXT loss between any transmit andreceive lane of a link segment (in dB with f in MHz) shall be at least:

Return Loss f( ) TBD TBD– fTBD------------⎝ ⎠

⎛ ⎞log×≥

Return Loss f( ) TBD≥


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(155–4)

for all frequencies from 100 MHz to 6000 MHz.

155.8.4.2 Multiple Disturber Near-End Crosstalk (MDNEXT)

Since four or ten transmit and four or ten receive lanes are used to transfer data between PMDs, the NEXTthat is coupled into a receive lane will be from the four or ten transmit lanes. To ensure the total NEXT cou-pled into a receive lane is limited, multiple disturber NEXT loss is specified as the power sum of the individ-ual NEXT losses.

The Power Sum loss between a receive lane and the four or ten transmit lanes (in dB with f in MHz) shall beat least:

(155–5)


MDNEXT loss is determined by summing the power of the four or ten individual pair-to-pair differentialNEXT loss values over the frequency range 100 MHz to 6000 MHz as follows:

(155–6)

where

MDNEXTloss(f) is the MDNEXT loss at frequency f,NL(f)i is the power of the NEXT loss at frequency f of pair combination i, in dB,f is frequency ranging from 100 MHz to 6000 MHz,i is the 0 to 3 (pair-to-pair combination) or 0 to 9 (pair-to-pair combination).

NEXT f( ) TBD TBD– fTBD------------⎝ ⎠

⎛ ⎞log×≥

MDNEXT f( ) TBD TBD– fTBD------------⎝ ⎠

⎛ ⎞log×≥

MDNEXTloss f( ) 10– 10NL f( )i– 10⁄

i 0=

i 3or9=

∑⎝ ⎠⎜ ⎟⎛ ⎞

log×=


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The minimum cable assembly NEXT / MDNEXT loss is illustrated in Figure 155–6.

Figure 155–6—Minimum cable assembly NEXT / MDNEXT loss (informative)

155.8.5 Far-End Crosstalk (FEXT)

155.8.5.1 Equal Level Far-End Crosstalk (ELFEXT) loss

Equal Level Far-End Crosstalk (ELFEXT) loss is specified in order to limit the crosstalk at the far end ofeach link segment and meet the BER objective specified in 155.7.4.1. Far-End Crosstalk (FEXT) is crosstalkthat appears at the far end of a lane (disturbed lane), which is coupled from another lane (disturbing lane)with the noise source (transmitters) at the near end. FEXT loss is defined as

FEXT_Loss(f) = 20 × log(Vpds(f)/Vpcn(f))

and ELFEXT Loss is defined as

ELFEXT_Loss(f) = 20 × log(Vpds(f)/Vpcn(f)) – SLS_Loss(f)

where

FEXT_Loss(f) is the FEXT loss at frequency f,ELFEXT_Loss(f) is the ELFEXT loss at frequency f,Vpds is the peak voltage of the disturbing signal (near-end transmitter),Vpcn is the peak crosstalk noise at the far end of the disturbed lane,SLS_Loss(f) is the insertion loss of the disturbed lane in dB,f is frequency ranging from 100 MHz to 6000 MHz.

The worst pair ELFEXT loss between any two lanes shall be at least:


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(155–7)


155.8.5.2 Multiple Disturber Equal Level Far-End Crosstalk (MDELFEXT) loss

Since four lanes or ten lanes are used to transfer data between PMDs, the FEXT that is coupled into a datacarrying lane will be from the three other lanes or nine other lanes in the same direction. To ensure the totalFEXT coupled into a lane is limited, multiple disturber ELFEXT loss is specified as the power sum of theindividual ELFEXT losses.

The Power Sum loss (labeled as MDELFEXT) between a lane and the three or nine adjacent disturbers shallbe at least:

(155–8)


Figure 155–7—Multiple Disturber Equal Level Far-End Crosstalk (MDELFEXT) loss

ELFEXT f( ) TBD TBD– fTBD------------⎝ ⎠

⎛ ⎞log×≥

MDELFEXT f( ) TBD TBD– fTBD------------⎝ ⎠

⎛ ⎞log×≥


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MDELFEXT loss is determined by summing the power of the three or nine individual pair-to-pair differen-tial ELFEXT loss values over the frequency range 100 MHz to 6000 MHz as follows:

(155–9)

where

MDELFEXTloss(f) is the MDELFEXT loss at frequency f,NL(f)i is the power of ELFEXT loss at frequency f of pair combination i, in dB,f is frequency ranging from 100 MHz to 6000 MHz,i is the 0 to 3 (pair-to-pair combination) or 0 to 9 (pair-to-pair combination).

The minimum cable assembly ELFEXT / MDELFEXT loss is illustrated in Figure 155–8.

Figure 155–8—Minimum cable assembly ELFEXT / MDELFEXT loss (informative)

155.8.6 Shielding

The cable assembly shall provide Class 2 or better shielding in accordance with IEC 61196-1.

155.8.7 Crossover function

The cable assembly shall be wired in a crossover fashion as illustrated in Figure 155–9, with each of the fouror ten pairs being attached to the transmitter contacts at one end and the receiver contacts at the other end.

MDELFEXTloss f( ) 10– 10NL f( )i– 10⁄

i 0=

i 3or9=

∑⎝ ⎠⎜ ⎟⎛ ⎞

log×=


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Figure 155–9—Cable wiring

NOTE—SLn and SLn<n> are the positive and negative sides of the differential signal pair for Lane n (n = 0,1,2,3) orLane n (n = 0,1,2,3,4,5,6,7,8,9)

155.9 Transmitter and receiver diferential printed circuit board trace loss

[Editor’s note (to be removed prior to publication) - subclause to be specify loss function of the form in(69B-6). PCB trace loss to be consistent with guidance on minimum PCB length found innicholl_01_0708.pdf.]

The 40GBASE-CR4 and 100GBASE-CR10 channel is defined between the transmitter and receiver blocksto include the transmiter and receiver differential controlled impedance printed circuit board insertion loss(Figure 155–2).

The maximum insertion loss (in dB with f in MHz) for the transmitter or the receiver differential controlledimpedance printed circuit board for each differential lane shall be:

(155–10)


155.10 MDI specification

This subclause defines the Media Dependent Interface (MDI). The 40GBASE-CR4 and 100GBASE-CR10PMD, as per 155.7, is coupled to the cable assembly, as per 155.8, by the MDI.

155.10.1 40GBASE-CR4 MDI connectors

Connectors meeting the requirements of 155.10.1.1 (Style-1) and 155.10.1.2 (Style-2) shall be used as themechanical interface between the PMD of 155.6 and the cable assembly of 155.7. The plug connector shallbe used on the cable assembly and the receptacle on the PHY. Style-1 or style-2 connectors may be used asthe MDI interface.

155.10.1.1 Style-1 40GBASE-CR4 MDI connectors

[Editor’s note (to be removed prior to publication) - Style-1 40GBASE-CR4 MDI connectors figure filesto be included in revision.]

The connector for each end of the cable assembly shall be the quad small form factor pluggable (QSFP) plugwith the mechanical mating interface defined by IEC XXXXX-X-XX and illustrated in Figure 155–10. The

DLnDLn<n>

SLnSLn<n>

DLnDLn<n>

SLnSLn<n>

Signal ShieldSignal Shield

Signal Shield Signal Shield

Link Shield Link Shield

Insertion Loss f( ) TBD( )≤


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MDI connector shall be the quad small form factor pluggable (QSFP) receptacle with the mechanical matinginterface defined by IEC XXXXX-X-XX and illustrated in Figure 155–11. These connectors have a pinoutmatching that in Table 155–7, and electrical performance consistent with the signal quality and electricalrequirements of 155.7 and 155.8.

Figure 155–10—Example cable assembly plug (informative)

Figure 155–11—Example MDI board receptacle (informative)

The MDI connector of the PMD comprises 38 signal connections. The Style-1 40GBASE-CR4 MDI con-nector pin assignments shall be as defined in Table 155–7.

Table 155–7—Style-1 40GBASE-CR4 lane to MDI connector pin mapping

Rx lane MDI Connector pin Tx lane MDI

Connector pin

S1

S2

G1

S16

S15

G9

S15

S16

G9

S2

S1

G1


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155.10.1.1.1 Style-1 hardware pin definitions

[Editor’s note (to be removed prior to publication) - subclause to specify pin assignment states to imple-ment baseline objective to enable detection of copper versus fiber or no module present.]

155.10.1.2 Style-2 40GBASE-CR4 MDI connectors

The connector for each end of the cable assembly shall be the latch-type plug with the mechanical matinginterface defined by IEC 61076-3-113 and illustrated in Figure 155–12. The MDI connector shall be thelatch-type receptacle with the mechanical mating interface defined by IEC 61076-3-113 and illustrated inFigure 155–13. These connectors have a pinout matching that in Table 155–8, and electrical performanceconsistent with the signal quality and electrical requirements of 155.7 and 155.8.

Figure 155–12—Example Style-2 cable assembly plug (informative)

Figure 155–13—Example Style-2 MDI board receptacle (informative)

155.10.1.2.1 Style-2 40GBASE-CR4 Connector pin assignments

[Editor’s note (to be removed prior to publication) - Tables and figure file numbers below need to beupdated.]

S1

S2

G1

S16

S15

G9

S15

S16

G9

S2

S1

G1


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The MDI connector of the PMD comprises 16 signal connections, eight signal shield connections, and onelink shield connection. The 10GBASE-CR4 MDI connector pin assignments shall be as defined in TableTable 155–8.

155.10.2 100GBASE-CR10 MDI connectors

[Editor’s note (to be removed prior to publication) - 100GBASE-CR10 MDI connectors figure files to beincluded in revision.]

The connector for each end of the cable assembly shall be the SFF-8092 plug with the mechanical matinginterface defined by IEC XXXXX-X-XX and illustrated in Figure 155–14. The MDI connector shall be theSFF-8092 receptacle with the mechanical mating interface defined by IEC XXXXX-X-XX and illustrated inFigure 155–15. These connectors have a pinout matching that in Table 155–9, and electrical performanceconsistent with the signal quality and electrical requirements of 155.7 and 155.8.

Figure 155–14—Example cable assembly plug (informative)

Table 155–8—Style-2 40GBASE-CR4 lane to MDI connector pin mapping


Connector pin

DL0 S1 SL0 S16

DL0<n> S2 SL0<n> S15






DL3<n> S8 SL3<n> S9

Signal Shield G1 Signal Shield G5




— — Link Shield G9

S1

S2

G1

S16

S15

G9


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Figure 155–15—Example MDI board receptacle (informative)

The MDI connector of the PMD comprises 84 connections. The 100GBASE-CR10 PMD MDI connectorpin assignments shall be as defined in Table 155-13.

155.11 Environmental specifications

All equipment subject to this clause shall conform to the applicable requirements of 14.7.

Table 155–9—100GBASE-CR10 lane to MDI connector pin mapping


Connector pin

S15

S16

G9

S2

S1

G1


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155.12 Protocol implementation conformance statement (PICS) proforma for Clause 155, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10


The supplier of a protocol implementation that is claimed to conform to Clause155 Physical MediumDependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10, shall com-plete the following protocol implementation conformance statement (PICS) proforma. A detailed descrip-tion of the symbols used in the PICS proforma, along with instructions for completing the PICS proforma,can be found in Clause 21.

[Editor’s note (to be removed prior to publication) - PICs to be added prior to publication]


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156. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10

156.1 Overview

The 40GBASE-SR4 and 100GBASE-SR10 PMD sublayers provide point-to-point 40 Gb/s and 100 Gb/sEthernet links over four or ten pairs of multimode fiber, up to at least 100 m. Table 156–1 shows the primaryattributes of each PMD type.

This clause specifies the 40GBASE–SR4 PMD and the 100GBASE–SR10 PMD together with the multi-mode fiber medium. These two PMDs are very similar. 40GBASE–SR4 uses four identical lanes, while100GBASE–SR10 uses ten of the same lanes. In this clause, where there are four or ten items depending onPMD type, the number of items is represented by n+1, and an example item by i. Thus n is 3 or 9.

Figure 156–1 shows the relationship of the PMD and MDI (shown shaded) with other sublayers to theISO/IEC Open System Interconnection (OSI) reference model. The purpose of each PHY sublayer is sum-marized in 152.1.4. 40 Gb/s and 100 Gb/s Ethernet is introduced in Clause 150. Further relevant informationmay be found in Clause 1 (terminology and conventions, references, definitions and abbreviations) andAnnex A (bibliography, entries referenced here in the format [Bn]).

When forming a complete Physical Layer, each PMD shall be connected to the appropriate PMA as shownin Table 156–2, and to the medium through the MDI. A PMD is optionally combined with the managementfunctions that may be accessible through the management interface defined in Clause 45.

156.1.1 Physical Medium Dependent (PMD) service interface

Editor’s note (to be removed prior to publication) - The service interface definitions and notation in802.3ba between PMA and PMD sublayers will be reconciled as per the service interface definitions spec-ified in 1.2.2 (see 150.2.6)]

This subclause specifies the services provided by the 40GBASE-SR4 and 100GBASE-SR10 PMDs. Theservice interfaces for these PMDs are described in an abstract manner and do not imply any particular imple-mentation (an optional implementation is specified in 156.6.1 and 156.6.5). The PMD service interface sup-ports the exchange of encoded data between the PMA and PMD entities. The PMD translates the encodeddata to and from signals suitable for the specified medium.

Table 156–1—Summary of 40GBASE–SR4 and 100GBASE–SR10

PMD Type 40GBASE–SR4 100GBASE–SR10 Unit

Fiber type Type A1aa (50/125 μm multimode) “OM3”

a Specified in IEC 60793-2-10

Number of fiber pairs 4 10

Nominal wavelength 850 nm

Minimum range 0.5 to 100 m

Signaling rate, each lane 10.3125 ±100 ppm Gbd


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Table 156–2—PMD type and associated clauses

Associated clause 40GBASE–SR4 100GBASE–SR10

151—RS Required Required

151—XLGMIIa Optional Not applicable

151—CGMIIa Not applicable Optional

152—PCS for 40GBASE-R Required Not applicable

152—PCS for 100GBASE-R Not applicable Required

153—PMA for 40GBASE-R4 (4 lanes at PMD service interface) Required Not applicable

153—PMA for 100GBASE-R10 (10 lanes at PMD service interface) Not applicable Required

156—40GBASE-SR4 PMD Required Not applicable

156—100GBASE-SR10 PMD Not applicable Required

a XLMII and CGMII are optional interfaces. However, if the appropriate MII is not implemented, a conforming imple-mentation must behave functionally as though the RS, and XLMII or CGMII, were present.

Figure 156–1—40GBASE-SR4 and 100GBASE-SR10 PMD relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model and IEEE 802.3 CSMA/CD LAN model

PMD TYPES:MEDIUM:

S = PMD FOR MULTIMODE FIBER — 100 m


CGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENTPPI = PARALLEL PHYSICAL INTERFACEXLGMII = 40 Gb/s MEDIA INDEPENDENT INTERFACE

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

MAC—Media Access Control

MDIMEDIUM

CGMII

100GBASE-R PCS

PMD

PMA

100GBASE-SR10

PHYPPI

HIGHER LAYERS



MDIMEDIUM

XLGMII

40GBASE-R PCS

PMD

PMA

RECONCILIATION

40GBASE-SR4

PHYPPI



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PMD_UNITDATA.request<0:n>PMD_UNITDATA.indication<0:n>PMD_SIGNAL.indication

156.1.1.1 PMD_UNITDATA.request



PMD_UNITDATA.request0(tx_bit0)PMD_UNITDATA.request1(tx_bit1)...PMD_UNITDATA.requesti(tx_biti)...PMD_UNITDATA.requestn(tx_bitn)

The data conveyed by PMD_UNITDATA.request0 to PMD_UNITDATA.requestn consists of four or tenparallel continuous streams of encoded bits, one stream for each lane. The tx_bit<0:n> correspond to the bitsin the tx_lane<0:n> bit streams. Each bit in the tx_bit parameter can take one of two values: ONE or ZERO.


The PMA continuously sends four or ten parallel bit streams PMA_UNITDATA.outputi(output_bit_lane_i)to the PMD, each at a nominal signaling rate of 10.3125 GBd (see 153.3.2).






PMD_UNITDATA.indication0(rx_bit0)PMD_UNITDATA.indication1(rx_bit1)...PMD_UNITDATA.indicationi(rx_biti)...PMD_UNITDATA.indicationn(rx_bitn)

The data conveyed by PMD_UNITDATA.indication0 to PMD_UNITDATA.indicationn consists of four orten parallel continuous streams of encoded bits. The rx_bit<0:n> correspond to the bits in the rx_lane<0:n>bit streams. Each bit in the rx_bit parameter can take one of two values: ONE or ZERO.




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This primitive is received by the client (the PMA) as PMA_UNITDATA.inputi(input_bit_lane_i). Theeffect of receipt is described in 153.3.1.3.

156.1.1.3 PMD_SIGNAL.indication




The SIGNAL_DETECT parameter can take on one of two values: OK or FAIL. When SIGNAL_DETECT= FAIL, rx_bit<0:n> are undefined, but consequent actions based on PMD_UNITDATA.indication, wherenecessary, interpret rx_bit<0:n> as logic ZEROs.

NOTE—SIGNAL_DETECT = OK does not guarantee that rx_bit<0:n> are known to be good. It is possible for a poorquality link to provide sufficient light for a SIGNAL_DETECT = OK indication and still not meet the 10–12 BERobjective.




The effect of receipt of this primitive as PMA_SIGNAL.input(SIGNAL_OK) by the client (the PMA) isdescribed in 153.3.3.3.

156.2 Delay and skew


A 40GBASE-SR4 PMD shall incur a round-trip delay (transmit and receive) of not more than 1024 TBC bit-times, or 2 TBC pause_quanta, including 2 m of fiber. A 100GBASE-SR10 PMD shall incur a round-tripdelay (transmit and receive) of not more than 2048 TBC bit-times, or 4 TBC pause_quanta, including 2 m offiber. A description of overall system delay constraints and the definitions for bit-times and pause_quantacan be found in 44.3.

[Editor’s note (to be removed prior to publication) - The 10G optical PMA/PMDs (except LRM) haveround-trip delay maxima of 512 MAC bit times or 1 pause_quantum; LRM has 18 pause_quanta. Since thedelay of 2 m of fiber is ~10 ns or 1000 bit times at 100 Gbit/s the minimum practical value is 1536 bit timesor 3 pause_quanta: that’s only 55 UI at 10.3125 GBd for two sublayers, round trip including PCB traces(say 2 ns or ~20 UI) but excluding the 2 m of fiber. To allow for future PMD developments that may involveEDC without disturbing the upper layers we should plan to keep the delay the same for future PMD typesand avoid the bare minimum, hence 4 proposed above giving 108 UI. At 40G, 2 pause_quanta allows161 UI. Further, the delay should be specified for the individual blocks implemented by different parties;separate specs for PMA and PMD, and for transmit and receive directions.]

156.2.2 Skew constraints

The relative delay between the lanes (skew) must be kept within limits so that the information on the lanesmay be reassembled by the PCS. The four or ten signals received from the PMA are controlled so that the


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skew is less than TBD ns and skew does not change by more than TBD, maybe 30? ps while the link is oper-ational. The delays through the four or ten PMD transmit paths shall match to within TBD ns and shall notchange by more than TBD ps while the link is operational. The medium is specified so that the delaysthrough the lanes match to within TBD ns and do not change by more than TBD ns. The delays through thefour or ten PMD receive paths shall match to within TBD ns and shall not change by more than TBD nswhile the link is operational. Therefore, the information on the lanes is returned to the PMA with a maxi-mum skew of TBD ns which cannot change by more than TBD ns while the link is operational. [Editor’snote (to be removed prior to publication) - the TBDs may be different for 40G and 100G.]


The optional MDIO capability described in Clause 45 defines several variables that may provide control andstatus information for and about the PMD. Mapping of MDIO control variables to PMD control variables isshown in Table 156–3. Mapping of MDIO status variables to PMD status variables is shown in Table 156–4.

NOTE—For 40GBASE-SR4, The highest-numbered six of the ten lane-by-lane transmit disables do not apply.

NOTE—For 40GBASE-SR4, The highest-numbered six of the ten lane-by-lane signal detects do not apply.


MDIO control variable PMA/PMD register name Register/bit number PMD control variable


Global transmit disable Transmit disable register 1.9.0 PMD_global_transmit_disable


Transmit disable 8 to Transmit disable 0

Transmit disable register 1.9.9 to 1.9.1 PMD_transmit_disable_8 to PMD_transmit_disable_0


MDIO status variable PMA/PMD register name Register/bit number PMD status variable

Local fault Status register 1 1.1.7 PMD_fault



Global PMD receive signal detect Receive signal detect register 1.10.0 PMD_global_signal_detect


PMD signal detect 8 toPMD signal detect 0

Receive signal detect register 1.10.9 to 1.10.1 PMD_signal_detect_8 to PMD_signal_detect_0


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The 40GBASE–SR4 and 100GBASE–SR10 PMDs perform the Transmit and Receive functions whichconvey data between the PMD service interface and the MDI.

156.4.1 PMD block diagram

The PMD block diagram is shown in Figure 156–2. For purposes of system conformance, the PMD sublayeris standardized at the points described in this subclause. The electrical transmit signal is defined at the output

of the Host Compliance Board (TP1a) (see 156.7.1), and other specifications of the electrical transmit inputport are defined at the input of the Module Compliance Board (TP1) (see 156.7.1). The optical transmit sig-nal is defined at the output end of a 50 μm multimode fiber patch cord (TP2), between 2 m and 5 m inlength. Unless specified otherwise, all optical transmitter measurements and tests defined in 156.7 are madeat TP2. The optical receive signal is defined at the output of the fiber optic cabling (TP3) at the MDI (see156.10.2.3). Unless specified otherwise, all optical receiver measurements and tests defined in 156.7 aremade at TP3. The electrical receive signal is defined at the output of the Module Compliance Board (TP4),and other specifications of the electrical receiver input port are defined at the input of the Host ComplianceBoard (TP4a). Figure 156–3 shows the test points in more detail.


The PMD Transmit function shall convert the four or ten electronic bit streams requested by the PMD ser-vice interface messages PMD_UNITDATA.request<0:n> into separate optical signal streams. The opticalsignal streams are delivered to the MDI, which contains at least four or ten parallel light paths for transmit,according to the transmit optical specifications in this clause. The higher optical power level in each signalstream shall correspond to tx_bit = ONE.

L0

Li

Ln

L1

Opticaltransmitter

tx_l

ane<

0:n>

rx_l

ane<

0:n>

PMD service interface

PMD service interface

L0

Li

Ln

L1

SIGNAL_DETECT

Figure 156–2—Block diagram for 40GBASE–SR4 and 100GBASE–SR10 transmit / receive paths

TP1<0:n> TP4<0:n>

Ret

imer

fun

ctio

n (p

art o

f PM

A)

...

...

Opticaltransmitter

Opticaltransmitter

Opticaltransmitter

Opticalreceiver

...

...

Opticalreceiver

Opticalreceiver

Opticalreceiver

Ret

imer

fun

ctio

n (p

art o

f PM

A)

&

For clarity, only one direction of transmission is shown

Patchcord

MDI

n+1 n+1

TP3<0:n>TP2<0:n>

MDIOptical fiber

cable PMDPMD


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The PMD Receive function shall convert the four or ten parallel optical signal streams received from theMDI into separate electronic bit streams for delivery to the PMD service interface using the messagesPMD_UNITDATA.indication<0:n>, all according to the receive optical specifications in this clause. Thehigher optical power level in each signal stream shall correspond to rx_bit = ONE.

156.4.4 PMD global signal detect function

The PMD global signal detect function shall report the state of SIGNAL_DETECT via the PMD serviceinterface. The SIGNAL_DETECT parameter is signaled continuously, while the PMD_SIGNAL.indicationmessage is generated when a change in the value of SIGNAL_DETECT occurs.

SIGNAL_DETECT shall be a global indicator of the presence of optical signals on all lanes. The value ofthe SIGNAL_DETECT parameter shall be generated according to the conditions defined in Table 156–5.

The PMD receiver is not required to verify whether a compliant 40GBASE-SR4 or 100GBASE-SR10 signalis being received. This standard imposes no response time requirements on the generation of theSIGNAL_DETECT parameter.

As an unavoidable consequence of the requirements for the setting of the SIGNAL_DETECT parameter,implementations must provide adequate margin between the input optical power level at which theSIGNAL_DETECT parameter is set to OK, and the inherent noise level of the PMD including the effects ofcrosstalk, power supply noise, etc.

Various implementations of the Signal Detect function are permitted by this standard, including implemen-tations that generate the SIGNAL_DETECT parameter values in response to the amplitude of the modula-tion of the optical signal and implementations that respond to the average optical power of the modulatedoptical signal.

156.4.5 PMD lane by lane signal detect function

Various implementations of the Signal Detect function are permitted by this standard. When the MDIO isimplemented, each PMD_signal_detect_i, where i represents the lane number in the range 0:n, shall be con-tinuously set in response to the magnitude of the optical signal on its associated lane, according to therequirements of Table 156–5.

Table 156–5—SIGNAL_DETECT value definition

Receive conditions SIGNAL_DETECT value

For any lane; Input_optical_power ≤ -30 dBm FAIL

For all lanes; [(Input_optical_power ≥ stressed receiver sensitivity (max) in OMA in Table 156–10) and (compliant 40GBASE–SR4 or 100GBASE–SR10 signal input as appropriate)]

OK

All other conditions Unspecified


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156.4.6 PMD reset function

If the MDIO interface is implemented, and if PMD_reset is asserted, the PMD shall be reset as defined in45.2.1.1.1.

156.4.7 PMD global transmit disable function

The PMD_global_transmit_disable function is optional and allows all of the optical transmitters to bedisabled.

a) When the PMD_global_transmit_disable variable is set to ONE, this function shall turn off all of theoptical transmitters so that the each transmitter meets the requirements of the average launch powerof the OFF transmitter in Table 156–8.

b) If a PMD_fault is detected, then the PMD may set the PMD_global_transmit_disable to ONE,turning off the optical transmitter in each lane.

156.4.8 PMD lane by lane transmit disable function

The PMD_transmit_disable_i function (where i represents the lane number in the range 0:n) is optional andallows the optical transmitter in each lane to be selectively disabled.

a) When a PMD_transmit_disable_i variable is set to ONE, this function shall turn off the optical trans-mitter associated with that variable so that the transmitter meets the requirements of the averagelaunch power of the OFF transmitter in Table 156–8.

b) If a PMD_fault is detected, then the PMD may set each PMD_transmit_disable_i to ONE, turningoff the optical transmitter in each lane.

If the optional PMD_transmit_disable_i function is not implemented in MDIO, an alternative method maybe provided to independently disable each transmit lane.

156.4.9 PMD fault function

If the MDIO is implemented, and the PMD has detected a local fault on any of the transmit or receive paths,the PMD shall set PMD_fault to ONE.

156.4.10 PMD transmit fault function (optional)

If the MDIO is implemented, and the PMD has detected a local fault on any transmit lane, the PMD shall setthe PMD_transmit_fault variable to ONE.

156.4.11 PMD receive fault function (optional)

If the MDIO is implemented, and the PMD has detected a local fault on any receive lane, the PMD shall setthe PMD_receive_fault variable to ONE.

156.5 Lane assignments

There are no lane assignments for 40GBASE-SR4 and 100GBASE-SR10. While it is expected that a PMDwill map electrical lane i to optical lane i and vice versa, there is no need to define where the lanes are phys-ically, as the PCS is capable of receiving with the lanes in any arrangement.


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156.6 PMD to MDI optical specifications for 40GBASE–SR4 and 100GBASE-SR10

The operating range for the 40GBASE–SR4 and 100GBASE–SR10 PMD is defined in Table 156–1. A com-pliant PMD operates on type A1a (50/125 µm) multimode fibers according to the specifications ofTable 156–17. A PMD which exceeds the operational range requirement while meeting all other opticalspecifications is considered compliant (e.g., operating at 125 m meets the minimum range requirement of0.5 m to 100 m). The signalling rate for a lane of a 40GBASE–SR4 or 100GBASE–SR10 PMD shall be asdefined in Table 156–1. Test points are defined in 156.7.1.

156.6.1 40GBASE–SR4 and 100GBASE-SR10 transmitter electrical specifications

Each lane of the electrical transmit signal for a 40GBASE–SR4 or 100GBASE–SR10 transmitter, if mea-sured at TP1a (see 156.7.1), shall meet the appropriate specifications of Table 156–6 per the definitions in

156.7. Each lane of the 40GBASE–SR4 or 100GBASE–SR10 transmitter, if measured at TP1 and TP1a(see 156.7.1), shall meet the appropriate specifications of Table 156–7 per the definitions in 156.7. It is notrequired that this interface be exposed or measurable. However, if it is not, a conforming implementationmust behave as though the interface were compliant.

[Editor’s note (to be removed prior to publication) - the following is from the baseline: presentation toprogress this requested.All values are provisional, shown for example, and will benefit from additional study. As requirements for100 m MMF and 10 m Cu are harmonized, DJ jitter tolerance may be relaxed and the maximum input signalamplitude tolerance increased depending on the maximum supported PCB trace length. Alternatively, theASIC could generate different signal amplitudes for copper and fiber.]

156.6.1.1 SDD11 at TP1a

The magnitude of SDD11 at TP1a (see 156.7.1) shall not exceed the limit given by:

Table 156–6—Electrical transmit signal output specifications

Parameter description Min Max Units Conditions

Single ended output voltage –0.3 4.0 V Referred to signal common

AC common mode output voltage – 15 mV RMS

TP1a Total Jitter outputa

a [Editor’s note (to be removed prior to publication) - For further study, intermediate between 10G SFP+ and 8GFC]

[Editor’s note (to be removed prior to publication) - Table notes in italic are from the baseline and are not expectedto appear in the final draft]

– 0.30 UI At BER = 10–12

TP1a Deterministic Jitter output UI

Specification values

Eye mask coordinates: X1, X2,Y1, Y2

0.15, TBD90, 350

UImV

TBD


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20×log10(|SDD11|) ≤ max(–12 + 2×√(f), –6.3+13×log10(f/5.5)) (156-1)

where f is the frequency in GHz.

156.6.2 Transmitter optical specifications

Each lane of a 40GBASE–SR4 or 100GBASE–SR10 optical transmitter shall meet the specifications ofTable 156–8 per the definitions in 156.7.

Table 156–7—Electrical transmit signal input specifications


Single ended input voltage tolerance –0.3 4.0 V Referred to TP1 sig-nal common

AC common mode input voltage tolerance 15 mV RMS

Differential input reflection coefficient, SDD11 – See 156.6.1.1 dB 10 MHz to 11.1 GHz

Reflected differential to common mode conversion, SCD11

– –10 dB 10 MHz to 11.1 GHz

Total Jitter tolerance at TP1aa 0.3 – UI At BER = 10–12

Deterministic Jitter tolerance (pk-pk) TBD – UI



0.15, TBD90, 350

UImV

TBD

a [Editor’s note (to be removed prior to publication) For further study, intermediate between 10G SFP+ and 8GFC]

Table 156–8—40GBASE–SR4 and 100GBASE–SR10 optical transmit characteristics

Description Type Value Unit

Center wavelength Range 840 to 860 nm

RMS spectral widtha Max 0.65 nm

Average launch power, each laneb Max 1c dBm

Optical Modulation Amplitude (OMA), each lane Min –3c d dBm

Aggregate signal parameter TBDe, each lane TBD TBD dB

Extinction ratio Min 3 dB

RIN12OMA Max –128 to –132 TBDc d dB/Hz

Optical return loss tolerance Min 12 dB


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156.6.3 Characteristics of signal within, and at the receiving end of, a compliant optical channel (informative)

Table 156–9 gives the characteristics of a signal within, and at the receiving end of, a lane of a compliant40GBASE–SR4 or 100GBASE–SR10 optical channel, and the aggregate signal. A signal with power in

OMA and average power not within the ranges given cannot be compliant. However, a signal with powervalues within the ranges is not necessarily compliant

156.6.4 40GBASE–SR4 or 100GBASE–SR10 receiver optical specifications

Each lane of a 40GBASE–SR4 or 100GBASE–SR10 optical receiver shall meet the specifications defined inTable 156–10 per the definitions in 156.7.

156.6.5 Receiver electrical specifications

Each lane of a 40GBASE–SR4 or 100GBASE–SR10 receiver and each lane of the electrical received signalat its output shall, if measured at TP4, meet the appropriate specifications of Table 156–11 per the defini-tions in 156.7. Each lane of the device receiving the electrical received signal shall meet the specifications ofTable 156–12 at TP4 and/or TP4a per the definitions in 156.7. It is not required that this interface be exposed

Encircled flux > 86% at 19 μm,< 30% at 4.5 μmc

Transmitter eye mask definition {X1, X2, X3?, Y1, Y2, Y3?} TBD TBD

Average launch power of OFF transmitter, each lane Max –30 dBm

a RMS spectral width is the standard deviation of the spectrumb [Editor’s note (to be removed prior to publication) - Reference see presentation on eye safety by J. Petrilla at March

2008 meeting, petrilla_02_0308]c [Editor’s note (to be removed prior to publication) - Subject to further study]d [Editor’s note (to be removed prior to publication) - To be made informative if aggregate signal parameter includes

the effect]e [Editor’s note (to be removed prior to publication) - For further study, e.g. TDP, TWDP, etc.]

Table 156–9—Characteristics of signal within, and at the receiving end of, a compliant optical channel (informative)

Description Minimum Maximum Unit

Total average power for 40GBASE–SR4 –1.9 +7 dBm

Total average power for 100GBASE–SR10 +2.1 +11 dBm

Average power, each lane –7.9 +1.0 dBm

Optical Modulation Amplitude (OMA), each lane –4.9 +4.0 dBm

Table 156–8—40GBASE–SR4 and 100GBASE–SR10 optical transmit characteristics



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Table 156–10—40GBASE–SR4 and 100GBASE–SR10 optical receiver characteristics


Center wavelength, each lane Range 840 to 860 nm

Damage thresholda Min +2 dBm

Average power at receiver input, each lane Max +1b dBm

Min –7.9 b c dBm

Receiver reflectance Max –12 dB

Stressed receiver sensitivity in OMA, each laned Max TBD dBm

Conditions of stressed receiver sensitivity test:

Vertical eye closure penaltye, each lane – TBD dB

Stressed eye jitter Jf, each lane – TBD UI

a The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal havingthis power level on one lane. The receiver does not have to operate correctly at this input power.[Editor’s note (to beremoved prior to publication) - 1 dB above average receive power maximum, to allow headroom for receiver testing.]

b [Editor’s note (to be removed prior to publication) - For further study]c [Editor’s note (to be removed prior to publication) - Depends on connector loss]dMeasured with conformance test signal at TP3 (see 156.7.4.9) for BER = 10–12.eVertical eye closure penalty is a test condition for measuring stressed receiver sensitivity. It is not a required character-

istic of the receiver.fStressed eye jitter is a test condition for measuring stressed receiver sensitivity. It is not a required characteristic of the

receiver.

Table 156–11—Receiver electrical output specifications


Single ended output voltage –0.3 4.0 V Referred to signal common

AC common mode output voltage (RMS) – 7.5 mV

Termination mismatch at 1 MHz – 5 %

Differential output reflection coefficient, SDD22 – See 156.6.5.1 dB 10 MHz to 11.1 GHz

Common mode output reflection coefficient, SCC22 –

–6 dB 10 MHz to 2.5 GHz

–3 dB 2.5 GHz to 11.1 GHz

Output transition time, 20% to 80% 28 – ps

Total Jitter output at TP4 – 0.70a UI At BER = 10–12

Deterministic Jitter output at TP4 (pk-pk) – 0.40 UI


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or measurable. However, if it is not, a conforming implementation must behave as though the interface werecompliant.

[Editor’s note (to be removed prior to publication) - the following is per the baseline: presentation toprogress the specifications requested: All values are provisional, shown for example, and will benefitfrom additional study.]

156.6.5.1 SDD22 at TP4

The magnitude of SDD22 at TP4 shall not exceed the limit given by:

20×log10(|SDD22|) ≤ max(–12 + 2×√(f), –6.3+13×log10(f/5.5)) (156-2)

where f is the frequency in GHz.



0.35, TBD,150, 425

UI,mV

TBD

a [Editor’s note (to be removed prior to publication) For further study, intermediate between 10G SFP+ and 8GFC]

Table 156–12—Receiver electrical input specifications


Single ended input voltage tolerance –0.3 4.0 V Referred to TP4 signal common

Total Jitter tolerance 0.70a

a [Editor’s note (to be removed prior to publication) - For further study, intermediate between 10G SFP+ and 8GFC]

– UI

Deterministic Jitter tolerance (pk-pk) 0.40 – UI



0.35, TBD,150, 425

UI,mV

TBD

Table 156–11—Receiver electrical output specifications



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156.6.6 40GBASE–SR4 and 100GBASE–SR10 link power budget (informative)

An illustrative power budget and penalties for a 40GBASE–SR4 or 100GBASE–SR10 optical channel areshown in Table 156–13.

156.7 Definitions of electrical and optical parameters and measurement methods

156.7.1 Test points and compliance boards

Figure 156–3 shows the six test points for 40GBASE-SR4 and 100GBASE-SR10. These are TP1, TP1a,TP2, TP3, TP4 and TP4a. Figure 156–3 also shows the substitution of compliance boards for PMD or PMA.Compliance boards are defined which bridge between the specific connector used by a PMD and generic testequipment with SMA connectors, for example. The PMD can be plugged into the Module ComplianceBoard, which has specified loss and other S-parameters. The Host Compliance Board, which also has speci-fied loss and other S-parameters, can plug into the PMA. The Module Compliance Board and the Host Com-pliance Board can be plugged together for calibration of compliance signals and to check the S-parametersof the boards. Table 156–14 shows the parameters or signals measured at each point.

All optical measurements shall be made through a short patch cable, between 2 m and 5 m in length, unlessotherwise specified. A patch cord that connects the MDI transmit side to 4 or 10 individual connectors maybe suitable.

156.7.2 Test patterns and related subclauses

Compliance is to be achieved in normal operation. Table 156–15 gives the test patterns to be used in eachmeasurement, unless otherwise specified, and also lists references to the subclauses in which each parameteris defined. The test patterns include TBD, defined in TBD.

NOTE—The longer test patterns are designed to emulate system operation; however, they do not form valid40GBASE-R, 40GBASE-R4 or 100GBASE-R10 frames.

Table 156–13—40GBASE–SR4 and 40GBASE–SR10 link power budget (informative)

Parameter Value Unit

Effective modal bandwidth at 850 nm 2000a

a Depends on launch conditions

MHz•km

Power budget 8.3b

b [Editor’s note (to be removed prior to publication) - For further study]

dB

Operating distance 0.5 to 100 m

Channel insertion lossc

c The channel insertion loss is calculated using the maximum distance specified in Table 156–1 and fiber attenuation of3.5 dB/km at 850 nm plus an allocation for connection and splice loss given in 156.10.2.2.1.

1.9d

d [Editor’s note (to be removed prior to publication) - Connector loss under study]

dB

Allocation for penaltiese

e Link penalties are used for link budget calculations. They are not requirements and are not meant to be tested.

TBD dB

Additional insertion loss allowed 0 dB


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[Editor’s note (to be removed prior to publication) - Pointers to existing test patterns or definition of newpatterns to be included here. The second column of Table 156–15 is not part of the draft, but show what10GBASE-SR, 10GBASE-LR and 10GBASE-LRM use.]

156.7.3 Electrical parameters

[Editor’s note (to be removed prior to publication) - The Electrical parameters listed below need to bewritten. Additional references: SFF-8431 (D.15, D.16) or FC-PI-4 (A.1.4.4)]

156.7.3.1 AC common mode voltage

TBD

156.7.3.2 Termination mismatch

TBD

156.7.3.3 Transition time

TBD

PMA function

Figure 156–3—Test points for 40GBASE-SR4 and 100GBASE-SR10

Optical PMD

transmitter

Optical PMD

receiver

Optical PMD

transmitter

Optical PMD

receiverPatch cord2 m to 5 m

HCB

MCB

HCB

PMD PMDMediumPMA PMA

TP1 TP4

TP0 TP5

TP2 TP3

TP4aTP1a

HCB = Host Compliance BoardMCB = Module Compliance BoardPMDSI = PMD service interface

PMA function

PMA function

PMA function

MCB

MDI MDIPMDSI PMDSIUse model

Compliance points

MCB

Compliance points

TP2

HCBMCB HCB

Compliance board calibration

Termination


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Table 156–14—Parameters defined at each test point

Test point Direction Parameter

TP1 Looking downstream into PMD transmitter input

PMD transmitter S11

TP1a Looking upstream into PMA transmitter output

PMA transmitter S22, PMA transmitted signal, PMD transmitter compliance signal calibration

TP2Looking upstream into optical transmitter output

PMD transmitted signal, PMD transmitter reflectance

Looking downstream into fiber Optical return loss, connector reflections

TP3Looking upstream into fiber PMD receiver compliance signal

Looking downstream into optical receiver input

PMD receiver reflectance

TP4 Looking upstream into PMD receiver output

PMD received signal, PMD receiver S22, PMA receiver compli-ance signal calibration

TP4a Looking downstream into PMA receiver input

PMA receiver S11

Table 156–15—Test-pattern definitions and related subclauses

Parameter Pattern Related subclause

Wavelength, spectral width 1 or 3a 156.7.4.1

Average optical power 1 or 3 156.7.4.2

Transmitter OMA (modulated optical power) Square [Ed. would prefer PRBS9] 156.7.4.3

Extinction ratio 1 or 3 156.7.4.5

Transmitted waveform (eye mask) 1 or 3 156.7.4.7.2

Aggregate TP2 metric 2 or 3 156.7.4.4

RINxOMA Square 156.7.4.6

Stressed receiver sensitivity 2 or 3 156.7.4.9

Calibration of OMA for receiver tests Square, eight ONEs and eight ZEROs 52.9.9

Vertical eye closure penalty calibration 2 or 3 52.9.9

a[Editor’s note (to be removed prior to publication) - The second column of Table 156–15 is not part of the draft, butshow what 10GBASE-SR, 10GBASE-LR and 10GBASE-LRM use. Patterns 1, 2 and 3 are defined in 52.9.1.1]


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156.7.3.4 More electrical parameter definitions?

156.7.4 Optical parameter definitions

156.7.4.1 Wavelength and spectral width

The wavelength of each optical lane shall be within the range given in Table 156–8 if measured using themethod given in TIA/EIA–455–127-A. The lane under test is modulated using the appropriate portion of avalid 40GBASE–R4 or 100GBASE–R10 signal, or with a valid 10GBASE-R signal.

156.7.4.2 Average optical power

The average optical power of each lane shall be within the limits given in Table 156–8 if measured using themethods given in TIA/EIA–455–95A.

156.7.4.3 Optical Modulation Amplitude (OMA)

OMA is as defined in 52.9.5 and 68.6.2.

156.7.4.4 Aggregate TP2 signal metric

TBD

156.7.4.5 Extinction ratio

Extinction ratio shall be within the limits given in Table 156–8 if measured using the methods specified inIEC 61280–2–2 using TBD test pattern or a valid 40GBASE–R4 or 100GBASE–R10 signal.

NOTE—Extinction ratio and OMA are defined with different test patterns (see Table 156–15).

156.7.4.6 Relative Intensity Noise (RIN12OMA)

The RIN measurement methodology shall be as defined in 52.9.6 with the exception that all lanes are opera-tional in both directions (transmit and receive), and each lane is tested individually.

156.7.4.7 Eye diagrams

Eye diagrams can be used to assess both electrical and optical signals.

[Editor’s note (to be removed prior to publication) - Generic details of the eye mask measurement to beincluded here. This is being studied by the Statistical Eye Ad Hoc.]

156.7.4.7.1 Eye mask for TP1a and TP4

The eye mask is defined by parameters X1, X2, Y1 and Y2. Unlike the optical eye mask, the vertical dimen-sions are fixed rather than scaled to the signal. See Figure 153A–6 for an example eye mask, showing themeaning of the parameters.

156.7.4.7.2 Transmitter optical waveform (transmit eye)

[Editor’s note (to be removed prior to publication) - Details of the transmit eye mask measurement specificto optical to be added here.]


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156.7.4.8 Transmit jitter for each lane of 40GBASE–SR4 and 100GBASE–SR10

[Editor’s note (to be removed prior to publication) - To be written. Also has electrical and optical applica-tions.]

156.7.4.9 Stressed receiver sensitivity

Stressed receiver sensitivity shall be within the limits given in Table 156–10 if measured using the methoddefined by 52.9.9 with the conformance test signal at TP3 with jitter J and vertical eye closure penalty asgiven in Table 156–10 and added sinusoidal jitter as specified in Table 156–16.

For each lane, the stressed receiver sensitivity is defined with the transmit section in operation on all n lanesand with the receive lanes not under test in operation. The pattern for the received compliance signal is spec-ified in Table 156–15. TBD, or a valid 40GBASE–R4 or 100GBASE–R10 signal is sent from the transmitsection of the receiver under test. The data being transmitted must be asynchronous to the received data.

156.8 Safety, installation, environment, and labeling


All equipment meeting this standard shall conform to IEC 60950-1.

156.8.1.1 Laser safety

40GBASE–SR4 and 100GBASE–SR10 optical transceivers shall conform to Class 1M laser requirements asdefined in IEC 60825–1 and IEC 60825–2, under any condition of operation. This includes single fault con-ditions whether coupled into a fiber or out of an open bore.

Conformance to additional laser safety standards may be required for operation within specific geographicregions.

Laser safety standards and regulations require that the manufacturer of a laser product provide informationabout the product’s laser, safety features, labeling, use, maintenance, and service. This documentationexplicitly defines requirements and usage restrictions on the host system necessary to meet these safetycertifications.13

Table 156–16—Applied sinusoidal jitter

Frequency range Sinusoidal jitter (UIpk -pk)

f < 40 kHz Not specified

40 kHz < f ≤ 4 MHz TBD

4 MHz < f < 10 LBa

a LB = loop bandwidth; upper frequency bound for added sine jitter should be at least 10 times the loop bandwidth of thereceiver being tested.

TBD

13A host system that fails to meet the manufacturers requirements and/or usage restrictions may emit laser radiation in excess of thesafety limits of one or more safety standards. In such a case, the host manufacturer is required to obtain its own laser safety certification.


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156.8.2 Installation

It is recommended that proper installation practices, as defined by applicable local codes and regulation, befollowed in every instance in which such practices are applicable.

156.8.3 Environment

The 40GBASE–SR4 and 100GBASE–SR10 operating environment specifications are as defined in 52.11, asdefined in 52.11.1 for electromagnetic emission, and as defined in 52.11.2 for temperature, humidity, andhandling.

156.8.4 PMD labeling

The 40GBASE–SR4 and 100GBASE–SR10 labeling recommendations and requirements are as defined in52.12.

156.9 Recommended electrical channel (informative)

A recommended maximum attenuation template for the Parallel Physical Interface’s channel, between thePMA IC and TP1a or TP4a, is shown in Figure 156–4, along with a recommended minimum attenuationintended to control the effect of reflections. It is recommended that

Figure 156–4—PPI channel recommendation

0 1 2 3 4 5 6 7 8 9 10 11 12

0

-2

-4

-6

-8

-10

-15

SDD21 (dB)Example of a compliant channel

Frequency (GHz)

Minimum loss

Maximum loss


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dB(SDD21)≤ TBD + TBD × √(f) + TBD × f + TBD × f2 + TBD × f3 TBD ≤ f ≤ 7 × 109 TBC ≤ TBD 7 × 109≤ f ≤ 11.1 × 109 TBC

(156-3)anddB(SDD21) ≥ TBD + TBD × √(f) + TBD × f + TBD × f2 + TBD × f3 f ≤ TBD

≥ TBD + TBD × √(f) + TBD × f + TBD × f2 + TBD × f3 TBD ≤ f ≤ 7 × 109 TBC ≥ TBD 7 × 109≤ f ≤ 11.1 × 109 TBC

(156-4)where f is the frequency in hertz.

[Editor’s notes (to be removed prior to publication) -

The limits above to be chosen with consideration of the dimensions in nicholl_01_0708.Expect that additional criteria such as crosstalk will be added.]

156.10 Optical channel

156.10.1 Fiber optic cabling model

The fiber optic cabling model is shown in Figure 156–5.

PMDConnectionConnectionPMD

Fiber optic cabling (channel)

Figure 156–5—Fiber optic cabling model

Patchcord

PatchcordLink

MDI MDI

n+1 n+1 n+1n+1 = 4 or 10 as appropriate


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The channel insertion loss is given in Table 156–17. A channel may contain additional connectors as long as

the optical characteristics of the channel, such as attenuation, modal dispersion, reflections and losses of allconnectors and splices meet the specifications. Insertion loss measurements of installed fiber cables aremade in accordance with IEC 61280-4-1/Method 2. The fiber optic cabling model (channel) defined here isthe same as a simplex[?] fiber optic link segment. The term channel is used here for consistency withgeneric cabling standards.

156.10.2 Characteristics of the fiber optic cabling (channel)

156.10.2.1 Optical fiber and cable

The 40GBASE–SR4 and 100GBASE–SR10 fiber optic cabling shall meet the requirements of IEC 60793-2-10 and the requirements given in Table 156–18, where they differ. Multimode cables chosen from [Editor’snote (to be removed prior to publication) - Insert additional reference for multiway cable if appropriate],IEC 60794-2-11 or IEC 60794-3-12 may be suitable. The fiber optic cabling consists of one or more sectionsof fiber optic cable and any intermediate connections required to connect sections together.

156.10.2.2 Optical fiber connection

An optical fiber connection, as shown in Figure 156–5, consists of a mated pair of optical connectors.

156.10.2.2.1 Connection insertion loss

The maximum link distances for multimode fiber are calculated based on an allocation of TBD dB total con-nection and splice loss. For example, this allocation supports four connections with an average insertion lossper connection of TBD dB. Connections with different loss characteristics may be used provided the require-ments of Table 156–17 and Table 156–18 are met.

156.10.2.3 Medium Dependent Interface (MDI) requirements

The 40GBASE–SR4 and 100GBASE–SR10 PMD is coupled to the fiber optic cabling at the MDI. The MDIis the interface between the PMD and the “fiber optic cabling” (as shown in Figure 156–5). The MDI has at

Table 156–17—Fiber optic cabling (channel) characteristics


Operating distance Max 100 m

Length difference between optical lanes Max TBD m

Channel insertion loss Min 0 dB

Channel insertion lossa

a These channel insertion loss values are defined at 850 nm. They include cable, connectors, and splices.[

Max 1.9b

b [Editor’s note (to be removed prior to publication) - For further study]

dB

Fiber insertion loss at 850 nm Max 0.4 TBC dB

Losses of all connectors and splices Max TBD dB


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least eight optical paths for 40GBASE–SR4 or twenty optical paths for 100GBASE–SR10. Examples of anMDI include the following:

a) Connectorized fiber pigtail;b) PMD receptacle.

When the MDI is a connector plug and receptacle connection, it shall meet the interface performance speci-fications of IEC 61753-1-1 and IEC 61753-022-2.

NOTE—Compliance testing is performed at TP2 and TP3 as defined in 156.4.1, not at the MDI.

Table 156–18—Optical fiber and cable characteristics

Description Value Unit

Nominal core diameter 50 μm

Nominal fiber specification wavelength 850 nm

Effective modal bandwidtha 2000 MHz•km

Fiber cable attenuation (max) 3.5 TBC dB/km

Zero dispersion wavelength (λ0) 1295 ≤ λ0 ≤ 1320 nm

Chromatic dispersion slope (max) (S0) 0.11 for 1300 ≤ λ0 ≤ 1320 and0.001×(λ0 – 1190) for 1295 ≤ λ0 ≤ 1300

ps/nm2 km

a Effective modal bandwidth for fiber meeting TIA/EIA-492AAAC-2002 [Editor’s note (to be removed prior to publi-cation) - Is there an IEC equivalent now?] when used with sources meeting the wavelength and encircled flux speci-fications of Table 52–7.


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156.11 Protocol implementation conformance statement (PICS) proforma for Clause 156, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR1014


The supplier of a protocol implementation that is claimed to conform to Clause 156, Physical MediumDependent sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10, shall complete the follow-ing protocol implementation conformance statement (PICS) proforma.






Supplier1




NOTES




Identification of protocol standard IEEE Std 802.3ba-20xx, Clause 156, Physical Medium Dependent sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10



Date of Statement


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157. Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-LR?

157.1 Overview

[Editor’s note (to be removed prior to publication) - Baseline proposal for Physical Medium DependentSublayer for 40Gb/s over long reach, 10Km, single mode fiber, has not been adopted by the Task Force.Appropriate text will be added after the baseline proposal is adopted by the P802.3ba Task Force.

Also the corresponding PICS tables will be added to this clause after the baseline text is adopted]


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157.2 Protocol implementation conformance statement (PICS) proforma for Clause 157, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-LRx15

[Editor’s note (to be removed prior to publication) - Insert PICS, for 40GBASE-LRx after the baselinetext is adopted by the P802.3ba Task Force]


The supplier of a protocol implementation that is claimed to conform to Clause 157, Physical MediumDependent sublayer and baseband medium, type 40GBASE-LR4, shall complete the following protocolimplementation conformance statement (PICS) proforma.





Supplier1




NOTES





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Identification of protocol standard IEEE Std 802.3ba-20xx, Clause 157, Physical Medium Dependent sublayer and baseband medium, type 40GBASE-LR4



Date of Statement


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158. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4

158.1 Overview

This clause specifies the 100GBASE–LR4 PMD and the 100GBASE–ER4 PMD together with the single-mode fiber medium. In order to form a complete physical layer, each PMD shall be connected to the appro-priate sublayers indicated in Table 158–1 and optionally with the management functions that may be acces-sible through the management interface defined in Clause 45.

Figure 158–1 shows the relationship of the PMD and MDI (shown shaded) with other sublayers to the ISO/IEC (IEEE) Open System Interconnection (OSI) reference model.

158.1.1 Physical Medium Dependent (PMD) service interface

Editor’s note (to be removed prior to publication) - The service interface definitions and notation in802.3ba between PMA and PMD sublayers will be reconciled as per the service interface definitions spec-ified in 1.2.2 (see 150.2.6)]

This subclause specifies the services provided by the 100GBASE-LR4 and 100GBASE-ER4 PMDs. Theservice interfaces for these PMDs are described in an abstract manner and do not imply any particular imple-mentation. The PMD Service Interface supports the exchange of encoded data between the PMA and PMDentities. The PMD translates the encoded data to and from signals suitable for the specified medium.


PMD_UNITDATA.request<0:3>PMD_UNITDATA.indication<0:3>PMD_SIGNAL.indication

158.1.1.1 PMD_UNITDATA.request


Table 158–1—PMD type and associated clauses

Associated clause 100GBASE–LR4 100GBASE–ER4

151—RS Required Required

151—CGMIIa

aThe CGMII is an optional interface. However, if the CGMII is not implemented, a conform-ing implementation must behave functionally as though the RS and CGMII were present.

Optional Optional

152—PCS for 100GBASE-R Required Required

153—PMA for 100GBASE-R Required Required


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PMD_UNITDATA.request0(tx_bit0)PMD_UNITDATA.request1(tx_bit1)PMD_UNITDATA.request2(tx_bit2)PMD_UNITDATA.request3(tx_bit3)

The data conveyed by PMD_UNITDATA.request0 to PMD_UNITDATA.request3 consists of four parallelcontinuous streams of encoded bits, one stream for each lane. The tx_bit<0:3> correspond to the bits in thetx_lane<0:3> bit streams. Each bit in the tx_bit parameter can take one of two values: ONE or ZERO.


The PMA continuously sends four parallel bit streams to the PMD, each at a nominal signaling speed of25.78125 GBd.

158.1.1.1.3 Effect of Receipt


Figure 158–1—100GBASE-R PMD relationship to the ISO/IEC Open Systems Interconnec-tion (OSI) reference model and IEEE 802.3 CSMA/CD LAN model

PMD TYPES:MEDIUM:

L = PMD FOR FIBER - 10 Km SINGLE-MODE FIBERE = PMD FOR FIBER - 40 Km SINGLE-MODE FIBER


CGMII = 100 Gb/s MEDIA INDEPENDENT INTERFACEMDI = MEDIUM DEPENDENT INTERFACEPCS = PHYSICAL CODING SUBLAYERPHY = PHYSICAL LAYER DEVICEPMA = PHYSICAL MEDIUM ATTACHMENTPMD = PHYSICAL MEDIUM DEPENDENT

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

HIGHER LAYERS



MAC

MDIMEDIUM

CGMII

100GBASE-R PCS

PMDPMA

RECONCILIATION

100GBASE-LR4 or 100GBASE-ER4

PHY


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PMD_UNITDATA.indication0(rx_bit0)PMD_UNITDATA.indication1(rx_bit1)PMD_UNITDATA.indication2(rx_bit2)PMD_UNITDATA.indication3(rx_bit3)

The data conveyed by PMD_UNITDATA.indication0 to PMD_UNITDATA.indication3 consists of fourparallel continuous streams of encoded bits. The rx_bit<0:3> correspond to the bits in the rx_lane<0:3> bitstreams. Each bit in the rx_bit parameter can take one of two values: ONE or ZERO.




The effect of receipt of this primitive by the client (the PMA) is described in Clause 153.

158.1.1.3 PMD_SIGNAL.indication




The SIGNAL_DETECT parameter can take on one of two values: OK or FAIL. When SIGNAL_DETECT= FAIL, rx_bit<0:3> are undefined, but consequent actions based on PMD_UNITDATA.indication, wherenecessary, interpret rx_bit<0:3> as a logic ZERO.

NOTE—SIGNAL_DETECT = OK does not guarantee that rx_bit<0:3> are known to be good. It is possible for a poorquality link to provide sufficient light for a SIGNAL_DETECT = OK indication and still not meet the 10–12 BER objec-tive.




The effect of receipt of this primitive by the client (the PMA) is described in Clause 153.

158.2 Delay and skew


An upper bound to the delay through the PMA and PMD is required for predictable operation of the MACControl PAUSE operation (Clause 31, Annex 31B). The PMA and PMD shall incur a round-trip delay


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(transmit and receive) of not more than 1536 bit-times, or 3 pause_quanta, including 2 m of fiber. A descrip-tion of overall system delay constraints and the definitions for bit-times and pause_quanta can be found in44.3.

[Editor’s note (to be removed prior to publication) - The 10G optical PMDs (except LRM) all have delayrequirements of 512 bit-times or 1 pause_quantum. Since the delay of 2 metres of fiber is ~ 1000 bit timesat 103.125 Gbit/s the minimum practical value is 1536 bit times or 3 pause_quanta.]

158.2.2 Skew constraints

The relative delay between the lanes (skew) must be kept within limits so that the information on the lanesmay be reassembled by the PCS. The delays through the four PMD transmit paths shall match to withinTBD bit-times (TBD ns) and shall not change by more than TBD bit-times (TBD ns) while the link is opera-tional. The delays through the four PMD receive paths shall match to within TBD bit-times (TBD ns) andshall not change by more than TBD bit-times (TBD ns) while the link is operational.


The optional MDIO capability described in Clause 45 defines several variables that may provide control andstatus information for and about the PMD. Mapping of MDIO control variables to PMD control variables isshown in Table 158–2. Mapping of MDIO status variables to PMD status variables is shown in Table 158–3.


The 100GBASE–LR4 and 100GBASE–ER4 PMDs perform the Transmit and Receive functions whichconvey data between the PMD service interface and the MDI.

158.4.1 PMD block diagram

The PMD block diagram is shown in Figure 158–2. For purposes of system conformance, the PMD sublayeris standardized at the points described in this subclause. The optical transmit signal is defined at the outputend of a single-mode fiber patch cord (TP2), between 2 m and 5 m in length. Unless specified otherwise, alltransmitter measurements and tests defined in 158.8 are made at TP2. The optical receive signal is defined atthe output of the fiber optic cabling (TP3) at the MDI (see 158.13.3). Unless specified otherwise, all receivermeasurements and tests defined in 158.8 are made at TP3.


MDIO control variable PMA/PMD register name

Register/ bit number PMD control variable


Global transmit disable Transmit disable register 1.9.0 PMD_global_transmit_disable






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TP1 <0:3> and TP4 <0:3> are informative reference points that may be useful to implementers for testingcomponents (these test points will not typically be accessible in an implemented system).


The PMD Transmit function shall convert the four electronic bit streams requested by the PMD serviceinterface message PMD_UNITDATA.request<0:3> into four separate optical signal streams. The four opti-cal signal streams shall then be wavelength division multiplexed and delivered to the MDI, all according tothe transmit optical specifications in this clause. The higher optical power level in each signal stream shallcorrespond to tx_bit = ONE.


The PMD Receive function shall demultiplex the composite optical signal stream received from the MDIinto four separate optical signal streams. The four optical signal streams shall then be converted into fourelectronic bit streams for delivery to the PMD service interface using the messagePMD_UNITDATA.indication<0:3>, all according to the receive optical specifications in this clause. Thehigher optical power level in each signal stream shall correspond to rx_bit = ONE.

Optical Fiber Cable

tx_l

ane<

0:3>

rx_l

ane<

0:3>

PatchCord

TP2 TP3

MDI MDI

L0

L2

L3

L1

L0

L3

L1

L2

SIGNAL_DETECT

WD

Mux

WD

Dem

uxWD = Wavelength Division

NOTE—Specification of the retimer function is beyond the scope of this standard; however, a retimer may berequired to ensure compliance at test points TP2 and TP3.

Figure 158–2—Block diagram for 100GBASE–LR4 and 100GBASE–ER4 transmit/receive paths

TP1<0:3> TP4<0:3>

PMD Service Interface

Optical receiver

Optical receiver

Optical receiver

Optical receiver

PMD Service Interface

Optical transmitter

Optical transmitter

Optical transmitter

Optical transmitter

Retimer function (part of PMA)

Retimer function (part of PMA)


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158.4.4 PMD global signal detect function

The PMD global signal detect function shall report the state of SIGNAL_DETECT via the PMD serviceinterface. The SIGNAL_DETECT parameter is signaled continuously, while the PMD_SIGNAL.indicationmessage is generated when a change in the value of SIGNAL_DETECT occurs.

SIGNAL_DETECT shall be a global indicator of the presence of optical signals on all four lanes. The PMDreceiver is not required to verify whether a compliant 100GBASE-R signal is being received. This standardimposes no response time requirements on the generation of the SIGNAL_DETECT parameter.

As an unavoidable consequence of the requirements for the setting of the SIGNAL_DETECT parameter,implementations must provide adequate margin between the input optical power level at which the


MDIO status variable PMA/PMD register name

Register/ bit number PMD status variable

Local fault Status register 1 1.1.7 PMD_fault



Global PMD receive sig-nal detect

Receive signal detectregister

1.10.0 PMD_global_signal_detect

PMD signal detect 3 Receive signal detect register

1.10.4 PMD_signal_detect_3







Table 158–4—SIGNAL_DETECT value definition

Receive conditions SIGNAL_DETECT value

For any lane; Input_optical_power ≤ -30 dBm FAIL

For all lanes; [(Input_optical_power ≥ receiver sensitivity (max) in OMA in Table 158–8 or Table 158–12)

AND(compliant 100GBASE–R signal input)]

OK

All other conditions Unspecified


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SIGNAL_DETECT parameter is set to OK, and the inherent noise level of the PMD due to crosstalk, powersupply noise, etc.

Various implementations of the Signal Detect function are permitted by this standard, including implemen-tations that generate the SIGNAL_DETECT parameter values in response to the amplitude of the modula-tion of the optical signal and implementations that respond to the average optical power of the modulatedoptical signal.

158.4.5 PMD lane by lane signal detect function

Various implementations of the Signal Detect function are permitted by this standard. When the MDIO isimplemented, each PMD_signal_detect_n, where n represents the lane number in the range 0:3, shall be con-tinuously set in response to the magnitude of the optical signal on its associated lane, according to therequirements of Table 158–4.

158.4.6 PMD reset function

If the MDIO interface is implemented, and if PMD_reset is asserted, the PMD shall be reset as defined in45.2.1.1.1.

158.4.7 PMD global transmit disable function

The PMD_global_transmit_disable function is optional and allows all of the optical transmitters to bedisabled.

a) When a PMD_global_transmit_disable variable is set to ONE, this function shall turn off all of theoptical transmitters so that the each transmitter meets the requirements of the average launch powerof the OFF transmitter in Table 158–7 or Table 158–11.

b) If a PMD_fault is detected, then the PMD may set the PMD_global_transmit_disable to ONE,turning off the optical transmitter in each lane.

158.4.8 PMD lane by lane transmit disable function

The PMD_transmit_disable_n (where n represents the lane number in the range 0:3) function is optional andallows the optical transmitters in each lane to be selectively disabled.

a) When a PMD_transmit_disable_n variable is set to ONE, this function shall turn off the opticaltransmitter associated with that variable so that the transmitter meets the requirements of the averagelaunch power of the OFF transmitter in Table 158–7 or Table 158–11.

b) If a PMD_fault is detected, then the PMD may set each PMD_transmit_disable_n to ONE, turningoff the optical transmitter in each lane.

If the optional PMD_transmit_disable_n function is not implemented in MDIO, an alternative method shallbe provided to independently disable each transmit lane for testing purposes.

158.4.9 PMD fault function

If the MDIO is implemented, and the PMD has detected a local fault on any of the transmit or receive paths,the PMD shall set PMD_fault to ONE.

158.4.10 PMD transmit fault function (optional)

If the MDIO is implemented, and the PMD has detected a local fault on any transmit lane, the PMD shall setthe PMD_transmit_fault variable to ONE.


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158.4.11 PMD receive fault function (optional)

If the MDIO is implemented, and the PMD has detected a local fault on any receive lane, the PMD shall setthe PMD_receive_fault variable to ONE.

158.5 Wavelength-division-multiplexed lane assignments

The wavelength range for each lane of the 100GBASE–LR4 and 100GBASE–ER4 PMDs shall be asdefined in Table 158–5. The center frequencies are members of the frequency grid for 100 GHz spacing andabove defined in ITU-T G.694.1 and are spaced at 800 GHz.

NOTE—There is no requirement to modulate a particular electrical lane on to a particular optical lane, as the PCS iscapable of receiving with the lanes in any arrangement.

158.6 PMD to MDI optical specifications for 100GBASE–LR4

The operating range for the 100GBASE–LR4 PMD is defined in Table 158–6. A 100GBASE–LR4 compli-ant PMD operates on type B1.1 and type B1.3 single-mode fibers according to the specifications defined inTable 158–17. A PMD which exceeds the operational range requirement while meeting all other opticalspecifications is considered compliant (e.g., operating at 12.5 km meets the minimum range requirement of2 m to 10 km).

158.6.1 100GBASE–LR4 transmitter optical specifications

The 100GBASE–LR4 transmitter shall meet the specifications defined in Table 158–7 per the definitions in158.8.

Table 158–5—Wavelength-division-multiplexed lane assignments

Lane Center frequency Center wavelength Wavelength range

L0 231.4 THz 1295.56 nm 1294.53 to 1296.59 nm

L1 230.6 THz 1300.05 nm 1299.02 to 1301.09 nm

L2 229.8 THz 1304.58 nm 1303.54 to 1305.63 nm

L3 229.0 THz 1309.14 nm 1308.09 to 1310.19 nm

Table 158–6—100GBASE–LR4 operating range

PMD Type Minimum range

100GBASE–LR4 2 m to 10 km


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[Editor’s note (to be removed prior to publication) - The values of 2.2 dB for “Transmitter and dispersionpenalty per lane (max)” in Table 158–7 and 2.2 dB for “Allocation for penalties” in Table 158–9 are place-holders. The final value is expected to be between 1.8 and 2.5 dB ]

[Editor’s note (to be removed prior to publication) - The adopted baseline for 100GBASE-LR4 inanslow_01_0708.pdf had a value of 3.2 dBm for OMA per lane (max). This value was incorrectly reducedfrom the value of 4.0 dBm proposed in cole_01_0708.pdf because of the change to the use of a TDP method-ology. Consequently, this draft retains the value of 4.0 dBm propoosed in cole_01_0708.pdf]

Table 158–7—100GBASE-LR4 transmit characteristics

Description 100GBASE–LR4 Unit

Signaling speed per lane (range) 25.78125 ± 100 ppm GBd

Lane wavelengths (range) 1294.53 to 1296.591299.02 to 1301.091303.54 to 1305.631308.09 to 1310.19

nm

Side-mode suppression ratio (SMSR), (min) 30 dB

Total average launch power (max) 10.0 dBm

Average launch power per lane (max) 4.0 dBm

Average launch power per lanea (min) –3.8 dBm

Optical Modulation Amplitude (OMA), each lane (max) 4.0 dBm

Launch power per lane (min) in OMA minus TDPb –1.8 dBm

Optical Modulation Amplitude (OMA), each lane (min) –0.8 dBm

Transmitter and dispersion penalty, each lane (max) 2.2 (See editors note) dB

Average launch power of OFF transmitter, each lane (max) –30 dBm

Extinction ratio (min) 4.0 dB

RIN12OMA (max) –132 dB/Hz

Optical return loss tolerance (max) 12 dB

Transmitter reflectancec (max) –12 dB

Transmitter eye mask definition {X1, X2, X3, Y1, Y2, Y3} TBD

aAverage launch power per lane (min) is informative and not the principal indicator of signal strength. Atransmitter with launch power below this value cannot be compliant; however, a value above this does notensure compliance.

bTDP is transmitter and dispersion penalty, see 158.8.5.cTransmitter reflectance is defined looking into the transmitter.


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158.6.2 100GBASE–LR4 receive optical specifications

The 100GBASE–LR4 receiver shall meet the specifications defined in Table 158–8 per the definitions in158.8.

158.6.3 100GBASE–LR4 link power budget (informative)

An illustrative power budget and penalties for 100GBASE–LR4 channels are shown in Table 158–9.

Table 158–8—100GBASE–LR4 receive characteristics

Description 100GBASE–LR4 Unit



nm

Receive power, per lane (OMA) (max) 4.0 dBm

Average receive power, per lane (max) 4.0 dBm

Damage thresholda

aThe receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal havingthis average power level.

5.0 dBm

Average receive power, per laneb (min)

bAverage receive power per lane (min) is informative and not the principal indicator of signal strength. Areceived power below this value cannot be compliant; however, a value above this does not ensure compli-ance.

–10.1 dBm

Receiver reflectance (min) –26 dB

Receiver sensitivity (OMA), per lane (max) –8.1 dBm

Stressed receiver sensitivity (OMA), per lanec

cMeasured with conformance test signal at TP3 (see 158.8.10) for BER = 10–12.

–6.3 dBm

Vertical eye closure penalty,d per lane

dVertical eye closure penalty is a test condition for measuring stressed receive sensitivity. It is not a requiredcharacteristic of the receiver.

1.8 dB

Receive electrical 3 dB upper cutoff frequency, per lane (max) 31 GHz


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158.7 PMD to MDI optical specifications for 100GBASE–ER4

The operating range for the 100GBASE–ER4 PMD is defined in Table 158–10. A 100GBASE–ER4 compli-ant PMD operates on type B1.1 and type B1.3 single-mode fibers according to the specifications defined inTable 158–17. A PMD which exceeds the operational range requirement while meeting all other opticalspecifications is considered compliant (e.g., operating at 42.5 km meets the minimum range requirement of2 m to 30 km).

158.7.1 100GBASE–ER4 transmitter optical specifications

The 100GBASE–ER4 transmitter shall meet the specifications defined in Table 158–11 per the definitions in158.8.

Table 158–9—100GBASE–LR4 link power budget

Parameter 100GBASE-LR4 Unit

Power budget 8.5 dB

Operating distance 10 km

Channel insertion lossa 6.3 dB

Maximum discrete reflectance –26 dB

Allocation for penaltiesb 2.2 (See editors note) dB

Additional insertion loss allowed 0.0 dB

aThe channel insertion loss is calculated using the maximum distance specified in Table 158–6 and fiber attenuation of0.43 dB/km at 1295 nm plus an allocation for connection and splice loss given in 158.13.2.1.

bLink penalties are used for link budget calculations. They are not requirements and are not meant to be tested.

Table 158–10—100GBASE–ER4 operating range

PMD Type Minimum range

100GBASE–ER42 m to 30 km

2 m to 40 kma

aLinks longer than 30 km for the same link power budget are considered engineeredlinks. Attenuation for such links needs to be less than the worst case specified for B1.1or B1.3 single-mode fiber.


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158.7.2 100GBASE–ER4 receive optical specifications

The 100GBASE–ER4 receiver shall meet the specifications defined in Table 158–12 per the definitions in158.8.

Table 158–11—100GBASE–ER4 transmit characteristics

Description 100GBASE–ER4 Unit



nm

Side-mode suppression ratio (SMSR), (min) 30 dB

Total average launch power (max) 8.4 dBm

Difference in launch power between any two lanes (max) 3.0 dB

Average launch power per lane (max) 2.4 dBm

Average launch power per lanea (min) –2.9 dBm

Optical Modulation Amplitude (OMA), each lane (max) 4.0 dBm

Optical Modulation Amplitude (OMA), each lane (min) 0.1 dBm

Average launch power of OFF transmitter, each lane (max) –30 dBm

Extinction ratio (min) 8.0 dB

RIN12OMA (max) –132 dB/Hz

Optical return loss tolerance (max) 12 dB

Transmitter reflectanceb (max) –12 dB

Transmitter eye mask definition {X1, X2, X3, Y1, Y2, Y3} TBD

aAverage launch power per lane (min) is informative and not the principal indicator of signal strength. Atransmitter with launch power below this value cannot be compliant; however, a value above this does notensure compliance.

bTransmitter reflectance is defined looking into the transmitter.


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158.7.3 100GBASE–ER4 link power budget (informative)

An illustrative power budget and penalties for 100GBASE–ER4 channels are shown in Table 158–13.

Table 158–12—100GBASE–ER4 receive characteristics

Description 100GBASE–ER4 Unit



nm

Receive power, per lane (OMA) (max) 4.0 dBm

Difference in receive power between any two lanes (max) 4.0 dB

Average receive power, per lane (max) 4.0 dBm

Damage thresholda 5.0 dBm

Average receive power, per laneb (min) –20.9 dBm

Receiver reflectance (min) –26 dB

Receiver sensitivity (OMA), per lane (max) –21.4 dBm

Stressed receiver sensitivity (OMA), per lanec –17.9 dBm

Vertical eye closure penalty,d per lane 3.5 dB

Receive electrical 3 dB upper cutoff frequency, per lane (max) 31 GHz

aThe receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal havingthis average power level.

bAverage receive power per lane (min) is informative and not the principal indicator of signal strength. A re-ceived power below this value cannot be compliant; however, a value above this does not ensure compliance.

cMeasured with conformance test signal at TP3 (see 158.8.10) for BER = 10–12.dVertical eye closure penalty is a test condition for measuring stressed receive sensitivity. It is not a required

characteristic of the receiver.


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158.8 Definition of optical parameters and measurement methods

All optical measurements shall be made through a short patch cable, between 2 m and 5 m in length unlessotherwise specified.

158.8.1 Test patterns for optical parameters

Compliance is to be achieved in normal operation. Table 158–14 gives the test patterns to be used in eachmeasurement, unless otherwise specified, and also lists references to the subclauses in which each parameteris defined. The test patterns include TBD, defined in TBD

[Editor’s note (to be removed prior to publication) - Pointers to existing test patterns or definition of newpatterns to be included here]

NOTE—TBD test patterns are designed to emulate system operation; however, they do not form valid 100GBASE–Rsignals..

158.8.2 Wavelength

The wavelength of each optical lane shall be within the ranges given in Table 158–5 if measured per TIA/EIA–455–127. An optical spectrum analyzer (OSA) or equivalent instrument is used, with the resolutionbandwidth of TBD, and the lane under test is modulated using a valid 100GBASE–R signal.

158.8.3 Average optical power

The average optical power of each lane shall be within the limits given in Table 158–7 for 100GBASE–LR4or Table 158–11 for 100GBASE–ER4 if measured using the methods given in TIA/EIA–455–95, with thesum of the optical power from all of the laness not under test below –30 dBm, per the test set-up inFigure 53–6.

158.8.4 Optical Modulation Amplitude (OMA)

OMA is as defined in 52.9.5 with the exception that each lane may be tested individually with the sum of theoptical power from all of the lanes not under test being below –30 dBm, or if other lanes are operating, asuitable optical filter may be used to separate the lane under test.

Table 158–13—100GBASE–ER4 link power budget

Parameter 100GBASE–ER4 Unit

Power budget 21.5 dB

Operating distance 30 40a km

Channel insertion loss 15 18 dB

Maximum discrete reflectance –26 –26 dB

Allocation for penaltiesb 3.5 3.5 dB

Additional insertion loss allowed 3.0 0.0 dBaLinks longer than 30 km are considered engineered links. Attenuation for such links needs to be less

than the worst case for B1.1 or B1.3 single-mode fiberbLink penalties are used for link budget calculations. They are not requirements and are not meant to be

tested.


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158.8.5 Transmitter and dispersion penalty (TDP)

Transmitter and dispersion penalty (TDP) is as defined in 52.9.10 with the exception that each optical lane istested individually using an optical filter to separate the lane under test from the others. The measurementprocedure for 100GBASE–LR4 and 100GBASE–ER4 is detailed in 158.8.5.1 to 158.8.5.4.

[Editor’s note (to be removed prior to publication) - An optical filter is used here to ensure that the trans-mitter operates with realistic electrical crosstalk. Is there a need to specify the performance of the opticalfilter? In a similar application in Annex B of G.959.1 the filter ripple is limited to 0.5 dB and the isolation ischosen such that the ratio of the power in the lane being measured to the sum of the powers of all of theother lanes is greater than 20 dB ]

158.8.5.1 Reference transmitter requirements

The reference transmitter is a high-quality instrument-grade device, which can be implemented by a CWlaser modulated by a high-performance modulator. It should meet the following basic requirements:

a) The rise/fall times should be less than TBD ps at 20% to 80%.b) The output optical eye is symmetric and passes the transmitter optical waveform test of 158.8.8.c) In the center 20% region of the eye, the worst case vertical eye closure penalty as defined in 52.9.9.3

is less than 0.5 dB.d) Jitter less than 0.20 UI peak-peak.e) RIN should be minimized to less than –TBD dB/Hz

Table 158–14—Test-pattern definitions and related subclauses

Parameter Pattern Related subclause

Wavelength TBD 158.8.2

Side mode suppression ratio TBD —

Average optical power TBD 158.8.3

Optical modulation amplitude (OMA) Square 158.8.4

Transmitter and dispersion penalty (TDP) TBD 158.8.5

Extinction ratio TBD 158.8.6

RINxOMA Square 158.8.7

Transmitter optical waveform TBD 158.8.8

Stressed receiver sensitivity TBD 158.8.11

Calibration of OMA for receiver tests TBD

Vertical eye closure penalty calibration TBD

Receive upper cutoff frequency TBD 158.8.12


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158.8.5.2 Channel requirements

The transmitter is tested using an optical channel that meets the requirements listed in Table 158–15.

A 100GBASE–LR4 or 100GBASE–ER4 transmitter is to be compliant with a total dispersion at least asnegative as the “minimum dispersion” and at least as positive as the “maximum dispersion” columns speci-fied in Table 158–15 for the wavelength of the device under test. This may be achieved with channels con-sisting of fibers with lengths chosen to meet the dispersion requirements.

To verify that the fiber has the correct amount of dispersion, the measurement method defined in ANSI/TIA/EIA–455–175A–92 may be used. The measurement is made in the linear power regime of the fiber.

The channel provides a maximum optical return loss specified in Table 158–15. The state of polarization ofthe back reflection is adjusted to create the greatest RIN.

158.8.5.3 Reference receiver requirements

The reference receiver should have the bandwidth given in 158.8.8. The sensitivity of the reference receivershould be limited by Gaussian noise. The receiver should have minimal threshold offset, deadband, hystere-sis, baseline wander, deterministic jitter or other distortions. Decision sampling should be instantaneouswith minimal uncertainty and setup/hold properties.

The nominal sensitivity of the reference receiver, S, is measured in OMA using the set up of Figure 52–12without the test fiber and with the transversal filter removed. The sensitivity S must be corrected for any sig-nificant reference transmitter impairments including any vertical eye closure. It should be measured whilesampling at the eye center or corrected for off-center sampling. It is calibrated at the wavelength of the trans-mitter under test.

For all transmitter and dispersion penalty measurements, determination of the center of the eye is required.Center of the eye is defined as the time halfway between the left and right sampling points within the eyewhere the measured BER is greater than or equal to 1 × 10–3.

The clock recovery unit (CRU) used in the TDP measurement has a corner frequency of less than or equal to10 MHz and a slope of 20 dB/decade. When using a clock recovery unit as a clock for BER measurements,passing of low-frequency jitter from the data to the clock removes this low-frequency jitter from themeasurement.

Table 158–15—Transmitter compliance channel specifications

PMD typeDispersiona (ps/nm)

aThe dispersion is measured for the wavelength of the device under test (λ in nm). The coefficient assumes 10 km for100GBASE–LR4 and 40 km for 100GBASE–ER4.

Insertion lossb

bThere is no intent to stress the sensitivity of the BERT’s optical receiver.

Optical return lossc (max)

cThe optical return loss is applied at TP2.

Minimum Maximum

100GBASE–LR4 0.2325 . λ . [1 – (1324 / λ)4] 0.2325 . λ . [1 – (1300 / λ)4] Minimum 12 dB

100GBASE–ER4 0.93 . λ . [1 – (1324 / λ)4] 0.93 . λ . [1 – (1300 / λ)4] Minimum 12 dB


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158.8.5.4 Test procedure

The test procedure is as defined in 52.9.10.4 with the exception that all lanes are operational in both direc-tions (transmit and receive), and each lane is tested individually using an optical filter to sererate the laneunder test from the others.

158.8.6 Extinction ratio

The extinction ratio of each lane shall be within the limits given in Table 158–7 for 100GBASE–LR4 orTable 158–11 for 100GBASE–ER4 if measured using the methods specified in IEC 61280–2–2, with thesum of the optical power from all of the lanes not under test below –30 dBm. The extinction ratio is mea-sured using TBD test pattern or a valid 100GBASE–R signal.

NOTE—Extinction ratio and OMA are defined with different test patterns (see Table 158–14)

158.8.7 Relative Intensity Noise (RIN12OMA)

The RIN measurement methodology is defined in 52.9.6 with the exception that each lane may be testedindividually with the sum of the optical power from all of the lanes not under test being below –30 dBm, orif other lanes are operating, a suitable optical filter may be used to separate the lane under test. Also, theupper –3 dB limit of the measurement apparatus is to be approximately equal to the signaling rate (i.e.,25.8 GHz).

158.8.8 Transmitter optical waveform (transmit eye)

[Editor’s note (to be removed prior to publication) - Details of the transmit eye mask measurement to beincluded here. This is being studied by the Statistical Eye Ad HocNote: clause 158.8.5.3 refers to this clause for its reference receiver bandwidth requirement. Dependingupon the results of the Statistical Eye Ad Hoc, this may or may not be appropriate.]

158.8.9 Transmit jitter for each lane of 100GBASE–LR4 and 100GBASE–ER4

[Editor’s note (to be removed prior to publication) - The PMD specifications for 10GBASE-LR and -ER inclause 52 do not have separate transmitter jitter requirements, but “Acceptable transmitted jitter isachieved by compliance with 52.9.7, transmitter optical waveform, and 52.9.10, transmitter and dispersionpenalty”. However, for 10GBASE-LX4 in clause 53 there is a requirement to measure BER as a function ofsampling time (see clause 53.8.1). Is this measurement needed here?]

158.8.10 Receiver sensitivity

Receiver sensitivity, which is defined for an ideal input signal, is informative and testing is not required. Ifmeasured, the test signal should have negligible impairments such as intersymbol interference (ISI), rise/falltimes, jitter and RIN. Instead, the normative requirement for receivers is stressed receiver sensitivity.

158.8.11 Stressed receiver sensitivity

Stressed receiver sensitivity shall be within the limits given in Table 158–8 for 100GBASE–LR4 orTable 158–12 for 100GBASE–ER4 if measured using the method defined in 53.9.12 and 53.9.15 with theconformance test signal at TP3 as described in 53.9.14 with added sinusoidal jitter as specified in


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Table 158–16 and the vertical eye closure penalty given in Table 158–8 for 100GBASE–LR4 orTable 158–12 for 100GBASE–ER4.

For each lane, the stressed receiver sensitivity is defined with the transmit section in operation on all fourlanes and with the receive lanes not under test in operation. TBD, or valid 100GBASE–R encoded data maybe sent from the transmit section of the receiver under test. The data being transmitted must be asynchronousto the received data.

158.8.12 Receiver 3 dB electrical upper cutoff frequency

The receiver cutoff frequency shall be within the limits given in Table 158–8 for 100GBASE–LR4 orTable 158–12 for 100GBASE–ER4 if measured as described in 52.9.11. Each optical lane is measured usingan optical signal or signals with its/their wavelength within the specified wavelength range of the lane to betested. The test may use an electrical combiner and one optical source as in 53.9.13.

158.9 Safety, installation, environment, and labeling


All equipment subject to this clause shall conform to IEC 60950-1.

158.9.2 Laser safety

100GBASE–LR4 and 100GBASE–ER4 optical transceivers shall conform to Class 1 laser requirements asdefined in IEC 60825–1 and IEC 60825–2, under any condition of operation. This includes single fault con-ditions whether coupled into a fiber or out of an open bore.

Conformance to additional laser safety standards may be required for operation within specific geographicregions.

Laser safety standards and regulations require that the manufacturer of a laser product provide informationabout the product’s laser, safety features, labeling, use, maintenance, and service. This documentationexplicitly defines requirements and usage restrictions on the host system necessary to meet these safetycertifications.16

158.9.3 Installation

It is recommended that proper installation practices, as defined by applicable local codes and regulation, befollowed in every instance in which such practices are applicable.

Table 158–16—Applied sinusoidal jitter

Frequency range Sinusoidal jitter (UI pk to pk)

f < TBD kHz Not specified

TBD kHz < f ≤ TBD MHz TBD

TBD MHz < f < 10 LBa

aLB = loop bandwidth; Upper frequency bound for added sine jitter should be at least 10 times the loop bandwidth ofthe receiver being tested.

TBD

16A host system that fails to meet the manufacturers requirements and/or usage restrictions may emit laser radiation in excess of thesafety limits of one or more safety standards. In such a case, the host manufacturer is required to obtain its own laser safety certification.


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158.10 Environment

Normative specifications in this clause shall be met by a system integrating a 100GBASE–LR4 or100GBASE–ER4 PMD over the life of the product while the product operates within the manufacturer’srange of environmental, power, and other specifications.

It is recommended that manufacturers indicate in the literature associated with the PHY the operating envi-ronmental conditions to facilitate selection, installation, and maintenance.

It is recommended that manufacturers indicate, in the literature associated with the components of theoptical link, the distance and operating environmental conditions over which the specifications of this clausewill be met.

158.10.1 Electromagnetic emission

A system integrating a 100GBASE–LR4 or 100GBASE–ER4 PMD shall comply with applicable local andnational codes for the limitation of electromagnetic interference.

158.10.2 Temperature, humidity, and handling

The optical link is expected to operate over a reasonable range of environmental conditions related to tem-perature, humidity, and physical handling (such as shock and vibration). Specific requirements and valuesfor these parameters are considered to be beyond the scope of this standard.

158.11 PMD labeling requirements

It is recommended that each PHY (and supporting documentation) be labeled in a manner visible to the user,with at least the applicable safety warnings and the applicable port type designation (e.g.,100GBASE–LR4).

Labeling requirements for Class 1 lasers are given in the laser safety standards referenced in 158.9.2.

158.12 Fiber optic cabling model

The fiber optic cabling model is shown in Figure 158–3.

The channel insertion loss is given in Table 158–17. A channel may contain additional connectors as long asthe optical characteristics of the channel, such as attenuation, dispersion, reflections and polarization modedispersion meet the specifications. Insertion loss measurements of installed fiber cables are made in accor-dance with ANSI/TIA/EIA–526–7/method A–1. The fiber optic cabling model (channel) defined here is thesame as a simplex fiber optic link segment. The term channel is used here for consistency with genericcabling standards.

PMDConnectionConnectionPMD

Fiber optic cabling (channel)

Figure 158–3—Fiber optic cabling model

Patchcord

PatchcordLink

MDI MDI


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158.13 Characteristics of the fiber optic cabling (channel)

The 100GBASE–LR4 and 100GBASE–ER4 fiber optic cabling shall meet the specifications defined inTable 158–17. The fiber optic cabling consists of one or more sections of fiber optic cable and any interme-diate connections required to connect sections together.

158.13.1 Optical fiber and cable

The fiber optic cable requirements are satisfied by type B1.1 (dispersion un-shifted single-mode) and typeB1.3 (low water peak single-mode) fibers specified in IEC 60793-2 and the requirements in Table 158–18where they differ.

Table 158–17—Fiber optic cabling (channel) characteristics

Description 100GBASE–LR4 100GBASE–ER4 Unit

Operating distance (max) 10 30 40 km

Channel insertion lossa (max) 6.3 18 18 dB

Channel insertion loss (min) 0 0 dB

Positive dispersion (max) 9.5 28 36 ps/nm

Negative dispersion (min) –28.5 –85 –114 ps/nm

DGD_maxb TBD TBD TBD ps

Optical return loss TBD TBD TBD dB

aThese channel insertion loss values include cable, connectors, and splices.bDifferential Group Delay (DGD) is the time difference at reception between the fractions of a pulse that were transmit-

ted in the two principal states of polarization of an optical signal. DGD_max is the maximum differential group delaythat the system must tolerate.

Table 158–18—Optical fiber and cable characteristics

Description Type B1.1, B1.3 SMF Unit

Nominal fiber specification wavelength 1310 nm

Fiber cable attenuation (max) 0.43a or 0.5b

aThe 0.43 dB/km at 1295 nm attenuation for optical fiber cables is derived from Appendix I of ITU-T G.695.bThe 0.5 dB/km attenuation is provided for Outside Plant cable as defined in ANSI/TIA/EIA 568-B.3-2000.

Using 0.5 dB/km may not support operation at 10 km for 100GBASE–LR4 or 40 km for100GBASE–ER4.

dB/km

Zero dispersion wavelength (λ0) 1300 < λ0 < 1324 nm

Dispersion slope (max) (S0) 0.093 ps/nm2 km


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158.13.2 Optical fiber connection

An optical fiber connection, as shown in Figure 158–3, consists of a mated pair of optical connectors.

158.13.2.1 Connection insertion loss

The maximum link distances for single-mode fiber are calculated based on an allocation of 2.0 dB total con-nection and splice loss. For example, this allocation supports four connections with an average insertion lossper connection of 0.5 dB. Connections with different loss characteristics may be used provided the require-ments of Table 158–17 and Table 158–18 are met.

158.13.2.2 Maximum discrete reflectance

The maximum discrete reflectance shall be less than –26 dB.

158.13.3 Medium Dependent Interface (MDI) requirements

The 100GBASE–LR4 or 100GBASE–ER4 PMD is coupled to the fiber optic cabling at the MDI. The MDIis the interface between the PMD and the “fiber optic cabling” (as shown in Figure 158–3). Examples of anMDI include the following:

a) Connectorized fiber pigtail;b) PMD receptacle.

When the MDI is a connector plug and receptacle connection, it shall meet the interface performance speci-fications of IEC 61753-1-1 and IEC 61753-021-2

NOTE—Compliance testing is performed at TP2 and TP3 as defined in 158.4.1, not at the MDI.


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158.14 Protocol implementation conformance statement (PICS) proforma for Clause 158, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER417


The supplier of a protocol implementation that is claimed to conform to Clause 158, Physical MediumDependent sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4, shall complete the follow-ing protocol implementation conformance statement (PICS) proforma.






Supplier1




NOTES




Identification of protocol standard IEEE Std 802.3ba-20xx, Clause 158, Physical Medium Dependent sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4



Date of Statement


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[Editor’s note (to be removed prior to publication) - The PICS to be inserted here.]


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Annex A

(informative)

Bibliography

[Editor’s note (to be removed prior to publication) - Insert new informative references to this annex]

Change B8 as follows, and rearrange in alphbetical order:

[B8] ANSI/EIA/TIA 455-127-A-19912006 (FOTP-127-A), Basic Spectral Characterization of MultimodeLasers Diodes.

Insert the following references in alphabetical order and renumber the list

[Bx1] FC-PI-4 Fibre Channel — Physical Interface-4 draft 8.00 dated 21 May, 2008 .

[Bx2] SFF-8431Enhanced 8.5 and 10 Gigabit Small Form Factor Pluggable Module “SFP+” draft 3.0 dated8 May, 2008


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NOTE—This annex is numbered in correspondence to its associated clause; i.e., Annex 4A corresponds to Clause 4.

Annex 4A

(normative)

Simplified full duplex media access control

This annex is based on the Clause 4 MAC, with simplifications for use in networks that do not require thehalf duplex operational mode. Additional functionality is included for managing Physical Layer congestionand for support of interframe spacing outside this sublayer. This annex stands alone and does not rely oninformation within Clause 4 to be implemented.

4A.4.2 MAC parameters

Insert the following note below Table 4A-2 for 40 Gb/s and 100Gb/s MAC data rates, and renumber notesas appropriate:

NOTE 4—For 40 and 100 Gb/s operation, the spacing between two packets, from the last bit of the FCS field of the firstpacket to the first bit of the Preamble of the second packet, can have a minimum value of 8 BT (bit times), as measuredat the XLGMII or CGMII receive signals at the DTE. This interPacketGap shrinkage may be caused by variable networkdelays and clock tolerances.

.

WARNING

Any deviation from the above specified values may affect proper operation of the network.


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Annex 30A

(normative)

GDMO specification for IEEE 802.3 managed object classes

[Editor’s note (to be removed prior to publication) - Annex 30A and Annex 30B updates will be theresponsibility of the ongoing MIB Task Force.]


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Annex 30B

(normative)

GDMO and ASN.1 definitions for management

30B.2 ASN.1 module for CSMA/CD managed objects

[Editor’s note (to be removed prior to publication) - Annex 30A and Annex 30B updates will be theresponsibility of the ongoing MIB Task Force.]


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Annex 69A

(normative)

Interference tolerance testing

69A.2.1 Pattern generator


For 10GBASE-KR and 40GBASE-KR4, the peak-to-peak amplitude delivered by the pattern generator, asmeasured on a sequence of alternating ones and zeros, shall be no more than 800 mV, adjusted by a gain bTCas defined in 69A.2.2, regardless of equalization setting.

69A.3 Test methodology

Change last paragraph as follows:

The interference tolerence test parameters are specified in Table 70-7 for 1000BASE-KX, in Table 71-7 for10GBASE-KX4, and in Table 72-10 for 10GBASE-KR and 40GBASE-KR4.


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Annex 69B

(informative)

Interconnect characteristics

69B.4.1 Overview

Change Table 69B-1 as follows:

69B.4.3 Insertion loss

Change Figure 69B-5 as follows:

Table 69B–1—Insertion loss parameters

Parameter 1000BASE-KX 10GBASE-KX4 10GBASE-KR40GBASE-KR4 Units

fmin 0.05 GHz

fmax 15.00 GHz

b1 2.00 × 10-5

b2 1.10 × 10-10

b3 3.20 × 10-20

b4 –1.20 × 10-30

f1 0.125 0.312 1.000 GHz

f2 1.250 3.125 6.000 GHz

fa 0.100 0.100 0.100 GHz

fb 1.250 3.125 5.15625 GHz


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69B.4.4 Insertion loss deviation


Figure 69B–5—Insertion loss limit for 10GBASE-KR and 40GBASE-KR4

0 1000 2000 3000 4000 5000 6000

0

5

10

15

20

25

30

35

40

Fitte

d at

tenu

atio

n (d

B)

Frequency (MHz)

1000BASE-KX

10GBASE-KX4

10GBASE-KR / 40GBASE-KR4

HIGH CONFIDENCEREGION


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69B.4.5 Return loss


Figure 69B–6—Insertion loss deviation limits

0 1000 2000 3000 4000 5000 6000-10

-8

-6

-4

-2

0

2

4

6

8

10

Inse

rtion

loss

dev

iatio

n (d

B)

Frequency (MHz)

1000BASE-KX

10GBASE-KX4




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69B.4.6.4 Insertion loss to crosstalk ratio (ICR)


Figure 69B–7—Return loss limit

50 100 1000 100000

2

4

6

8

10

12

14

16

Ret

urn

loss

(dB

)

Frequency (MHz)

1000BASE-KX

10GBASE-KX4




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Figure 69B–8—Insertion loss to crosstalk ratio limit

100 1000 100000

10

20

30

40

50

60

Inse

rtion

loss

to c

ross

talk

ratio

(dB

)

Frequency (MHz)

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10GBASE-KX4




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NOTE—This annex is numbered in correspondence to its associated clause; i.e., Annex 153A corresponds toClause 153.

Annex 153A

(normative)

40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI)

153A.1 Overview

This annex defines the functional and electrical characteristics for the optional 40 Gb/s Attachment UnitInterface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI). Figure 153A–1 shows the relationshipsof the XLGMII, PMA, XLAUI, and PMD for 40 Gb/s and CGMII, PMA, CAUI, and PMD for 100 Gb/s.

Figure 153A–1—40 Gb/s and 100 Gb/s attachment unit interface relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model and IEEE 802.3

CSMA/CD LAN model

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSIREFERENCE

MODELLAYERS

LAN CSMA/CD LAYERS

HIGHER LAYERS




MEDIUM

XLGMII

40GBASE-R PCS

PMA

PMA

RECONCILIATION

XLAUI

MEDIUM

CGMII

100GBASE-R PCS

PMA

PMACAUI

PMD PMD


ATTACHMENT UNIT INTERFACE:CAUI = 100 Gb/s ATTACHMENT UNIT INTERFACEXLAUI = 40 Gb/s ATTACHMENT UNIT INTERFACE



PHYPHY


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The purpose of the XLAUI or CAUI is to provide a flexible chip-to-chip interconnect for discrete 40 Gb/s or100 Gb/s components respectively. An example application of CAUI includes providing a physical connec-tion between a ten-lane 100 Gb/s PMA and 10:4 PMA mapping element. An example application of XLAUIincludes providing lane extension for interfacing MAC and PHY components in a 40 Gb/s Ethernet systemdistributed across a circuit board.

The optional XLAUI/CAUI interface has the following characteristics:

a) Simple signal mapping to the XLGMII/CGMII;b) Independent transmit and receive data paths;c) Four lanes conveying the XLGMII data, or ten lanes conveying the CGMII data;d) Differential AC-coupled signaling with low voltage swing;e) Self-timed interface allows timing control at higher layers;f) Shared technology with other 40 Gb/s or 100 Gb/s interfaces;g) Shared functionality with other 40 Gb/s or 100 Gb/s ethernet blocks;h) Utilization of 64B/66B coding.

153A.1.1 Summary of major concepts

The following is a list of the major concepts of XLAUI and CAUI:

a) The optional XLAUI/CAUI interface can be inserted between layers in the IEEE 802.3 CSMA/CD LANmodel to transparently enable chip-to-chip communication;b) The XLAUI is organized into four lanes, the CAUI is organized into ten lanesc) The XLAUI/CAUI interface is a parallel electrical interface with each lane running at a nominal rate of10.3125 Gb/s

153A.1.2 Application

The application of the optional XLAUI/CAUI is primarily intended as a chip-to-chip (integrated circuit tointegrated circuit) interface implemented with traces and potentially one connector on a printed circuitboard. The XLAUI/CAUI allows interconnect distances of approximately 25 cm.

153A.1.3 Rate of operation

The XLAUI interface supports the 40 Gb/s data rate of the XLGMII. The CAUI interface supports the 100 Gb/s data rate of the CGMII. For 40 Gb/s applications, the data stream is converted into four lanes at thechip interface. For 100 Gb/s applications, the data stream is converted into ten lanes at the chip interface.The data is 64B/66B coded, resulting in a nominal rate of 10.3125 Gb/s for each lane in both 40 Gb/s and100 Gb/s applications.

153A.2 XLAUI / CAUI link block diagram

Editor’s note: (to be removed prior to publication) - Include definition of XLAUI, CAUI ling block dia-gram, test points and channel boundaries in this section]

XLAUI / CAUI link is illustrated in Figure 153A–2.


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153A.2.1 Definition of transmit test points

[Editor’s note: (to be removed prior to publication) - Insert or change, to include definition of transmittest points]

153A.2.2 Definition of receive test points

[Editor’s note: (to be removed prior to publication) - Insert or change, to include definition of receive testpoints]

Figure 153A–2—Definition of transmit and receive test points

153A.3. XLAUI/CAUI electrical characteristics

The electrical characteristics of the XLAUI/CAUI interface are specified such that they can be appliedwithin a variety of 40 Gb/s Ethernet or 100 Gb/s ethernet equipment types. The electrical characteristics forXLAUI/CAUI are specified in this section. Unless specified otherwise, the electrical characteristics definedin this subclause are applicable to all valid sequences of code-groups.

153A.3.1 Signal levels

The XLAUI/CAUI is a low-swing AC-coupled differential interface. AC-coupling allows for interoperabil-ity between components operating from different supply voltages. Low-swing differential signalling pro-vides noise immunity and improved electromagnetic interference (EMI) immunity. Differential signalswings are defined in the following sections, and depend on several factors such as transmitter pre-equaliza-tion and transmission line losses.

153A.3.2 Signal paths

The XLAUI/CAUI signal paths are point-to-point connections. Each path corresponds to a XLAUI/CAUIlane, and is comprised of two complementary signals making a balanced differential pair. For XLAUI, thereare four differential paths in each direction for a total of eight pairs, or sixteen connections. For CAUI, thereare ten differential paths in each direction for a total of twenty pairs, or 40 connections. The signal paths are

XLAUI/CAUIComponent

XLAUI/CAUIComponent

XLAUI/CAUIChannel

TransmitCompliance

Point

Transmit

Compliance

ComplianceCompliance

Point

PointPoint

Receive

Receive


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intended to operate up to approximately 25 cm over controlled impedance traces on FR4 printed circuitboards (PCBs).

153A.3.3 Transmitter characteristics

The XLAUI/CAUI transmitter characteristics are summarized in Table 153A–1. The XLAUI/CAUI signal-ling speed shall be 10.3125 GBd ±100 ppm. The corresponding Baud period is nominally 96.96969697 ps.

153A.3.3.1 Output amplitude

Driver differential output amplitude shall be less than 760 mVp-p including any transmit equalization. DC-referenced logic levels are not defined since the receiver is AC-coupled. Single-ended output voltage rangeshall be between –0.4 V and 4.0 V with respect to ground. See Figure 153A–3 for an illustration of absolutedriver output voltage limits and definition of differential peak-to-peak amplitude.

Table 153A–1—Transmitter characteristics

Parameter Value Units

Signalling speed per lane (range) 10.3125 GBd +- 100 ppm GBd

Unit interval nominal 96.96969697 ps

Single-ended output voltage rangemaximumminimum

4.0–0.4

VV

Maximum Differential Output Voltage, peak-to-peak

760 mV

Maximum Termination Mismatch at 1MHz 5 %

Maximum Output AC Common Mode Volt-age, RMS

15 mV

Minimum Output Rise and Fall time (20% to 80%)

24 ps

Differential Output S-parameters (see "Equation 153A-1") dB

Common Mode Output S-parameters (see "Equation 153A-2") dB

Maximum Total Jitter 0.32 UI

Maximum Deterministic Jitter 0.17 UI

Transmitter eye mask definition X1 0.16 UI

Transmitter eye mask definition X2 0.38 UI

Transmitter eye mask definition Y1 190 mV

Transmitter eye mask definition Y2 380 mV


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153A.3.3.2 Transition time

Differential transition times greater than 24 ps are required, as measured between the 20% and 80% levels.Shorter transitions may result in excessive high-frequency components and increase EMI and crosstalk. Theupper limit is defined by the transmit eye mask.

153A.3.3.3 Differential output return loss

For frequencies from 10 MHz to 11.1 GHz, differential output S-parameters shall exceed Equation (153A-1). Differential S-parameters include contributions from on-chip circuitry, chip packaging,and any off-chip components related to the driver. This output impedance requirement applies to all validoutput levels. The reference impedance for differential return loss measurements is 100 Ω.

SDD22 = –12 dB for 10 MHz < Freq (f) < 2.125 GHz, and–6.5 + 13.33 log(f/5.5) dB for 2.125 GHz <= Freq (f) = < 11.1 GHz (153A-1)

where f is frequency in GHz.

Figure 153A–3—Driver output voltage limits and definitions[Li and Li<N> are the positive and negative sides of the

differential signal pair for lane i (i = 0, 1, 2, 3 for XLAUI. For CAUI i = 1:10)]

SLi - SLi<N>

Ground

4.0 V

–0.4 V

SLi<N>

SLi

Minimum absolute output

Maximum absolute output

Differential peak- to-peak amplitude


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Figure 153A–4—Differential output return loss

153A.3.3.4 Common mode output return loss

For frequencies from 10MHz to 11.1 GHz, differential to common mode output S-parameters shall exceedequation (153A-2). Differential S-parameters include contributions from on-chip circuitry, chip packaging,and any off-chip components related to the driver. This output impedance requirement applies to all validoutput levels. The reference impedance for differential return loss measurements is 100 Ω.

SCC22 = –9 dB for 10 MHz < Freq (f) < 2.125 GHz, and–3.5 + 13.33 log(f/5.5) dB for 2.125 GHz <= Freq (f) = < 7.1 GHz and-2 dB for 7.1 GHz < Freq (f) < 11.1 GHz (153A-2)


2

3

4

5

6

7

8

910

0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15

11

12

131415

Frequency (GHz)

Ret

urn

Loss

(dB

)


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Figure 153A–5—Common mode output return loss

153A.3.3.5 Transmitter eye mask definition

The eye templates are given in Figure 153A–7 and Table 153A–1. The template measurement requirementsare specified in 153A.4.2. The jitter requirements at the transmitter are for a maximum total jitter of 0.32 UIpeak-to-peak and a maximum deterministic component of 0.17 UI peak-to-peak. Jitter specifications includeall but 10–12 of the jitter population. The maximum random jitter is equal to the maximum total jitter minusthe actual deterministic jitter. Jitter measurement requirements are described in 153A.4.3.

1

2

3

4

5

6

7

8

9

100 1 2 3 4 5 6 7 8 9 10 11 12

Frequency (GHz)

Ret

urn

Loss

(dB

)


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153A.3.4 Receiver characteristics

Receiver characteristics are summarized in Table 153A–2 and detailed in the following subclauses.

Table 153A–2—Receiver characteristics

Parameter Value Units

Signalling speed per lane (range) 10.3125 GBd +- 100 ppm GBd

Unit interval nominal 96.96969697 ps

Minimum Differential Input Voltage, p-p See receiver eye mask definition

mV

Maximum Input AC Common Mode Voltage, RMS

20 mV

Minimum Input Rise and Fall Time (20% to 80%)

24 ps

Differential Input S-parameters (see "Equation 153A-3") dB

Differential Common Mode Input Conversion S-parameters

(see "Equation 153A-4") dB

Maximum Total Jitter 0.62 UI

Maximum non-EQ Jitter (TJ - ISI) 0.42 UI

Receiver eye mask definition X1 0.31 UI

Receiver eye mask definition X2 0.5 UI

Receiver eye mask definition Y1 45 mV

Receiver eye mask definition Y2 425 mV

Figure 153A–6—Driver template

0

–Y1

Y1

0 1-X1X1 1Time (UI)

Diff

eren

tial a

mpl

itude

(mV

)

Y2

–Y2

X2 1-X2


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153A.3.4.1 Bit error ratio

The receiver shall operate with a BER of better than 10–12 in the presence of a reference input signal asdefined in 153A.3.4.2.

153A.3.4.2 Reference input signals

Reference input signals to a XLAUI/CAUI receiver have the characteristics determined by compliantXLAUI/CAUI drivers and channel. Reference input signals satisfy the far-end template given in Figure153A–7 and Table 153A–2. The template measurement requirements are specified in 153A.4.2. Signal jitterdoes not exceed the jitter tolerance requirements specified in 153A.3.4.8.

153A.3.4.3 Input signal amplitude {Editor’s note: (to be removed prior to publication) - Insert orchange, to include input signal amplitude}

153A.3.4.4 Differential input return loss

For frequencies from 50MHz to 11.1GHz, differential input S-parameters shall exceed equation (153A-3).Differential S-parameters include contributions from on-chip circuitry, chip packaging, and any off-chipcomponents related to the receiver. The reference impedance for differential return loss measurements is 100 Ω.

SDD11 = –12 dB for 50 MHz < Freq (f) < 2.125 GHz, and–6.5 + 13.33 log(f/5.5) dB for 2.125 GHz <= Freq (f) = < 11.1 GHz (153A-3)


Figure 153A–7—Receiver template

0

–Y1

Y1

0 1-X1X1 1Time (UI)

Diff

eren

tial a

mpl

itude

(mV

)

Y2

–Y2

X2


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Figure 153A–8—Differential input return loss

153A.3.4.5 Common mode input return loss

For frequencies from 10 MHz to 11.1 GHz, differential to common mode input conversion S-parametersshall exceed equation (153A-4). Differential S-parameters include contributions from on-chip circuitry, chippackaging, and any off-chip components related to the receiver. The reference impedance for differentialreturn loss measurements is 100 Ω.

SCD11 = –15 dB for 10 MHz < Freq (f) < 11.1 GHz (153A-4)


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5

6

7

8

910

0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15

11

12

131415

Frequency (GHz)

Ret

urn

Loss

(dB

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Figure 153A–9—Differential to common mode input conversion S-parameters

153A.3.4.6 Receiver eye mask definition

The eye templates are given in Figure 153A–7 and Table 153A–2. The template measurement requirementsare specified in 153A.4.2. The jitter requirements at the receiver are 0.62 UI peak-to-peak and a maximumnon-EQ jitter of 0.42 UI peak-to-peak.

153A.3.4.7 AC-coupling

The XLAUI/CAUI receiver shall be AC-coupled to the XLAUI/CAUI transmitter to allow for maximuminteroperability between various 10 Gb/s components. AC-coupling is considered to be part of the receiverfor the purposes of this specification unless explicitly stated otherwise. It should be noted that there may bevarious methods for AC-coupling in actual implementations.

153A.3.4.8 Jitter tolerance

The XLAUI/CAUI receiver shall have a peak-to-peak total jitter amplitude tolerance of at least 0.62 UI. Thistotal jitter is composed of two components: non-EQ jitter and trace-loss jitter. Non-EQ jitter tolerance shallbe at least 0.42 UIp-p. The XLAUI/CAUI receiver shall tolerate sinusoidal jitter with any frequency andamplitude defined by the mask of Figure 153A–10. This sub-component of non-EQ jitter is intended toensure margin for low-frequency jitter, wander, noise, crosstalk and other variable system effects. Jitterspecifications include all but 10-12 of the jitter population.

3

4

5

6

7

8

910

0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15

11

12

131415

Frequency (GHz)

Ret

urn

Loss

(dB

)

16


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153A.3.5 Interconnect characteristics

The XLAUI/CAUI is primarily intended as a point-to-point interface of up to approximately 25 cm betweenintegrated circuits using controlled impedance traces on low-cost printed circuit boards (PCBs). The perfor-mance of an actual XLAUI/CAUI interconnect is highly dependent on the implementation.

153A.3.5.1 Characteristic impedance

[Editor’s note: (to be removed prior to publication) - Insert or change, to include characteristic imped-ance]

153A.4 Electrical measurement requirements

[Editor’s note: (to be removed prior to publication) - Insert or change, to include electrical measurementrequirements]

153A.4.1 Interconnect definition

[Editor’s note: (to be removed prior to publication) - Insert or change, to include interconnect definition]

(153A-5)

Figure 153A–10—Single-tone Sinusoidal Jitter Mask

Frequency

Sinusoidal jitter amplitude

5 UIp-p

0.05 UIp-p

40 kHz 4 MHz 10 Loop Bandwidth

s21 s21 limit TBD=≤


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.

153A.4.2 Eye template measurements

[Editor’s note: (to be removed prior to publication) - Insert or change, to include eye template measure-ments]

.

153A.4.3 Jitter test requirements

[Editor’s note: (to be removed prior to publication) - Insert or change, to include jitter test requirement

153A.4.3.1 Transmit jitter

[Editor’s note: (to be removed prior to publication) - Insert or change, to include transmit jitter]

Figure 153A–11—Compliance interconnect magnitude response and ISI loss

Frequency (GHz)

0

Sample compliance interconnect

|s21| (dB)

TBDTBDTBD

TBD

0

Figure 153A–12—Eye template alignment

0 UI 1 UI

Data eye

Zero crossinghistogram

Template alignment

0

+Vpk

-Vpk


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153A.4.3.2 Jitter tolerance

[Editor’s note: (to be removed prior to publication) - Insert or change, to include jitter tolerance]

153A.5. Environmental specifications

[Editor’s note: (to be removed prior to publication) - Insert or change, to include environmental specifi-cations]


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153A.6. Protocol implementation conformance statement (PICS) proforma for Annex 153A, 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI)18

[Editor’s note (to be removed prior to publication) - Insert PICS, for 40 Gb/s and 100Gb/s AttachmentUnit Interfaces]



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