978-1-4673-6361-7/13/$31.00 c⃝2013 IEEE 662

A 1-V Bulk-Driven CMOS Fully Differential Second-Generation Current Conveyor

Sopapun Suwansawang School of Electronics Engineering

Faculty of Science and Technology, Nakhon Pathom Rajabhat University

85 malaiman Rd. Nakhon Pathom 7300, Thailand. E-mail sopapun@npru.ac.th

Thawatchai Thongleam School of Electronics Engineering

Faculty of Science and Technology, Nakhon Pathom Rajabhat University

85 malaiman Rd. Nakhon Pathom 7300, Thailand. E-mail thawatchait@npru.ac.th

Abstract—A 1-V fully differential second-generation current conveyer (FDCCII) is presented in this paper. The input stage of the circuit is designed using bulk-driven transistors in order to rail-to-rail operation. To increase DC gain, the feedforward circuits technique are employed in this design. The low voltage FDCCII is verified by using HSPICE in 0.18 μm CMOS technology. The simulation results show rail-to-rail input and output swing. The experimental and result shows the fully differential voltage Y-X DC transfer characteristic and fully differential current X-Z characteristic shows linearity. Finally, the bandwidth and power dissipation are 25.7 MHz (VX/VY), 30 MHz (IZ/IX) and 403.77 μW, respectively.

Keywords—low-voltage; bulk-driven; FDCCII; CCII; feedforward technique

I. INTRODUCTION Since 1970, the second generation current conveyor

(CCII), which is current-mode analog circuit basic building block, was designed and implemented by Sedra and Smith [1]. The current-mode (CM) circuits are more advantage than voltage-mode (VM) circuits such as a large bandwidth, a wide common-mode range, and a bandwidth product independent of gain. However, the folded cascade CCII circuit is operated under high supply voltage. The CCII has been used for several applications such as current amplifier, active filter, oscillator, instrumentation, and variable gain amplifier (VGA). Nowadays, the modern VLSI technologies are being scaled down [2], while the threshold voltage is not reduced scaling. Therefore, according to Ref [3] CCII should be operated in the low supply voltage and rail-to-rail signal swing for both port VY and VX.

To achieve analog circuit operated in low supply voltage, the bulk-driven transistor and the folded cascode techniques CCII has been reported in order to increase dc-gain, and the resulting bulk driven CCII can achieve rail-to-rail and low supply voltage operation [4]. On the other hand, the transconductance of the bulk-driven is 2 to 5 times lower than the transconductance of the gate-driven CCII. As a result, the

voltage VY can’t be following to the voltage VX. In addition, the impedance at X terminal (RX) has been high resistance.

Several the current conveyor have been proposed in the differential difference current conveyor (DDCC) [5], and the differential voltage current conveyor [6]. They are not only large supply voltage operation, but also limited voltage follower rail-to-rail swing (between VY-VX). According to Ref [7], the FG-MOS current controlled current conveyor (CCCII) has been proposed to reduce the supply voltage. However, the impedance node X can’t be designed low impedance.

Recently, the fully differential CCII (FDCCII) is one of the most impotent widely used in the analog building blocks. FDCCII has been proposed in reference [8-13]. Unfortunately, the approach circuits can’t be operated in rail-to-rail signal swing. Consequently, they are not well suited for modern low supply voltage (below 1 V). This paper is organized as follows. The basic concept of FDCCII is presented in Section II. In Section III the bulk-driven CMOS FDCCII is explaining. In Section IV, the simulation results and discussions for the FDCCII are presented. Finally, conclusions are explaining.

II. FULLY DIFFERENTIAL SECOND GENERATION CURRENT CONVEYER

Fig. 1 is shows building block of low voltage CMOS FDCCII. The basic characteristics of FDCCII are high input impedance Y node (Y+ and Y-), low impedance X node (X+ and X-), and large output impedance Z node (Z+ and Z-).

Fig. 1. The Symbol of FDCCII.

663

Fig. 2. Bulk-driven CMOS FDCCII with feedforward circuit.

From figure 1, the basically of characteristic of FDCCII can be described by the following matrix equation;

0 0 01 0 00 1 0

⎡ ⎤ ⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥ ⎢ ⎥=⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥ ⎢ ⎥±⎣ ⎦ ⎣ ⎦ ⎣ ⎦

Y Y

X X

Z Z

I VV II V

(1)

where IX, IY, IZ, VX, VY, and VZ are current and voltage at nodes X, Y and Z, respectively. The six-terminal of FDCCII can be still described by Equation (1), According to Equation (1), the differential voltage and current are related in VdX = VX+-VX-, VdY = VY+-VY-, and VdZ = VZ+-VZ-, and IdX = IX+-IX-, IdY = IY+-IY-, and IdZ = IZ+-IZ-, respectively.

III. PROPOSED BULK-DRIVEN CMOS FDCCII A. Bulk-driven CMOS FDCCII

Fig. 2 shows the proposed bulk-driven CMOS FDCCII. As seen, the bulk-driven FDCCII topology is based on the high gain of FDDA connected in voltage follower configuration. The input stage of FDCCII is consists of the transistors M1a,b-M3a,b. The transistors M4a,b and M5a,b are consists to be the input current or the output voltage. The transistors M6a,b and M7a,b are consists to be the output stage. The port signals VY+(-) are input signal at bulk terminal of FDDA and transconductor (Gm). The output signals of tranconductor (Gm) (vof1a(c) and vof1b(d)) auxiliary circuit is the gate-driven transistors M1a(b) and M2a(b) (vg1a(c) and vg1b(d)). The output stage amplifier (M4a,b-M5a,b), connected in the class AB configuration [14] is employed amplify the signals at nodes vO1a and vO1b. The dc operating points are set by VB2 through the large resistors Rlarge, where the implementations of Rlarge as the PMOS transistors are operated in cutoff region. In order to op-amp stability, resistor RC1a (RC1b) and capacitor CC1a (CC1b) are used to compensation of the amplifier circuit.

Fig. 3 illustrates the transconductor (Gm), which is connected in the feedforward technique [14]. The transconductor auxiliary circuits are used to increase differential-mode gain of fully differential difference amplifier (FDDA) and suppressed common-mode input signal.

Fig. 3. Bulk-driven transconductor.

The operation of the proposed circuit can be explained as follows. When the inputs vY+ and vY− are differential signals, the signals at nodes vOF1c and vOF1a are in phase with the input signals vY+ and vY-, respectively. As a results, the current signals gmb1avY+ (gmb2bvY-) and the current signals gm2aAvFvY- (gm1bAvFvY+) are combined and passed through M1a (M2b) and M2a (M1b), where AvF = gmFb1a(b-d)RGF1a(b), thus the differential signal current are passed through RG1 and RG2. Consequently, the signal voltage at nodes vO1a and vO1b are enhanced. The voltage vO1a and vO1b are converted to current id4a(b) and id5a(b). As a result, the output signals VX are followed to the input differential signals. The port of VX is followed to VY by the negative feedback configuration. Straightforward analysis of the impedance at terminal node VX of the FDCCII in Figure 2 shows is given by

( )

( )

4 5 1 2

1 2 1 1 2 1

1

1

≈+

×+

xm a( b ) m a( b ) G ( )

mb a( b ), a( b ) mbF a( b ),c( d ) m a( b ), a( b ) GF a,b( c,d )

Rg g R

g g g R(2)

where gmb1a(b), gmb2a(b), gm1a(b), gm2a(b), gmbF1a(b), gmbF1c(d), gm4a(b), and gm5a(b) are bulk-driven transconductance and gate-driven transconductance of M1a(b,), M2a(b), M1Fa(b), M4a(b) and M5a(b), respectively. RGF1a(b), RGF1c(d) and RG1(2) are the output resistance of GmF1(2), the output resistance of FDDA, respectively.

vY +(-)

MF1a(c) MF1b(d)

VDD

VB3MC2a(b)

vX+(-)

VG

MF2a(c)

vOF1b(d)vOF1a(c)

MF2b(d)

GmF1,2

vOF1b(d)

vX +(-)

vOF1a(c)vY +(-)

RGF1a(c) RGF1b(d)

664

Continuously, when the inputs vX+ and vX− are differential current signals, the current signals are passed through at node VX. Moreover, the signals swing at node VX are amplified by the transconductor GMF. As a result, the signal voltage vg1a (vg1d) are in phase with the signal voltage vX- (vX+). The current signals gmb2avX- (gmb1bvX+) and the current signals gm1aAvFvX+ (gm2bAvFvX-) are combined and passed through RG1 and RG2. The signal voltage at nodes vO1a and vO1b are enhanced. The signal voltage at nodes vO1a and vO1b are used to pull and push the output current iOUT,Z+ and iOUT,Z-. The output current at node VZ are followed to the input differential current signals at node VX.

B. Common-mode rejection circuitry Figure 4 shows the common-mode rejection circuitry,

which is used to set dc output voltage and suppress the output common-mode signal and of the proposed FDCCII, in this case, the common-mode feedback are employed two circuits, which are connected at node VX and VZ. As seen, a bulk-driven fully differential pair was designed operation in the CMFB circuit. The common-mode detector are the bulk-driven fully differential pair (M8a(b), M8c(d), M9a(b), and M9c(d)). Therefore, the port signals VX+ (VZ+) and VX− (VZ-) are operated in rail-to-rail output swing. The common-mode signals VX+ (VZ+) and VX− (VZ-) are converted to current common-mode feedback with the bulk-driven fully differential pair. The transistor M10a(b) (M10c(d)) are connected in diode-connected transistor.

The operation of the circuit can be explained as follows. In case of differential VX+ (VZ+) and VX− (VZ-), the current signal is not flow through transistor M10a(b) (M10c(d)), the signal at node vCMFB1a(b) (vCMFB1c(d)) nearly constant. Nevertheless, when VX+ (VZ+) and VX− (VZ-) are common-mode signals, the common-mode current feedback signal is flow pass to transistor M10a(b) (M10c(d)) and M11a(b) (M11c(d)), which connected in the current mirror configuration. After that, the voltage signal is appeared at node vCMFB1a(b) (vCMFB1c(d)). In this design, the signal vCMFB1a(c) (vCMFB1b(d)) are fed back to the bulk-driven transistor M5a(b) (M5c(d)). Eventually, the common-mode signal vCMFB1a(c) (vCMFB1b(d)) and VX+ (VZ+) and VX− (VZ-) have opposite phase, the common-mode response are suppressed.

Fig. 4. Common-mode rejection circuitry [14].

IV. SIMULATION RESULTS AND DISCUSSIONS The operation of the proposed FDCCII was simulated with

HSPICE by using a 0.18 µm standard CMOS technology. The proposed circuit is operated under 1 V supply voltage. The input stage and the output stage bias current of the circuits are 10 µA and 20 µA, respectively. Fig. 5 shows DC transfer characteristic between the fully differential input voltage VY and fully differential output voltage VX. As seen, the result shows that VX follows VY. Fig. 6 shows frequency response VZ/VX of FDCCII which illustrates 0 dB DC gain and 25.7 MHz bandwidth.

Fig. 5. X-Y fully differential DC characteristic.

Fig. 6. Frequency response of output X.

The DC transfer characteristic between fully differential current IX - IZ is illustrated in Fig. 7. As seen, the result shows differential current IZ follower IX. The frequency response IZ/IX of FDCCII is shown in Fig. 8, which illustrates 0 dB DC gain and 30 MHz (-3 dB) bandwidth. The time-domain response of fully differential input voltage VY and fully differential output voltage VX of the proposed FDCCII is illustrated in Fig. 9. A 2 Vp-p sine wave at 1 MHz is applied to differential voltage VY. As seen, the result of simulation illustrates the voltage node VX are rail-to-rail operation.

vX -(Z-)vX+(Z+)

M8a(c) M8b(d)

VDD

VB4MC3a(b)

M9a(c) M9b(d)

VB4MC4a(b)

VREF

VB5

vCMFB1b(d)

VB5

vCMFB1a(c)

M11a(c) M11b(d)

M10a(c) M10b(d)

M12a(c) M12b(c)

V X(V

)

-100

-80

-60

-40

-20

0

20

Frequency [Hz]105 106 107 108 109103 104 1010 1011

665

Fig. 7. X-Z fully differential DC characteristic.

Fig. 8. Frequency response of output Z.

Fig. 9. Transient response (Input 2 Vp-p, 1 MHz).

V. CONCLUSIONS In this paper, a 1-V bulk-driven CMOS FDCCII is

presented. The proposed circuit is used bulk-driven transistors technique in order to input rail-to-rail and operate under a low supply voltage. The feedforward technique was employed to increase the open loop gain and decrease input impedance at the X terminal. The FDCCII circuit is designed using a standard 0.18 μm CMOS process and operate under 1 V supply voltage. The simulation results show differential voltage and current very linearity. The bandwidth (- 3 dB) are 25.7 MHz (VX/VZ) and 30 MHz (IZ/IX). Eventually, the power consumption is 403.77 μW.

REFERENCES [1] S. A. Smith and K. C. Smith, “A second-generation current conveyor

and its applications,” IEEE Transactions on Circuits Theory. CT-17(1). February 1970. pp. 132-134.

[2] Shouli Yan and Edgar Sanchez-Sinencio, “Low Voltage AnalogCircuit Design Techniques: A Tutorial,” IEICE Transaction on Analog Integrated Circuits and System, vol. E00-A, no. 2, February 2000, p. 1-17.

[3] V. Kasemsuwan, and W. Nakhlo, “A simple 1.5 V rail-to-rail CMOS current conveyor,” Journal of Circuits, Systems, and Computers., vol.16, No. 4, 2007, pp. 627-639.

[4] F. Khateb, N. Khatip, and D. Kubanek, “Novel low-voltage low-power high-precision CCII ± based on bulk-driven folded cascode OTA,” Microelectronic Journal. Vol. 42, 2011, pp. 622-631.

[5] W. Chiu, S. I. Liu, H. W. Tsao, and J. J. Chen, “CMOS Differential difference current conveyor and their application,” IEE Proc-Circuit Devices System., vol.143, No. 2, April 1996, pp. 91-96.

[6] F. Khateb, N. Khatip, and J. Koton, “Novel low-voltage ultra-low-DVCC based on floating-gate folded cascode OTA,” Microelectronic Journal. Vol. 42(8), 2011, pp. 1010-1017.

[7] R. Fani, and E. Farshidi, “A FG-MOS based fully differential current controlled current conveyor and its applications,” Circuits System Signal Process., November 2012, pp. 1-19.

[8] H. A. Alzaher, H. O. Elwan, and M. Ismail, “A CMOS fully balanced seond-generation current conveyor,” IEEE Trans Circuits and Systems II: Analog and digital signal processing. Vol. 50, no. 6, June. 2003, pp. 278-287.

[9] A. Lopez-Martin, J. Ramirez-Angulo, and R. G. Carvajal, “A proposal for high-performance CCII-based analogue CMOS design,” International Journal of Circuit Theory and Applications., vol. 33, May 2005, pp. 379-391.

[10] S. A. Mahamoud “New fully-differential CMOS seond-generation current conveyor,” ETRI Journal. Vol. 28, no. 4, August, 2006, pp. 495-501.

[11] S. A. Mahmoud, “Fully differential CMOS CCII based on differential difference transconductor,” Analog Integr Circ Sig Process., February 2007, pp. 195-203.

[12] E. A. Sobhy, and A. M. Soliman, “Realizations of fully differential voltage second-generation current conveyor with an application,” International Journal of Circuit Theory and Applications., vol. 38, 2010. pp. 441-452.

[13] F. Kacar, B. Metin, H. Kuntman, and O. Cicekoglu, “A new high-performance CMOS fully differetial second-generation current conveyor with application example of biquad filter realisation,” International Journal of Electronics, vol. 97, no. 5, May 2010, pp. 499-510.

[14] T. Thongleam, S. Suwansawang, and V. Kasemsuwan, “Low-voltage high gain, high CMRR and rail-to-rail bulk-driven op-amp using feedforward technique ,” The 13th International Symposium on Communications and Information Technologies (ISCIT 2013). 4-6 September. 2013.

-1000 -800 -600 -400 -200 0 200 400 600 800 1000-1000

-800

-600

-400

-200

0

200

400

600

800

1000

IX ( A)

IZ+IZ-

Gai

n [d

B]V

olta

ge (V

)