Common-Mode and Differential-Mode Loop Gains of Paralleled Buck Converters

Ming Li Department of Systems

United Technologies Research Center East Hartford, Connecticut, USA, 06108

mingli.xjtu@gmail.com

Chi Kong Tse Department of Electronic and Information Engineering

The Hong Kong Polytechnic University Hung Hom, Hong Kong, China

encktse@polyu.edu.hk

Abstract—Based on the time-domain decomposition of small-signal model in paralleled buck converters, two equivalent low-order loop gains, namely, common-mode and differential-mode loop gains, are derived to analyze and design the stability of the system with N converter modules. Specifically, the proposed loop gains are applied to two voltage-mode controlled buck converters under active current-sharing control. Experimental verification is performed to validate the effectiveness of the proposed loop gains on locating the stability boundary of design parameters.

I. INTRODUCTION Modular interaction usually exists in power electronic systems involving connections of individual converters, such as interconnected converters [1]-[5]. For paralleled dc-dc converters, since the constituent converters are not identical, a proper current-sharing control such as an active current-sharing scheme is necessarily used to prevent unbalanced currents that would be drawn from their outputs. Modular interaction in such systems, which has been shown to occur between the current sharing and voltage feedback loops, may adversely affect the system performance and even jeopardize the stability of the entire system [1]-[2]. Thottuvelil and Verghese [2] presented a general modeling approach to address the stability of paralleled dc-dc converters, which needs to consider all direct and cross-coupling transfer functions of the voltage reference to each inductor current as well as various impedances. In particular, this work conceptually categorized the system stability into common- and differential-mode stabilities. Moreover, the common-mode instability has been found primarily dependent on the voltage loop and the number of converters, and the differential-mode instability primarily on the current-sharing loop. In general, modeling approaches of power electronics converters include average model based time-domain large signal analysis [7] and frequency-domain small-signal analysis [8,9], and discrete-time model in time-domain and sample-data model in frequency-domain [10]. In particular,

small-signal model based loop gain analysis is the mainstream for engineering design, and it can be easily extended to system-level modeling and control analysis, such as DC distributed power supply [11], grid-tied converters [12] and EMI filter stability design in cascaded structure [13,14]. Therefore, the focus of modeling inter-connected converter system in this work is the small-signal model based loop gain derivation. By linearization of averaged model of paralleled converters, previous work [6] has has shown that the time-domain small-signal model of N voltage-mode controlled buck converters under master-slave and democratic schemes can be decomposed into two equivalent subsystems. Based on [6], two loop gains, which correspond to the common-mode and differential-mode stabilities, are proposed. In particular, using an equivalent standalone buck converter, an integrated model which combines the two proposed loop gains is presented for facilitating practical design.

II. PARALLLED BUCK CONVERTERS

A. Circuit Topology Fig.1 shows N paralleled buck converters under active current-sharing control. According to the inductor currents, the current-sharing bus generates a bus signal, vbus(t), i.e., vbus(t)=Rsibus(t). Specifically, ibus(t)=i1(t) for the master-slave scheme since converter 1 is pre-chosen as the master module, and ibus(t)=[i1(t)+i2(t)+…iN(t)]/N for the democratic scheme. The current-sharing loop generates a voltage signal vcsj(t) to adjust the voltage reference to achieve even current distribution. The small-signal model is illustrated in Fig.2. Clearly, converters are coupled with each other at the input, the output and the current-sharing bus. In particular, the output voltage of the compensator, ˆ( )v s , is generally represented by a linear combination of ˆ ( )ov s and ˆ ( )csv s , i.e., ˆ ˆ ˆ( ) ( ) ( ) ' ( ) ( )c o c csv s G s v s G s v s= + , where ( )cG s and

' ( )cG s are the transfer functions of linear compensators corresponding to ˆ ( )ov s and ˆ ( )csv s , respectively. Note that

978-1-4673-0803-8/12/$31.00 ©2012 IEEE 4295

detailed description of operating principle and parameter symbols can also be found in [6].

NL

1L

xNR

C R o ( )v t

( )Ni t

1( )i t1D

ramp1( )v t

1xR

1yR1( )v t

yNR

refNV

( )Nv t

DN

1H

NH

ref1V

1( )sR i t

( )s NR i t

SN

1er

ramp ( )Nv t

eNr

bus ( )v t

cs1( )v t

cs ( )Nv t

E

1S 1or

oNr

crc ( )v t

Figure 1. Circuit schemtaic of paralleled buck converters, roj is the on-resistance of switch Sj. rej is the sum of equivalent series resistance of the

inductor rlj and the sampling resistance Rs in converter j.

1L

CR oˆ ( )v s1( )i s

ˆ( )e s

1 1 1o eD r r+

1 1( )I d s

1 1 1( ) ( )oE r I d s−11: D

1( )H s

ref1ˆ ( )V s

busˆ ( )i s

cs1ˆ ( )v s

1( )cG s1( )d s

11 PV

1( )cG s′

NL

ˆ ( )N

i sN oN eND r r+

ˆ ( )N NI d s

ˆ( ) ( )oN N NE r I d s−1: ND

1( )i s

( )NH s

refˆ ( )NV s

csˆ ( )Nv s

ˆ ( )Nd s

1 PNV

( )cNG s′ˆ ( )Ni s

1( )v s

( )cNG sˆ ( )Nv s

oˆ ( )v s

oˆ ( )v s

crˆ ( )cv s

Figure 2. Small-signal model

B. Equivalent Transformation Referring to [6], the Jacobian of the small-signal model J(Xe) provides an effective means to judge the stability from the time-domain viewpoint. Apply elementary transformation to det(M) where M=[λ1- J(Xe)], the characteristic equation of the overall system can be expressed as:

1

1

det( )[det( )] for master-slave schemedet( ) 1det( )[det( )] ( ) for democratic scheme

N

N

p

A BM

A B λτ

−

−

⎧⎪= ⎨ +⎪⎩

(1)

where A and B can be found in [6]. This equation shows the system stability is equivalently determined by two low-order subsystems which are represented by det(A)=0 and det(B)=0, respectively.

III. COMMON- AND DIFFERENTIAL-MODE LOOP GAINS

A. Common-mode Loop Gain Let

cm c cmˆˆ ˆ ˆ[ , , ]y i v v= , and the equivalent subsystem

corresponding to A is: ˆ ˆ[ ]dy dt A yλ= − 1 . This set of equations essentially represents the small-signal model of a standalone voltage-mode buck converter in Fig.3. However, it is not related to current-sharing loop parameters, implying that it corresponds to common-mode stability [2, 6]. Clearly, derivation of Tcm(s) is the same as that of the voltage loop gain for the standalone buck converter, as shown in Fig. 4, and Tcm(s)=-Gc(s)FmGvd(s), where Fm is the modulator gain, and Gvd(s) is the control-to-output voltage transfer function.

L

C N NR ovcmi

D

rampv

xR

yRcmv

refV

er

E

S or

cNrcv

Figure 3. Equivalent standalone buck converter corresponding to

subsystem A

oˆ ( )v s( )cG srefˆ ( )V s

mF ( )vdG scmˆ ( )v s cmˆ ( )d s

Figure 4. Block diagram of common-mode loop

B. Differential-mode Loop Gain Let

dm dm csˆ ˆ ˆˆ [ , , ]z i v v= , and the equivalent subsystem

corresponding to B is: ˆ ˆ[ ]dz dt B zλ= − 1 . The parameters in the compensator of voltage loop and low pass filter of current-sharing loop are involved, implying that this subsystem corresponds to differential-mode stability [2,6]

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Applying Laplace transformation and substituting

dm dmˆˆ ( ) ( ) Pv s d s V= into the results, we obtain

* dm

dm

ˆ ( )( ) ˆ ( )o

idi s E r IG s

sL rd s−= =+

(2)

dm

cs

ˆ ( )' ( ) 1ˆ ( )

dc d

z

v s kkG s k kv s sτ

= = + + (3)

where * ( )idG s is control-to-inductor current transfer function in the differential-mode sense. Then, the differential-mode loop gain Tdm(s) can be constructed, as shown in Fig.5, where

refˆ ( )I s can be regarded as a virtual

reference for dmˆ ( )i s . From Fig.5, Tdm(s) is of the form:

*

dm ( ) ( ) ' ( ) ( )c m idT s H s G s F G s= − (4)

dmˆ ( )i s( )cG s′ref

ˆ ( )I smF * ( )idG s( )H s csˆ ( )v s dmˆ ( )v s dm

ˆ ( )d s

Figure 5. Block diagram of differential-mode loop

C. Integrated Small-Signal Model

L

/C NNR oˆ ( )v s

cm dmˆ ˆ( ) ( )i s i s+

ˆ( )e s

r

ˆ( )Id s

ˆ( ) ( )oE r I d s−1: D

( )H s

refˆ ( )V s

refˆ ( )I s

csˆ ( )v s

( )cG sˆ( )d s

mF

( )cG s′ dmˆ ( )i s

oˆ ( )v s

mF

cmˆ ( )d s

dmˆ ( )d s dmˆ ( )v s

cmˆ ( )v s

dmˆ ( )i scNr

ˆ ( )cv s

Figure 6. Integrated small-signal model using an equivalent standslone

buck converter

Furthermore, the system with identical converters can be topologically decomposed into N identical constituent converters including individual voltage and current-sharing loops if the following assumptions hold. First, the inductor current

cmj dmjˆ ˆ ˆ( ) ( ) ( )ji s i s i s= + . Second, for identical

converters, cm1 cm2 cmˆ ˆ ˆ( ) ( ) ( )Ni s i s i s= = . Third, equation

(2) shows that differential-mode currents are independent of the load, and hence dm1 dm2 dm

ˆ ˆ ˆ( ) ( ) ( ) 0Ni s i s i s+ + = . As a result, the integrated small-signal model which covers Tcm(s) and Tdm(s) can be illustrated in Fig.6. Tcm(s) can be

readily found by setting dmˆ ( ) 0i s = , whereas Tdm(s) can be

found by setting cmˆ ( ) 0i s = and ˆ ( ) 0ov s = simultaneously.

IV. STABILITY ANALYSIS AND EXPERIMENTAL RESULTS Two paralleled voltage-mode buck converters have been constructed. The nominal values are: E = 18 V, L = 192 µH, rl = 64 mΩ, ro = 0.1Ω, Rs = 30 mΩ, C = 670 µF, rc =8 mΩ, R = 2.5 Ω, Vref = 2 V, kd = 5, VP= 3 V, and T = 20 µs. Moreover, for the PI compensator and low pass filter [6]: Rz=3.7 kΩ Cz=0.1µF, kcs=0.2 and τp=0.6 ms.

A. Stability Analysis Fig.7 (a) shows the magnitudes and phases of Tcm(s) for three different k values for τp = 0.6 ms. As can be seen, the system operates in stable operation, critical stability boundary and common-mode instability for k = 0.15, kcm (kcm is the critical value of k when Tcm(s) loses stability) and k = 0.4. Fig.7 (b) shows the magnitudes and phases of Tdm(s) for the same k values.

(a) Tcm(s)

(b) Tdm(s)

Figure 7. Schematic of offline inverter system

103

104

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0

10

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Mag

nitu

de(d

B)

ωc

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Frequency(rad/sec)

Pha

se(d

eg)

k=0.15 k= k

cm

k=0.40

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0

10

20

30

Mag

nitu

de(d

B)

ωd

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Pha

se(d

eg)

k=0.15 k= k

cm

k=0.40

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Clearly, the differential-mode instability does not occur for all three k values. For τp = 2.8 ms, Figs.8 (a) and (b) show the frequency response of Tcm(s) and Tdm(s), respectively. As can be observed, the system operates in stable operation for k = 0.12, and Tdm(s) has a lower bandwidth compared to Tcm(s). For k=kdm, Tcm(s) maintains stable, but Tdm(s) is at critical stability boundary. For k = 0.28, both Tcm(s) and Tdm(s) are unstable.

(a) Tcm(s)

(b) Tdm(s)

Figure 8. Simulation results of passive and hybrid filters

B. Experimental Results Figs.9 show experimental waveforms of inductor currents and output voltage for stable operation (interleaving fashion), common-mode instability and differential-mode instabilities.

1i 2i

ov

(a) Stable operation for k=0.1 and τp = 0.6 ms

2i1i

ov

(b) Common-mode instability for k=0.27 and τp = 0.6 ms

1i

2i

ov

(c) Differential-mode instability with master-slave control when k=0.26 and τp = 2.8 ms

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nitu

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B)

ωc

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Frequency(rad/sec)

Pha

se(d

eg)

k=0.12 k= k

dm

k=0.28

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nitu

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B)

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se(d

eg)

k=0.12 k= k

dm

k=0.28

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1i

2iov

(d) Differential-mode instability with democratic control when k=0.24 and

τp = 2.8 ms

Figure 9. Experimental Waveforms for a system of two paralleled buck converters (i1 and i2: 1A/div; vo: 2V/div; time: 20 µs/div and 500 µs/div for

stable and unstable operations, respectively)

Figure 10. Bode plot of Tdm(s) when k=0.15 and τp = 2.5 ms

Furthermore, a larger bandwidth of Tdm(s) results in faster dynamic response of current-sharing loop if a relatively large kcs is used, as shown in Fig.10. In this case, once the differential-mode instability occurs (as a result of increasing k), the oscillating frequency of the inductor currents correspondingly increases. For illustration, Figs.11 shows the waveforms of differential-mode instability when the bandwidth of Tdm(s) is relatively large. As can be observed, i1 and i2 for the system with the master-slave scheme tend to oscillate in phase for larger kcs due to the non-symmetrical structure, as shown in Fig.11 (a). Nevertheless, the difference between the amplitudes of i1 and i2 still exist because slow transient response exhibits in the current-sharing loop as a result of relatively large τp. On the other hand, i1 and i2 for the system with democratic

scheme oscillate in antiphase due to the symmetrical structure of the control loops, as shown in Fig.11 (b).

1i

2i

ov

(a)With master-slave control, k=0.2, kcs=1.6.

1i 2i

ov

(b)With democratic control, k=0.19, kcs=2.0.

Figure 11. Experimental waveforms of differential-mode instability when the bandwidth of Tdm(s) is relatively large and and τp = 2.5 ms

C. Stability Boundary Fig.10 shows the measured differential-mode stability boundaries for τp = 2.8 ms. For comparison, we also show the analytically computed stability boundaries by using the proposed loop gains. Unstable region and stable region are located above and below the line, respectively. The results here verify the validity of the loop gain analysis for locating the stability boundary of the system. The discrepancies can be attributed to the inherent parameters' mismatch, such as in the on-resistance of the switch.

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0

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Mag

nitu

de(d

B)

ωd

103

104

-180

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Frequency(rad/sec)

Pha

se(d

eg)

k cs=0.6

k cs=1.0

k cs

=1.6

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Figure 12. Calculated and measured differential-mode stability

boundary for τp = 2.8 ms

In summary, common-mode stability and differential-mode stability are determined by the constitutive converters and control loops, respectively. Since the compensator used works in voltage feedback and current-sharing loops simultaneously, interaction between the voltage loop and current-sharing loops is unavoidable. Thus, the design of this compensator should aim at avoiding the two types of instabilities. The time-domain characteristic of inductor currents for certain type of instability is related to the bandwidth of Tdm(s) and the type of active current-sharing schemes. Generally, when the system exhibits common-mode instability due to a relatively small τp, the fast dynamical response of the current-sharing loop can maintain perfect current sharing, which is characterized by inductor currents having same oscillating amplitudes and phases. On the other hand, in practice, a relatively large τp can be selected to achieve a relatively small bandwidth of the current-sharing loop, which may lead to the differential-mode instability. Consequently, when the differential-mode instability occurs, current sharing will also be disrupted as a result of slow dynamical response of the current-sharing loop, which is characterized by inductor currents having different oscillating amplitudes or phases. Note that conventional design of current-sharing loop involves assigning a sufficiently narrow bandwidth, e.g., using relatively large τp and small kcs. However, our analysis here suggests that the current-sharing loop should adopt a relatively small τp (to completely avoid the differential-mode instability) and kcs (to achieve the narrow bandwidth of Tdm(s) simultaneously.

V. CONCLUSION This work presents a more complete framework to address the loop gain analysis of paralleled buck converters

in terms of common- and differential-mode stabilities. In particular, two unified equivalent loop gains have been established in terms of construction of block diagrams and integration of equivalent model based on a standalone converter. Since no cross-coupling transfer function and impedance is involved and only two low-order loop gains need to be dealt with independently, the results obtained here enable simple and effective analysis of stability of parallel-connected buck converters.

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0.5 1 1.5 20.1

0.15

0.2

0.25

0.3

0.35

k cs

k dm

analysisexperiment for master-slave schemeexperiment for democratic scheme

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